KR101484600B1 - Counter-based multi-cycle processor control unit - Google Patents

Abstract

A counter based multi-cycle processor control apparatus is disclosed. More particularly, the present invention relates to a method of generating an instruction fetch signal by decoding a first counter value to generate an instruction fetch signal, an instruction fetch unit fetching an instruction according to the fetch instruction signal, A first counter reset signal or a second counter signal, which is determined according to a counter value corresponding to each cycle of the fetched instruction, a data path control signal generator for decoding the instruction to generate a data path control signal, And a counter reset signal generator for generating a reset signal.

Description

Counter-based multi-cycle processor control unit < RTI ID = 0.0 >

The present invention relates to a counter based multicycle processor control apparatus. More particularly, the present invention relates to a counter-based multi-cycle processor control apparatus capable of generating a control signal based on a counter.

In a conventional multi-cycle processor, a control unit is mainly designed using a finite state machine (FSM) method. Figure 1 schematically shows a conventional control unit designed using a finite state machine system.

Referring to FIG. 1, instructions from a memory are fetched into a processor and stored in an instruction register. Next, the instruction is decoded and defined as a particular state (value). The control unit determines the value of the control signals according to the defined state. The next state is redefined by the state and instruction defined in the next clock, and the value of the control signals is again determined by the next state value.

However, the control unit designed on the basis of the conventional finite state machine system includes logic for deciding the NEXT STATE by decoding the instruction and CURRENT_STATE, which complicates the decoding process and unnecessarily increases power consumption .

Further, in the case of a control unit designed on the basis of a conventional finite state machine system, in the case of a large number of states, a large number of registers are used and the area occupied by the registers is increased. In addition, Hardware Description Language) code is also long.

SUMMARY OF THE INVENTION The present invention has been made in an effort to solve the above problems, and an object of the present invention is to provide a counter-based multi-cycle processor control unit that can simplify a decoding circuit in comparison with a conventional finite- And to provide a multicycle processor control device in which occupancy area and register usage can be reduced.

The objects of the present invention are not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood by those skilled in the art from the following description.

An apparatus for controlling a counter based multi-cycle processor according to an embodiment of the present invention includes an instruction fetch unit that decodes a first counter value to generate an instruction fetch signal, fetches an instruction according to the fetch instruction signal, A data path control signal generator for generating a data path control signal by decoding the second counter value and the fetched instruction, a data path control signal generator for generating a data path control signal according to a counter value corresponding to each cycle stage of the fetched instruction, And a counter reset signal generator for generating a first counter reset signal or a second counter reset signal.

According to an embodiment, the instruction fetch unit may include: a storage unit for storing the first counter value; an output unit for receiving the first counter value stored in the storage unit and decoding the first counter value to generate the instruction fetch signal; and an output logic portion.

According to an embodiment, the storage unit may include a register, and the first counter value may include an initial counter value or a counter value that is incremented by one from the initial counter value and the initial counter value, The initial counter value may be zero.

According to an embodiment, the instruction fetch unit may further include an operation unit that generates an incremented value from the initial counter value by one, wherein the operation unit may include an incrementor or an adder, The storage unit stores the second counter value. The output logic unit receives the second counter value stored in the storage unit and decodes the received second counter value to generate a data path control signal. An operation unit receiving the second counter value stored in the second counter and generating a counter value that is one more than the second counter value, an input unit for receiving the increased counter value and the second counter value, And a second signal selector for outputting the second counter value.

According to one embodiment, the second signal selector may output the second counter value when the second signal selector receives the stop signal HALTb or the wait signal WAITb, The division may include a register, and the arithmetic operation unit may include an incrementor or an adder, and the second selection output may include a multiplexer.

According to an embodiment, the counter reset signal generator includes an operation unit receiving a counter value stored in a storage unit and calculating a counter value that is increased by one from the counter value, receiving the incremented counter value, A first signal selector for outputting a first counter value or an initial counter value, a storage unit for storing the incremented counter value outputted by the first signal selector, a plurality of counter values stored in the storage unit, And an output logic unit for generating the first counter reset signal or the second counter reset signal corresponding to each counter value.

According to one embodiment, the plurality of counter values include a third counter value included in the first counter value, the second counter value, and the second counter value, And generating the first counter reset signal when the second counter value is input and generating the second counter reset signal when the output logic unit receives the third counter value, The counter value may be a counter value corresponding to the last cycle of the instruction among the second counter values.

According to an embodiment, the first counter reset signal or the second counter reset signal is received, and an initial counter value or an increased counter value is set in accordance with the received first counter reset signal or the second counter reset signal And a counter reset unit for selecting and outputting the reset signal.

According to one embodiment, the counter reset unit receives the first counter value or the second counter value, and generates an incremented counter value which is increased by one from the first counter value or the second counter value, The first counter reset signal or the second counter reset signal and outputs the increased counter value when the first counter reset signal is received, A first counter for outputting the initial counter value when the second counter reset signal is received, and a second counter for storing the first counter value, the second counter value, the increased counter value, And a storage unit.

According to one embodiment, the operation unit includes an incrementor or an adder, the first signal selection unit includes a multiplexer, and the storage unit may include a register.

According to one embodiment, the first counter value is a counter value designated by the instruction fetch section to fetch the instruction, and the second counter value is a value indicating that the data path control signal generation section is designated to generate the data path control signal It may be a counter value.

A counter-based multiprocessor controller according to an embodiment of the present invention receives and decodes a first counter value to receive an instruction, and receives and decodes the fetched instruction and a second counter value to perform a data path control An output logic for generating a signal, an incrementer for receiving the first counter value or the second counter value and calculating a counter value that is incremented by one from the first counter value or the second counter value, A first multiplexer for receiving the incremented counter value and selecting one of the input initial count value and the incremented counter value inputted and outputting the selected initial counter value or the incremented counter value outputted by the first multiplexer, Value and a current counter value stored in a register to the register, Including but tipeul Lexus, the second multiplexer, may be to send the counter values to the register is output if the received second multiplexer inputs the stop signal or standby signal to the register.

According to the present invention, the decoding circuit can be simplified as compared with the conventional finite state machine method by providing the counter-based control unit, so that the power consumption, the occupied area and the use of the register of the processor can be reduced , And the HDL code can be simplified.

The effects according to the present invention are not limited by the contents exemplified above, and more various effects are included in the specification.

1 is a schematic diagram of a control unit using a conventional finite state machine system.
2 schematically shows a multi-cycle processor control apparatus according to an embodiment of the present invention.
Figure 3 schematically illustrates an instruction fetch according to an embodiment of the invention.
4 schematically shows a data path control signal generator according to an embodiment of the present invention.
5 schematically shows a counter reset signal generator according to an embodiment of the present invention.
6 schematically shows a counter reset unit according to an embodiment of the present invention.
FIG. 7 schematically illustrates an embodiment of a counter-based multi-cycle processor control apparatus according to an embodiment of the present invention.
FIG. 8 is a flowchart illustrating an operation when a stop signal or a wait signal is not input to the counter-based multi-cycle processor control apparatus according to an embodiment of the present invention.
FIG. 9 is a flowchart illustrating an operation when a stop signal or a wait signal is input to the counter-based multi-cycle processor control apparatus according to an embodiment of the present invention.
10 is a flowchart illustrating an operation of the counter reset unit according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention and the manner of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

In addition, each block may represent a module, segment, or portion of code that includes one or more executable instructions for executing the specified logical function (s). It should also be noted that in some alternative implementations, the functions mentioned in the blocks may occur out of order. For example, two blocks that are shown one after the other may actually be executed substantially concurrently, or the blocks may sometimes be performed in reverse order according to the corresponding function.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The singular forms as used herein include plural forms as long as the phrases do not expressly express the opposite meaning thereto. Means that a particular feature, region, integer, step, operation, element and / or component is specified, and that other specific features, regions, integers, steps, operations, elements, components, and / And the like.

Although the first, second, etc. are used to describe various components, it goes without saying that these components are not limited to these terms. These terms are used only to distinguish one element from another. Therefore, it goes without saying that the first component mentioned below may be the second component within the technical scope of the present invention.

The term " part " used in the embodiment of the present invention means a hardware component such as software or an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit) . However, 'part' is not meant to be limited to software or hardware. &Quot; to " may be configured to reside on an addressable storage medium and may be configured to play one or more processors. Thus, by way of example, 'parts' may refer to components such as software components, object-oriented software components, class components and task components, and processes, functions, , Subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. The functions provided in the components and components may be further combined with a smaller number of components and components or further components and components.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

2 schematically shows a multi-cycle processor control apparatus 1 according to an embodiment of the present invention.

2, a counter-based multi-cycle processor control apparatus 1 according to an embodiment of the present invention includes an instruction fetch unit 100, a data path control signal generation unit 110, a counter reset signal generation unit 110, (120) and a counter reset unit (130). Hereinafter, each part included in the multicycle processor control apparatus 1 according to an embodiment of the present invention will be described with reference to FIG. 3 to FIG.

3, an instruction fetch unit 100 according to an embodiment of the present invention may include an operation unit 10, a storage unit 40, and an output logic unit 50. The instruction fetch unit 100 may decode an initial counter value stored in the storage unit 40 to generate an instruction fetch signal, and fetch the instruction from a predetermined memory unit according to the fetched instruction fetch signal. The first counter value referred to herein may be a counter value designated to fetch the instruction. The storage device may include a hard disk drive (HDD), a solid state drive (SSD), a tape drive, an optical drive, a RAID array, a random access memory (RAM) But is not limited thereto, and may include semiconductor devices manufactured according to various embodiments. The instruction fetch unit 100 is preferably configured to fetch the instruction when the initial counter value is received, and the initial counter value may be "0 ". Also, the instruction fetch unit 100 may generate an instruction fetch signal to decode the counter value and fetch the instruction even for the counter value increased by one or a predetermined value from the initial counter value and the initial counter value. In this case, since the counter value increased by the operation unit 10 can be used to fetch the instruction, the operation unit 10 receives the initial counter value from the storage unit 40, calculates the increased counter value, After transferring the counter value to the storage unit 40, the output logic unit 50 may be configured to fetch the instruction with the incremented counter value. In other words, not only can the instruction fetch unit 100 fetch the instruction only when the initial counter value is "0 ", but if the counter value designated to fetch the instruction is input even if it is not the initial counter value, And can be configured to be withdrawn from the apparatus. The fetched instruction may be stored in the storage unit 40 and stored, for example, in an instruction register.

4, the data path control signal generation unit 110 may include an operation unit 10, a second signal selection unit 30, a storage unit 40, and an output logic unit 50. The data path control signal generation unit 110 may generate the data path control signal based on the second counter value and the fetched instruction. The second counter value referred to herein may be a counter value that is distinct from the first counter value and designated to generate the datapath control signal. The output logic section 50 may decode the fetched instruction and the second counter value to generate a datapath control signal. The second counter value may preferably be a concept comprising a plurality of counter values. In addition, the data path control signals referred to herein may be control signals for various logic units included in various data paths, but are not limited thereto. It may be a control signal for various elements included in the counter based multicycle processor control apparatus 1 or for other elements electrically connected to the counter based multicycle processor control apparatus 1. [

In order to explain the process of generating the data path control signal according to the embodiment of the present invention, it is assumed that the fetched instruction is an instruction to perform the ADD operation. If the ADD command is OPcode 0011, the embodiment in which the data path control signal generator 110 is decoded to generate the data path control signal is represented by a VHDL code based on binary representation,

always @ (*)

case ({instruction, counter})

0011_000: control_signals = 5'b11011

0011_001: control_signals = 5'b00100

endcase

. ≪ / RTI > For example, if the fetched instruction and the counter value are {instruction, counter} {0011,000}, the control signal will generate a value of "11011 " And may be a control signal for other elements electrically connected to the counter based multi-cycle processor control device 1. [ That is, upon receiving the input described in the code, a corresponding value can be found and generated as a datapath control signal. By using such a method, the counter-based multi-cycle processor control apparatus generates a control signal based on the counter value unlike the conventional control unit using the finite state machine method, And the occupied area can be reduced, and the HDL code can also be simplified. The operation unit 10, the second signal selection unit 30, and the storage unit 40 may be configured to repeatedly perform the respective functions described below to generate the data path control signal.

5, the counter reset signal generation unit 120 may include an operation unit 10, a first signal selection unit 20, a storage unit 40, and an output logic unit 50.

The counter reset signal generator 120 may be configured to generate an active counter reset signal or an active counter reset signal according to the operation cycle of the instruction. The output logic unit 50 may generate an active counter reset signal through a decoding process of the instruction and the counter value when the counter value is input to the counter corresponding to the last cycle of the instruction, The counter reset signal is not activated by decoding the instruction and the counter reset signal. The activated counter reset signal may be a signal instructing to initialize the counter value stored in the storage unit 40. [ The counter reset signal that has not been activated may be a signal that does not initialize the counter value stored in the storage unit 40. For example, the counter reset signal may be an activated counter reset signal when the counter reset signal is "1 ", or may be a counter reset signal that is not activated when the counter reset signal is" 0 ". However, this is merely mentioned for convenience of explanation, and thus the value of the counter reset signal is not limited thereto. The activated counter reset signal may be generated in the last cycle of the instruction, or otherwise a non-activated counter reset signal may be generated. That is, the counter reset signal may be generated together with the generation of the control signal, and whether the generated counter signal is the active counter signal or the not activated counter signal may be determined according to the cycle phase of the instruction. The output logic section 50 may determine whether the cycle of the instruction includes only a single cycle step or a plurality of steps, and designates a counter value corresponding to each cycle. The counter value corresponding to each cycle may be the one specified by the user or automatically generated by the output logic unit 50 in accordance with the fetched instruction when fetching the instruction from the instruction fetch unit 100 .

For example, if the instruction includes an instruction to perform an operation "A + B = A ", the instruction may include a total of (EQUAL) operations to add a value to A plus the (ADD) It can be composed of two cycles. Since the step of performing the ADD operation is the first cycle of the instruction, a counter reset signal that is not activated together with the control signal for performing the ADD operation may be generated. Next, the step of performing the EQUAL operation corresponds to the last cycle of the instruction, so that a datapath control signal for performing the EQUAL operation may be generated, and an activated counter reset signal may be generated. The operation unit 10, the first signal selection unit 20, and the storage unit 40 may be configured to repeatedly perform respective functions to generate a counter reset signal.

Referring to FIG. 6, the counter reset unit 130 according to an exemplary embodiment of the present invention may include an operation unit 10, a first signal selection unit 20, and a storage unit 40. The first signal selection unit 20 may receive a counter reset signal generated by the output logic unit 50. When the activated counter reset signal designated to reset the counter value is input, the first signal selector 20 sets the initial counter value "0" among the counter value increased by the operation by the operation unit 10 and the initial counter value, Can be selected and output. The initial counter value is stored in the storage unit 40 so that the counter value can be initialized. On the other hand, when the non-activated counter reset signal is input, the increased counter value can be selected and output.

The operation unit 10 according to an embodiment of the present invention may perform an operation of receiving and incrementing a counter value. According to an embodiment of the present invention, the input counter may be configured to perform an operation of incrementing the input first counter value or the second counter value by one. The operation unit 10 of the present invention may preferably be composed of an incrementer 10_1. The incrementer 10_1 can perform a function of incrementing the counter value by one.

Further, according to another embodiment of the present invention, the arithmetic unit 10 may be constituted by an adder. The adder may be, for example, a sum which is a result of adding one digit binary number and a signal processing circuit for calculating whether a carry has occurred or not.

The first counter value referred to herein may be a counter value designated to fetch the instruction. The second counter value may be a counter value designated to generate the datapath control signal. However, the counter reset signal generator 120 may be configured to generate the counter reset signal that is activated when the counter value corresponds to the last cycle of the instruction among the second counter values. The initial counter value may preferably be "0 ", and the first counter value may be a concept including an initial counter value. In other words, the first counter value may coincide with the initial counter value, and in some embodiments, the first counter value may be a concept that includes the initial counter value.

The first signal selector 20 may be electrically connected to the calculator 10, which may be configured as an incrementer 10_1. The first signal selection unit 20_1 may be configured to receive an initial counter value or an incremented counter value output by the operation unit 10. [ The first signal selector 20 may be configured to receive a counter reset signal. When the activated counter reset signal is received, the first signal selector 20 can select and output an initial counter value, It may be possible to select and output an incremented counter value output by the operation unit 10. [ In this case, the counter value stored in the storage unit 40 becomes "0" and the counter value is reset to the initial state I can go back. It is preferable that the initial counter value input to the first signal selection unit 20 be input to the initial counter value stored in the storage unit 40. However, It does not. The first signal selector 20 may be composed of a multiplexer 20_1.

The second signal selection unit 30 may perform a function similar to that of the first signal selection unit 20 in that the second signal selection unit 30 selectively outputs the input signal. The second signal selector 30 may be configured to selectively output any one of a counter value output by the first signal selector 20 and a counter value directly input from the storage unit 40 . Here, the "direct input" means that the counter value stored in the storage unit 40 is directly input to the second signal selection unit 30 without passing through the operation unit 20. [ That is, the current counter value that has not been increased. The second signal selection unit 30 may be configured to output the current counter value directly input from the storage unit 40 when the stop signal HALTb or the wait signal WAITb is input. The stop signal HALTb or the wait signal WAITb may be an active low signal and the counter value may be configured to maintain the current counter value if either the stop signal or the wait signal is in an active state. The second signal selector 30 may be configured as a multiplexer 30_1.

The storage unit 40 may include at least one register 40_1. The register 40_1 may be configured to receive a clock pulse. The register 40_1 may store a command word or data read from a main memory (not shown) capable of storing predetermined data or the like, or may store a result of the operation. The register 40_1 may be classified into an address register, a program counter, a data register, an instruction register and an accumulator. An address register can store a memory address to read data from or write data to memory. The program counter may store the memory address where the next instruction to be executed is stored. The data register can store the data read from the memory. The instruction register can store the instruction read from memory. The register 40_1 may include a register having various functions in addition to the described register. The register 40_1 includes a data type field capable of storing data type bits and a data field capable of storing data. Here, the data type bit may be a bit for indicating the type of the data. The data type may be related to the size of the data or the sign / sign.

The storage unit 40 may store an initial counter value, a first counter value, a second counter value, and an incremented counter value according to an embodiment of the present invention. The initial counter value may be stored in the storage unit 40 in advance. The storage unit 40 may be configured to receive a clock pulse. The storage unit 40 may output the counter value according to the clock pulse input to the storage unit 40.

For example, if the VHDL code is used to decode the output logic unit 50 according to an embodiment of the present invention,

always @ (*)

casex ({instruction, counter})

xxxx_000: control_signals = 6'b010000; // instruction fetch

xxxx_001: control_signals = 6'b001000; // instruction fetch

0111_010: control_signals = 6'b000110; // add 1 cycle

0111_011: control_signals = 6'b000101; // add last cycle

Endcase

. ≪ / RTI >

When the input value is {instruction, counter} {xxxx, 000}, {xxxx, 001} in the output logic unit 50, control signals for fetching the instruction are generated, It is possible to generate control signals that operate. If the ADD instruction consumes two cycles except for instruction fetch, the control signal bit corresponding to counter_reset in {0011,011} can be set to '1'. In the above code, the least significant bit may be the counter_reset bit, each one of which may be the element's control signal. That is, the control_signals may include an instruction fetch signal, a datapath control signal, and a counter reset signal. In the above code, for example, two of the six bits may be an instruction fetch signal, three bits may be a datapath control signal, and the last bit may be a counter_reset signal. However, it should be apparent to those skilled in the art that the structure of the present invention is not limited to the above embodiments, for example, when the instruction fetched for the description of the present invention is an ADD instruction.

7 schematically shows an embodiment of a counter based multicycle processor control apparatus 1 according to an embodiment of the present invention.

7, the operation unit 10 is connected to the incrementer 10_1, the signal selectors 20 and 30 are connected to the multiplexers 20_1 and 30_1, and the storage unit 40 is connected to the registers 40_1 and 30_1, ), And the output logic section 50 may be composed of the output logic 50_1 configured with logic for performing the above-described decoding. Since the above description is the same as described above, a detailed description will be omitted.

FIG. 8 is a flowchart illustrating an operation in a case where a stop signal or a wait signal is not inputted to the counter-based multi-cycle processor controller according to an embodiment of the present invention.

Referring to FIG. 8, a first counter value is received, an instruction is fetched (S100), a second counter signal is received, a second counter signal and an instruction are decoded to generate a control signal (S110). In operation S120, the counter reset signal generator 130 generates an active counter reset signal in operation S130, if it is the last cycle of the instruction. However, if not the last cycle, a counter reset signal that is not activated is generated and a control signal is generated. Upon receipt of the activated counter reset signal, the counter value selector 30 outputs the initial counter value (S140), stores the initial counter value in the storage unit 40, and the counter based multicycle processor controller returns to the initial state (S150). The determination as to whether or not the instruction is the last cycle of the instruction may be made based on the counter value specified for each cycle as described above. That is, the output logic unit 50 can generate an activated counter reset signal when the counter value corresponding to the last cycle is input. The counter value corresponding to each cycle may be stored by the output logic section 50.

FIG. 9 is a flowchart illustrating an operation when a stop signal or a wait signal is input to the counter-based multi-cycle processor control apparatus according to an embodiment of the present invention.

Referring to FIG. 9, step S110 of fetching an instruction (S100) and decoding a second counter value and an instruction to generate a control signal (S110) may be the same as when no stop signal or wait signal is input. When a stop signal or a wait signal is input, the second signal selector 30 selects and outputs the current counter value stored in the storage unit 40 (S210), thereby maintaining the current counter value The same data path control signal may be generated (S220). If both the stop signal and the standby signal are not inputted, the increased counter value may be decoded to generate the data path control signal (S125)

10 is a flowchart illustrating an operation of a counter value selection unit included in the counter based multicycle processor control apparatus according to an embodiment of the present invention.

Referring to FIG. 10, the first signal selector 20 included in the calculator 10 can receive the increased counter value and the initial counter value (S300). In addition, the first signal selector 20 receives the counter reset signal and determines whether the counter reset signal is an active reset signal or a non-activated reset signal (S320). In the case of the activated reset signal, the initial counter value is outputted (S330), and if the reset signal is not activated, the increased reset signal may be output (S340).

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description, and all changes or modifications derived from the meanings of the claims and their equivalents are included in the scope of the present invention. .

1: Counter-based multi-cycle processor control unit
100: Instruction fetch unit
110: Data path control signal generation unit
120: Counter reset signal generation unit
130: counter reset section
10:
20: First signal selector
30: second signal selector
40:
50: output logic section

Claims (15)

An instruction fetch unit that decodes the first counter value to generate an instruction fetch signal and fetches instructions according to the fetch instruction fetch signal;
A data path control signal generator for generating a second counter value and decoding the second counter value and the fetched instruction to generate a data path control signal;
And a counter reset signal generator for generating a first counter reset signal or a second counter reset signal, the counter reset signal being determined according to a counter value corresponding to each cycle of the fetched instruction. The method according to claim 1,
The instruction fetch unit
A storage unit for storing the first counter value; And
And an output logic unit receiving the first counter value stored in the storage unit and decoding the first counter value to generate the instruction fetch signal. 3. The method of claim 2,
Wherein the storage comprises a register. 3. The method of claim 2,
Wherein the first counter value includes an initial counter value or a counter value that is incremented by one from the initial counter value and the initial counter value,
Wherein the initial counter value is zero. 5. The method of claim 4,
Wherein the instruction fetch unit further comprises an operation unit for generating a value that is increased by one from the initial counter value,
Wherein the operation unit includes an incrementor or an adder. The method according to claim 1,
Wherein the data path control signal generator comprises:
A storage unit for storing the second counter value; And
An output logic unit receiving the second counter value stored in the storage unit and decoding the input second counter value to generate a data path control signal;
An arithmetic unit for receiving the second counter value stored in the storage unit and generating a counter value that is incremented by one from the second counter value; And
And a second signal selector for receiving the incremented counter value and the second counter value and outputting the incremented counter value or the second counter value. The method according to claim 6,
Wherein the second signal selector outputs the second counter value when the second signal selector receives the stop signal (HALTb) or the wait signal (WAITb). The method according to claim 6,
Wherein the storage unit includes a register,
Wherein the operation unit includes an incrementor or an adder,
Wherein the second signal selector comprises a multiplexer. The method according to claim 1,
Wherein the counter reset signal generator comprises:
An operation unit receiving a counter value stored in the storage unit and calculating a counter value that is increased by one from the counter value;
A first signal selector for receiving the incremented counter value and outputting the incremented counter value or the initial counter value;
A storage unit for storing the incremented counter value outputted by the first signal selector; And
And an output logic unit receiving a plurality of counter values stored in the storage unit and generating the first counter reset signal or the second counter reset signal corresponding to each of the input plurality of counter values, Device. 10. The method of claim 9,
Wherein the plurality of counter values include a third counter value included in the first counter value, the second counter value, and the second counter value,
When the output logic unit receives the first counter value and the second counter value, generates the first counter reset signal,
When the output logic unit receives the third counter value, generates the second counter reset signal,
Wherein the third counter value is a counter value corresponding to a last cycle stage of the instruction among the second counter values. The method according to claim 1,
A counter reset circuit which receives the first counter reset signal or the second counter reset signal and selects and outputs an initial counter value or an increased counter value in accordance with the received first counter reset signal or the second counter reset signal, Lt; RTI ID = 0.0 > of: < / RTI > 12. The method of claim 11,
Wherein the counter reset unit comprises:
An operation unit that receives the first counter value or the second counter value and generates the incremented counter value that is incremented by one from the first counter value or the second counter value;
The first counter reset signal or the second counter reset signal and outputs the increased counter value when the first counter reset signal is received, A first signal selector for outputting the initial counter value when a second counter reset signal is input; And
And a storage unit for storing the first counter value, the second counter value, the incremented counter value, and the initial counter value. 13. The method of claim 12,
Wherein the operation unit includes an incrementor or an adder,
Wherein the first signal selector includes a multiplexer,
Wherein the storage comprises a register. The method according to claim 1,
Wherein the first counter value is a counter value designated by the instruction fetch section to fetch the instruction,
Wherein the second counter value is a counter value that the datapath control signal generator is designed to generate the datapath control signal. An output logic unit for receiving and decoding a first counter value to fetch an instruction, receiving and decoding the fetched instruction and a second counter value, and generating a data path control signal;
An incrementer that receives the first counter value or the second counter value and calculates a counter value that is incremented by one from the first counter value or the second counter value;
A first multiplexer receiving the initial counter value or the incremented counter value and selecting one of the input initial count value and the incremented counter value;
And a second multiplexer for transmitting any one of the initial counter value or the incremented counter value output from the first multiplexer and the current counter value stored in the register to the register,
And the second multiplexer outputs the counter and transmits the counter value to the register when the second multiplexer receives the stop signal or the wait signal.

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