KR20120030332A - Dsp engine with implicit mixed operands - Google Patents

Abstract

The processor includes at least one multiplier unit that can be controlled to operate in signed, unsigned, or mixed sign mode, and coupled to the multiplier unit to receive position information of a first operand and position information of a second operand. A multiplier unit mode decoder, wherein when in the mixed sign mode according to the positional information, the multiplier unit mode decoder operates to operate in a signed mode, an unsigned mode, or a combined sign / unsigned mode. Can be controlled.

Description

DSP ENGINE WITH IMPLICIT MIXED OPERANDS

The present invention relates to digital signal processing engines of digital signal processors (DSP) and / or central processing units (CPU) of microprocessors or microcomputers.

DSP engines must perform arithmetic calculations quickly. However, if precision is required in the DSP engine for certain calculations, a compromise is made. For example, 16-bit DSP engines are generally limited to 16-bit arithmetic operations. However, 32-bit operations may be supported by hardware or may be implemented by each programming. For this reason, for example, many 16-bit DSP engines provide very large accumulators, such as 40-bit accumulators, and other hardware that can provide high precision. These hardware structures combined with the multiplier can be used to perform high bit multiplication, such as 32 x 32 bit multiplication in a 16 bit DSP engine. Nevertheless, especially if high precision multiplication is required, such operations can significantly reduce the processing speed. For example, Fast Fourier Transform (FFT) operations require many such operations, and thus may require a lot of processing time. Dedicated 32-bit multipliers will require a large portion of the real area of the chip, which will increase the cost. Also, in order to operate such additional hardware, new instructions will be required.

Without changing the instruction set and with minimal changes to conventional hardware, improvements in DSP repair capabilities in conventional DSP cores are required.

According to one embodiment of the invention, the processor comprises: at least one multiplier unit which can be controlled to operate in signed, unsigned, or mixed sign mode, the multiplier unit being connected, the position information of the first operand and A multiplier unit mode decoder for receiving position information of a second operand, wherein the multiplier unit mode decoder is in signed mode, unsigned mode, or combined signed when in the mixed sign mode according to the position information; The multiplier unit can be controlled to operate in / unsigned mode.

According to another embodiment, the multiplier unit may comprise an n-bit multiplier controllable to perform signed, unsigned, or mixed sign multiplication on two input operands. According to another embodiment, the multiplier unit may include a multiplier data preprocessor and a signed multiplier coupled to the multiplier unit to independently sign or zero extend two input operands. According to another embodiment, the signed multiplier may be an n + 1 bit multiplier. According to another embodiment, the processor is configured to perform the automatic selection of the signed mode, the unsigned mode, and the signed, unsigned, or combined sign / unsigned multiplication. It may further include a control register for selecting. According to another embodiment, the location information may include information on whether a register in the plurality of working registers is an odd register or an even register. According to another embodiment, the first operand and the second operand are supplied by the data memory, and the location information may include information on whether the address of the memory is an odd address or an even address. According to another embodiment, the first operand may be selected from a first set of two consecutive registers and the second operand may be selected from a second set of two consecutive registers. According to another embodiment, the processor may further comprise a barrel shifter having a size to accommodate at least the magnitude of the result produced by the multiplier unit. According to another embodiment, the processor further comprises at least one accumulator and an adder coupled to the barrel shifter, wherein the multiplier unit, the accumulator and the barrel shifter may be part of a digital signal processing (DSP) engine. have. According to another embodiment, the processor may further include a result expansion unit coupled between the multiplier unit and the barrel shifter, and a zero-backfill coupled to the result expansion unit. According to another embodiment, the processor may further include round logic coupled to the accumulator. According to another embodiment, the DSP engine is a 16-bit DSP engine having a plurality of 16-bit registers, wherein the barrel shifter and the accumulator may each include 40 bits. According to another embodiment, the processor further comprises a microcontroller unit, wherein at least the multiplier unit may be shared by the microcontroller unit and the DSP engine to execute arithmetic microcontroller instructions. According to another embodiment, in a signed mode, the multiplier data preprocessor sign-extends all inputs; in an unsigned mode, the multiplier data preprocessor extends all inputs zero, and in a mixed sign mode. The multiplier mode decoder can instruct the multiplier data preprocessor to sign extend the input if the source is an odd register number or an odd memory address and zero extend the input if the source is an even register number or an even memory address.

According to another embodiment of the present invention, a method of performing multiplication in a processor includes a first n-bit operand from a first position to a multiplier unit that can be controlled to operate in signed, unsigned, or combined signed / unsigned mode. Providing a second operand from a second position to the multiplier unit, decoding the position for the first operand and the second operand, and signing, unsigning, or a combined sine Controlling the multiplier unit to operate in a mixed mode where de / unsign multiplication is performed according to the positions.

According to another embodiment of the method, the first operand and the second operand are stored in registers, and the location may include whether a register in a plurality of working registers is an odd register or an even register. have. According to another embodiment of the method, the first operand and the second operand are provided by a data memory, and the location may include whether the address of the memory is an odd address or an even address. According to another embodiment of the method, the first operand may be selected from a first set of two consecutive registers and the second operand may be selected from a second set of two consecutive registers. According to another embodiment of the method, a control register may determine whether the multiplier unit is to operate in the signed, unsigned or mixed mode. According to another embodiment of the method, in signed mode, the first operand and the second operand are signed extended, and in unsigned mode, the first operand and the second operand are zero extended. And, in mixed mode, the first operand and the second operand are signed extended if the operand is supplied by an odd register number or an odd memory address, and zero expanded when the operand is supplied by an even register number or an even memory address. Can be.

According to another embodiment of the present invention, a method of performing 2n bit multiplication using 4n bit data words stores a first operand for 2n bit multiplication in a first set of two consecutive registers or two consecutive memory locations. Storing a second operand for 2n bit multiplication in a second set of two successive registers or two successive memory addresses, the first set of first register or memory address and the second set Performing a first multiplication by a controllable multiplier unit using a first register or a memory address of, shifting an associated first result, and generating an associated second result; Multiplier unit controllable using one register or memory address and the second set of second registers or memory addresses Multiplier unit controllable using the second set of first registers or memory addresses and the first set of second registers or memory addresses to perform a second multiplication by Performing a third multiplication by adding the first result, the second result and the third result to produce a final result, and storing the final result in registers or memory, wherein For each multiplication, the multiplier unit can be automatically controlled according to the position of the register or memory address to operate in signed, unsigned, or combined sign / unsigned mode.

According to another embodiment of the method, the location may comprise whether the register in the plurality of working registers is an odd register or an even register. According to another embodiment of the method, the location may include whether the address of the memory is an odd address or an even address. According to another embodiment of the method, a control register may determine which mode of the multiplier unit to operate in signed, unsigned, and mixed sign modes. According to another embodiment of the method, in the signed mode, all inputs to the multiplier unit are signed extended, and in mixed sign mode, the input to the multiplier unit is such that the input is an odd register number or It can be signed extended if provided by an odd memory address, and zero expanded if its input is provided by an even register number or even memory address. According to another embodiment of the method, the second result and the third result are shifted, and a method of performing 2n bit multiplication using 4 n bit data words generates the associated fourth result, in order to generate an associated fourth result. Performing a fourth multiplication by the controllable multiplier unit using the second register or memory address of the set and the second register or memory address of the second set, wherein the fourth result is the second result. The first result may be added to the second result and the third result to generate the final result. According to another embodiment of the method, a control register may determine which mode of the multiplier unit to operate in signed, unsigned, and mixed sign modes. According to another embodiment of the method, the multiplier unit comprises a signed multiplier, in the case of signed mode all inputs to the multiplier unit are signed extended, and in the unsigned mode, the multiplier unit All inputs to are zero-extended, and in mixed sign mode, the input to the multiplier unit is signed extended if its input is provided by an odd register number or an odd memory address, and the input is an even register number or even memory. If provided by an address, it can be zero expanded.

The present invention is well adapted to fulfill the above objects as well as those inherent therein, and to achieve the goals and advantages. Many changes may be made by those skilled in the art, and such changes are included within the spirit of the invention, as defined by the appended claims.

With reference to the following description in conjunction with the accompanying drawings, it is possible to more fully understand the present invention and its advantages.
1 is a block diagram of a DSP engine according to the present invention.
2 is a block diagram of a multiplier / scaler unit.
3 is a diagram illustrating the main operations of 32-bit multiplication using a 16-bit multiplexer.
4 is a diagram illustrating an embodiment of a preprocessor of FIG. 2.
5-7 illustrate tables with multiplier operands and result formats.
8 illustrates one embodiment of a barrel shift in a block diagram.
9 is a table illustrating barrel shifter mode, direction and scale control.
10 and 11 are tables illustrating the barrel shifter mux configuration matrix.
12 is a table showing a data accumulator mux configuration matrix.
FIG. 13 is another table showing a data accumulator mux configuration matrix. FIG.
14 is a table showing examples of overflow and saturation operations.
15 is a table illustrating saturation and overflow modes.
16 is a round & data bus saturation logic block diagram.
17 is a table illustrating round mux encoding and functionality.
18 is a table illustrating conventional convergent rounding modes.
Fig. 19 is a block diagram of the Find First instruction hardware.
While embodiments of the invention are described, described, and defined with reference to preferred embodiments, such references do not imply a limitation of the invention, nor do they imply any limitation. Features of the present invention are capable of significant modifications and substitutions which may occur to those skilled in the art and having the benefit of the present invention, and also include equivalents in manner and function. The embodiments depicted and described herein are by way of example only, and are not intended to fully describe and describe the scope of the present invention.

According to the present disclosure, the DSP can process 32-bit multiplication without dedicated hardware by separating each 32-bit operand into two 16-bit operands. And a plurality of multiplications, shifting and addition can be performed to obtain each 32 or 64 bit result. A DSP generally has an n-bit multiplier, where n <32, for example it may include a 17-bit multiplier. Such multipliers are configurable to perform other types of multiplications. Depending on the operands, other types of multiplications may be performed in which the multiplier must be configured. For example, in a multiplication where two operands are signed, the multiplier must be configured differently than an operation in which two operands are unsigned or only one operand is signed. . As described in more detail below, such a configuration can be accomplished in various ways.

Figure 3 shows a simple example of 32-bit multiplication using 16-bit registers and a 16-bit multiplier that can perform four signed, unsigned, and mixed signed multiplications. As shown, to get a 64-bit result, four different types of multipliers are needed. Operation 350 performs a signed multiplication because the two operands 310, 330 represent the most significant bits (MSB) or upper half of the 32 bit operands. For a 64-bit result, this operation result is shifted left by 32 bits before being fed to the adder 390. For other precision, the result of the operation may be shifted left by 8, 16, or 24 bits before being fed to the adder 390 as it executes. Operation 360 multiplies the unsigned 16-bit portion 320 representing the lower half or least significant bits (LSB) of the first 32-bit operand with the signed portion 330 representing the MSB of the second operand. Similarly, operation 370 multiplies the unsigned 16-bit portion 340 representing the lower half or LSB of the second 32-bit operand and the signed portion 310 representing the MSB of the first operand. Thus, in these two cases, operations with mixed types must be performed, where one operand is treated as a signed operand and the other as an unsigned operand. For a 64-bit result, the result of the operations 360, 370 is shifted left by 16 bits before being fed to the adder 390. For other precision various shift values are applied accordingly. Finally, depending on the precision, the lower half 320, 340 of the two operands 320, 340 representing the LSBs of the two operands must be multiplied by operation 380. Each operation result is added by operation 390 after being properly shifted to obtain an appropriate result. Additional shifting can be applied to the final result.

In order to perform the operations 350, 360, 370, 380, each multiplication may require a multiplier or reconstruction of the operand or both the multiplier and the operand. That is, the computation increases considerably since separate steps are needed to construct a multiplier or transform operands, resulting in additional steps.

In accordance with the present disclosure, an association of registers or memory locations representing a 32-bit word may be used to control the mode of operation of the multiplier, or to control the preprocessor processing operands as required by the multiplier. have. According to various embodiments of the present invention, for a DSP, operands are generally stored in specific registers or memory locations. For example, the DSP engine may use four general purpose registers or four qualified memory locations to store operands for a particular operation, such as 2n bit multiplication. Each combination of registers used to perform 2n bit multiplication may automatically trigger a particular mode of operation for the multiplier unit. It can be particularly useful if 32-bit load operations are always performed in predefined areas of a register file or memory. Thus, for example, in a DSP that uses four working registers W5, W6, W7, and W8 to store operands, a 32-bit word is always an odd register followed by an even register, such as register W5 310 and W6 320 is stored. Similarly, with memory, 32-bit words can always be stored starting with even or odd addresses, depending on the implementation. Therefore, according to this scheme, W5 and W7 (odd registers) or even addresses of memory may always be considered signed values, and W6 and W8 (even registers) or odd registers of memory will always be unsigned values. Will be considered. In performing certain operations of the DSP engine that require configuration of a multiplier unit, some of these registers or memory locations may be used.

Therefore, the specific configuration registers used to configure the mode of operation of this multiplier can be used to set each mode. For example, the configuration register may include a setting for signed multiplication and a setting for unsigned multiplication. According to various embodiments of the present invention, a third mixed mode setting is included that enables automatic selection, depending on the allocation of registers or memory address used for the first and second operands. In the case where the registers shown in FIG. 3 are allocated as shown in parentheses, the instruction using registers W5 and W7 as the first and second operands automatically selects the signed mode. In an instruction to perform a multiplication, the selection of registers W6 and W8 as the first and second operands automatically selects the unsigned mode. The selection of registers W5 and W8 causes a combination of signed and unsigned modes where W5 is treated as signed and W8 is treated as unsigned, and the selection of registers W6 and W7 is treated as signed and W6 It causes such a mode to be treated as unsigned. Similar decoding occurs when memory locations are used. Here even addresses can be used to indicate signed values, and odd addresses can be used for unsigned values. Therefore, no reconfiguration of the multiplier is needed, and the DSP engine will perform the correct results for each step needed to perform 32 bit calculations with the "low bit" DSP engine.

Various implementations facilitate the execution of the signed extended accuracy algorithm. For example, once the multiplier is configured to automatically set operand mode, extended precision multiply-accumulate (MAC) class instructions and cross-multiplies can be used without concern for operand type. , Can be executed sequentially.

The following typical DSP instructions can be used with this specially configurable DSP engine.

command Algebraic Operations ED A = (x-y) ² EDAC A = A + (x-y) ² MAC A = A + (x * y) MPY A = x * y MPY.N A = -x * y MSC A = A-x * y

However, other instructions may also benefit from additional modes of operation. For example, a combined processor core with DSP function and microcomputer or microprocessor function may also use the same concept for non-DSP instructions or all instructions, as described in more detail below. It is available. In another embodiment of such a processor, only DSP instructions may be provided for this mechanism, while some types of microcontroller or microprocessor instructions may require manual setting.

By adding a mode to the DSP engine that associates a particular register with a signed or unsigned data type, the registers can be selected based on a 32-bit data alignment. Therefore, a multiply operation will be implicitly signed or unsigned based on the data source. According to one embodiment of the present invention, four major elements may be used to achieve certain preferred embodiments in accordance with the present disclosure.

1) 4 x 16 bit CPU registers

2) 17 x 17 bit multiplier (can also be a 16x16 bit multiplier with signed / unsigned mode control)

3) Multiplier data preprocessor used for sign or zero extended input data

4) DSP engine multiplier mode decoder

According to one embodiment, to select a signed, unsigned or mixed sign operation, the DSP engine multiplier mode decoder decodes the user control bits. In this embodiment, an n + 1 bit multiplier is used which always operates in signed mode. The preprocessor may also change the input operands from n bits to n + 1 bits, where the most significant bit is used as a sign. In signed mode, it causes the multiplier data preprocessor to sign-extend all input data (17 bits). To sign extend the operand to 17 bits, the MS bits of the operand are copied to the seventeenth bit. In unsigned mode, it causes the multiplier data preprocessor to zero out all input data (17 bits). To zero extend the operand to 17 bits, the seventeenth bit is simply set to zero (ie, the operand is always seen as a positive value by a 17-bit multiplier). In mixed sign mode, if the source is an odd register number or an odd / even memory address, it causes the multiplier data preprocessor input to be code-extended, or if the source is an even register number or an even / odd memory address, the multiplier data preprocessor Causes input to expand to zero.

According to one embodiment, 32-bit data is loaded into CPU registers (or memory) in an alignment manner where LS words are located in even registers (or memory addresses) and MS words are located in odd registers (or memory addresses). . As a result, in mixed sign mode, the sign of all 16-bit cross multiplies needed to complete 32 X 32-bit multiplication will be automatically selected without user intervention, e.g., DSP engine By eliminating the need to constantly switch computation modes)

1 illustrates a preferred DSP engine that may be used in accordance with the teachings of the present invention. Two 40-bit accumulators 110, 115 may be provided. Two 40-bit accumulators 110, 115, via multiplexers 120, 125, 150, 155, 190, adder 145, round logic 130, and barrel shifter 160. ) An additional multiplexer 135 connects the X data bus with the output of the round logic 130 and the barrel shifter 160. As shown in FIG. 1, the adder 145 may invalidate one input and saturate the result. The barrel shifter 160 may also receive data from the multiplexer / scaler unit 185 controllable via the added multiplexer 175, sign extension unit 165 and multiplexer 155. The provided zero-backfill unit 170 connects the X data bus to the second input of the multiplexer 175. Controllable 16-bit multiplexer / scaler unit 185 is configured via mode register 180 to operate as signed, unsigned, or mixed sign / unsign, and also to transfer data from / to a register array. I can send it. An output of the 16-bit multiplier scaler unit 185 is connected to a first input of the multiplexer 175. The mode decoder 195 provides automatic control of the controllable multiplier / scaler 185 mode of operation. To this end, the mode decoder may receive the number of registers representing the first and second operands or the addresses of the memory locations of the first and second operands. Alternatively, information of whether the address or register is odd or even may be supplied to the mode decoder. The mode decoder may use the matrix to switch the configuration mode of multiplier / scaler 185 according to this information. This automatic mode selection is controlled programmatically via the mode register 180. When each bit of the mode register 180 is set, the multiplier / scaler 185 receives the mode information directly from the mode decoder 195. Otherwise, a particular fixed mode (sign / unsign) is selected via the mode register 180. Because of this, as shown by the dotted lines in FIG. 1, the mode decoder 195 may also receive control signals from the mode register 180.

Another embodiment of the combination of multiplier / scaler unit 185 and mode decoder 195 is shown in FIG. 2. This embodiment receives two 17-bit input words and outputs a 32-bit result fed to the fractional scaler 210 which can shift the result by one bit if the operands are fractional operands. The multiplier 220 may be included. To this end, the fractional scaler 210 may be controlled by the bits of the mode control register 240. Also provided is a mixed mode operand preprocessor 230 that receives two 16-bit operands from working registers (or memory) and generates two signed 17-bit operands that are fed to multiplier 220. The results of multiplier 220 may be fed back to a register array or memory. Mixed mode operand preprocessor 230 supplies the signed operands to signed multiplier 220. The mixed mode operand preprocessor converts the input data statically or automatically, depending on the location of the data entered. The term location can be interpreted as information in which actual data is stored in such a manner. For example, in two consecutive registers or memory addresses that store two data words, one data word is always at odd numbers, the subsequent word is at even positions, and vice versa. If two words are always stored on the same area, this information (even / odd) can be used to reliably distinguish between the MS word and the LS word. As indicated by the mixed mode selection signal, this information is fed to the mixed mode operand preprocessor.

FIG. 4 is a diagram illustrating an embodiment of the preprocessor illustrated in FIG. 2. Here, sign extension unit 410 and zero fill unit 420 are provided to perform operand changes on the first and / or second operand. The comparing and selecting unit determines which units 410, 420 are used for the first and second operands. The comparison and selection unit may receive an address or memory location of a register and determine whether the location is odd or even. Alternatively, this information may be provided directly by, for example, each address bit or other means operable to forward or generate this information.

One embodiment shown in all figures represents a 16-bit DSP with 16-bit registers, 16-bit or 17-bit multipliers, and a barrel shift. These values are exemplary. The present invention is applicable to another n-bit processor having a multiplier and a plurality of n-bit registers that cannot directly process operands having a size of 2n.

According to various implementations, the DSP engine 100 may be coupled to a microcontroller unit (MCU) and may be a hardware block that receives data from a W register array but contains its own specific result registers. However, in other embodiments, data may also be supplied from memory. The DSP engine 100 may be controlled from the same single issue instruction decoder that oversees the MCU arithmetic logic unit (ALU). In addition, virtual addresses of all operands may be generated in the W register array. According to one embodiment, as a result, concurrent computation with the MCU instruction flow is possible, although both MCU ALU and DSP engines can be used simultaneously by the same instruction (eg, ED and EDAC instructions). I will not.

As shown in Figures 1 and 2, the DSP engine is a 40-bit adder / subtractor with a fast 17-bit x 17-bit multiplier 220, barrel shifter 160, and two target registers 110, 115. 145, and round / saturation logic 130. DSP engine 100 may be essentially one large asynchronous block, with only accumulator result registers 110, 115 clocked. Data input to the DSP engine 100 can be obtained from the following.

1. Directly from W array registers:

For example, among instructions, W4, W5, W6 or W7 for MAC layer

-Any W register (target accumulator A or B) for the MUL.xx layer among the instructions.

2. From the X-bus for all other DSP instructions

3. From X-bus for all MCU instructions using barrel shifter 160

Data output from the DSP engine can then be recorded.

1. Target accumulators 110, 115, as defined in the DSP instruction to be executed.

2. Write the X-buses for the MAC, MSA, CLRAC, and MOVSAC accumulators where EA is the W13 register or at [W13] + = 2 (MPY (N), SQR {AC), ED {AC). Note that no option is provided).

3. X-bus for MCU instructions using barrel shifter 160

4. A 32-bit aligned register pair write bus from multiplier 220 to the W array to support MCU multiply instructions.

The DSP engine may also have the ability to perform an accumulator inherent with accumulator operations that do not require additional data. These instructions are ADDAB, SUBAB and NEGAB.

As shown in FIG. 1, the block diagram of the DSP engine 100 is conceptual in nature and is intended for use as an aid in understanding the data flow required by the instructions exerting it. The block diagram of the actual implementation can vary considerably. For one or more particular implementations, the various units and their functionality shown in FIGS. 1 and 2 will be described below. Therefore, the preferred and specific implementations described below will not limit the scope of the present invention.

Multiplier

The 17 x 17 bit multiplier 220 is capable of a signed operation and multiplexes its output using a scaler to support 1.31 fractional or 32-bit integer results. The MAC / MSA, MPY {N}, ED {AC) and SQR {AC} operations are typically signed, but the DSP engine may be configured for unsigned or mixed code operations.

The three control bits (IF, US <1: 0>) in the 16-bit CPU core control register 240 (CORCON) are unsigned / signed for DSP and MCU multiplication instructions targeting integers / fractionals and accumulators, respectively. Determines the coded / mixed sign operation. MCU multiply instructions targeting the W array can always be considered integer operations. Scaler 210 shifts the multiplier result one bit left only during fractional operations.

Integer / Fractional (IF) Control Bits

According to one embodiment, the state of the CORCON <IF> bit in register 240 controls the operand type for DSP and MCU multiply instructions targeting accumulators 110 and 115. If CORCON <IF> = 0, multiply operands are considered fixed point 1.15 fractional values. If CORCON <IF> = 1, multiply operands are considered integer values.

If MCU instructions are targeting accumulators 110 and 115, it is assumed that they can be used in conjunction with DSP instructions, so they must inherit the same operand type. If this is not the case, the user must manually manipulate the CORCON <IF> bit accordingly.

Signed Of Unsigned  Control bits

If CORCON <US [1: 0]> = 2'bOO of the MAC / MSA, MPY {N}, ED {AC}, and SQR {AC} instructions, both operands are always sign extended to the seventeenth bit of the multiplier input value later. It is considered a signed value. In addition, the result is sign extended prior to some operations with an accumulator (which will always be signed effectively).

If CORCON <US [1: 0]> = 2'bO1 of MAC / MSA, MPY {N}, ED {AC}, and SQR {AC} instructions, both operands are always zero-extended to the 17th bit of the multiplier input value later. It is considered an unsigned value. In addition, the result is zero expanded (which will always be effectively signed) prior to some operations with an accumulator.

If CORCON <US [1: 0]> = 2'b1x in MAC / MSA, MPY {N}, ED {AC} and SQR {AC}, the operands are considered as signed or unsigned values depending on the W register source. . If the W register source is odd (W5, W7), the operand is assumed to be signed. If the W register source is even, the operator is assumed to be unsigned. If one or both of the operands are signed, the result is signed expanded, otherwise zero expanded (some will always be effectively signed) prior to some operation with an accumulator.

According to one embodiment, the CORCON <US [1: 0]> bits do not affect MCU multiply instructions that determine whether their own operation is signed or unsigned.

MCU Multiply Instructions

The same multipliers can be used to support MCU multiply instructions including integer 16-bit signed, unsigned, mixed sign multiplications. As shown in FIG. 2, additional data paths are provided to allow these instructions to write the results back to the W array and to the X data bus (via the W array). These passages are located prior to the data scaler 210. In addition, these instructions may also target accumulators 110, 115. Since the operands may be fractions (CORCON <IF> = 0), these passages may be located behind the data scaler 210. That is, the result will be scaled to normal based on the state of the IF bit. All MCU multiply operations explicitly identify signed or unsigned operations. MCU multiply instructions may write a full 32-bit result into an evenly arranged W register pair or only LS 16 bits of the result into a single (even) W register based on the instruction destination field encoding.

According to some embodiments, for 32-bit results, the destination register pairs for the MCU multiplies will be sorted (ie odd: even), where 'odd' contains the MS result word and 'even' contains the LS result word. . In such an embodiment, W3: W2 may be allowed, but \ 4: W3 is not allowed and will be indicated by the assembly as an error. Similarly, for 16-bit results, the destination register can be an even value. For example, W6 may be allowed, but W7 is not allowed and will be indicated by the assembler.

According to one embodiment, an unsigned multiply instruction is instructed to use byte or word scale operands. The destination can always be a W3: W2 register pair in the W array. Byte operands direct the 16-bit result to W2 (W3 unchanged), and word operands direct the 32-bit result to W3: W2.

For example, the simple data preprocessing logic shown in FIG. 4 zeros or sign extends the operands to 17 bits so that unsigned, signed or mixed sign multiplications can be performed with signed values.

According to one embodiment, all unsigned operands can always be zero extended to the seventeenth bit of the multiplier input value. All signed operands can always be signed extended to the seventeenth bit of the multiplier input value. According to one embodiment, for signed 16-bit multipliers, multiplier 220 produces 30 bits of data and 2 bits of sign, which are provided to scaler 210. If the instruction is operating in integer mode, the result is unchanged and output from the multiplier block as a 32-bit signed number. If the instruction is operating in fractional mode (DSP ops and MCU multiply ops targeting DSP accumulators when CORCON <IF> = 0), the result is shifted 1 bit to the left (ie, it leaves 1 bit of sign). box). For fractional multipliers, bit 0 of the result is always zero. For 16-bit mixed mode (sign / unsign) multipliers, the multiplier produces 31 bits of data and 1 bit of sign. For unsigned 16-bit multipliers, the multiplier produces a 32-bit unsigned result.

5 through 7 are tables showing how operands are treated for each multiply type and the corresponding result format generated. For MCU multiply instructions targeting only one (even) W register, the resulting LS word, R <15: 0>, is written to the target register. The remaining MS bits are discarded.

Barrel Shifter

8 is a block diagram of a 40-bit barrel shifter 160 that can perform up to 16-bit arithmetic right shift or 16-bit left shift in a single cycle. The source may be either the two DSP accumulators 110, 115 or the X-bus (to support the multi-bit shift or memory data of the register). To support various requirements for DSP or MCU multibit shift instructions, the shifter 160 may be custom designed specifically to include two modes of operation. The operating mode is controlled by the BIDIR signal.

In a first mode that can be used by all MCU shift instructions (ie, all shift instructions except SFTAC and SFTACK), barrel shifter 160 has a 5-bit shift scale value, SFTNUM <4: 0> and an indication. Accept the signal L_R. If L_R = O, shifter 160 will shift the input operand left by the number of bits defined by SFTNUM <4: 0>. If L_R = 1, shifter 160 will shift the input operand to the right by the number of bits defined by SFTNUM <4: 0>. 9 is a table showing direction and scale control as well as shift range according to control signals.

The MCU multibit shift instruction has two layers, one with a constant shift value and the other with a variable shift value. Certain shift instructions ASRK, LSRK, SLK contain a 4-bit scale character field that limits the shift range to be between 0 and 15. Variable shift instructions (ASRW, LSRW, SLW) use the W register as the source of the shift magnitude. The shift operation will be organized so that the shift result is correct for all values. When shifting a data value to 16 bits larger than 15 bits, a useful shift range is between 0 and 15, as it is the same as clearing or setting it.

In the second mode, which can be used by the remaining remaining DSP shift instructions SFTAC and SFTACK operating only on 40-bit DSP accumulators, the shifter is applied to a 6-bit two's complement signed shift value representing the magnitude and direction of the shift operation. Instructed by The shift direction and sign correspond to those required for data normalization.

In this mode, the L_R signal becomes a sign bit (and consequently still indicating the shift direction), and SFTNUM <4: 0> is the shift value LS 5 bits, representing the shift magnitude. For positive (L_R = 0, right shift) values, the shifter will shift the target accumulator to the right by the number of bits defined by SFTNUM <4: 0> from 0 to a maximum of 16. For negative ((L_R = 1, left shift) values, the shifter will shift the target accumulator left by two's complement of the number of bits defined by SFTNUM <4: 0> from 0 to a maximum of 16. The table of 9 describes the direction and scale control as well as the shift range according to the control signals.

In this mode, the DSP multi-bit shift instruction has two layers, one with a constant shift value (SFTACK) and the other with a variable shift value (SFTAC). The assembler will prevent attempts to use SFTACK instructions with shift values greater than 16 or less than -16. For SFTAC instructions, the maximum shift magnitude is limited by hardware with shift values greater than 16 or less than -16. Attempts to execute an SFTAC instruction with a shift value outside the valid range will result in a math error trap. If this occurs, the attempted shift result will not be written to the target accumulator. Attempts to execute SFTACK instructions with shift values outside the valid range (eg, by manually manipulating the instruction character field) will not be disturbed. The command will be executed, but it will not produce correct results. Since the SFTAC range is limited because the target DSP accumulator is 40 bits wide, shift values larger than 16 bits can produce meaningful results (i.e. it may not be zero or all 1's complement, MCU multi May be the case for bit shift ops). That is, MCU variable multi-bit shift instructions can accept any shift scale and still get the correct result, but this is not the case with SFTAC instructions without extending the shifter 160 range.

It is also possible to shift the signed value in the accumulator so that the sign is removed. If the barrel shift result then passes through the saturation logic normally, it will produce a false saturation result based on the new sign. However, the shifter 160 includes logic to check the shifted bit to the left beyond bit 39 so that a catastrophic overflow is accepted based on the sign of the original data value and saturation is applied correctly. For example,

; Assume that Q31 saturation is enabled.

; And AccA = Ox0078AA0000

SFTAC A, # 9

; Ox007FFFFFPF-> AccA, SA = 1

; AccAii9 = OxP554000000 However, if a bit 39 overflow is detected, the SA is set and saturated to the maximum positive (original AccA [39] = 0) Q31 value.

Multibit MCU Shift Instructions ASRK, LSRK and SLK provide an unsigned 4-bit shift value from the instruction character field. The instructions zero extend this value into 5 bits so that SFTNUM <5: 0>. The instruction shift direction determines L-R. Multi-Bit MCU Shift Instructions ASRW, LSRW and SLW extract the unsigned 4-bit shift value from the LS 4 bits of the W register Wb. The instructions zero extend this value into 5 bits so that FTNUM <5: 0>. The instruction shift direction determines L-R. The shifter mode signal BIDIR is cleared for these instructions. If some of the remaining MS 12 bits of Wb are set (which indicates a shift value greater than 15), then the shift result will be forced to zero or all 1's complement (the ASRW when the MS bit of the original operand is set). For).

The multibit DSP shift instruction SFTACK provides a two's complement signed 6 bit shift value from the instruction character field. The MS bits of this value are assigned to L_R, and the remaining 5 bits are assigned to SFTNUM <4: 0>. This shifter mode signal, BIDIR, is set for this command. Shift values outside the effective range are not disturbed in hardware because they are not detected by the assembler.

The multi-bit DSP shift instruction SFTAC extracts a signed 6-bit shift value from the LS 6 bits of the W register Wn. The MS bits of this value are assigned to L_R, and the remaining 5 bits are assigned to SFTNUM <4: 0>. This shifter mode signal, BIDIR, is set for this command. To prevent attempts to shift beyond the maximum range of the barrel shifter, Wn is checked to confirm that the shift value is valid. If the shift value is greater than 16 or less than -16, an arithmetic error trap will be generated and the shift result will not be written to the target accumulator.

The barrel shifter 160 is 40 bits wide to accommodate the width of the accumulators. The barrel shifter 160 is used for both DSP and MCU shift operations. The resulting data is obtained from BSout40 for DSP shift operations and from BSout16 for MCU shift operations.

Data Is is rounded to and from the barrel shift so that MCU shifts can be achieved through a series of multiplexers that make up the data path. Multiplexers that achieve this data selection are referred to as M1 through M4. 10 is a table showing how the multiplexers are configured for each DSP engine instruction. 11 shows an alternative mapping in which instructions are grouped into common control blocks to demonstrate the possibility of decoding efficiency. If possible, 'don't care' states have been used to compress the decoding requirements. Redundant signals are shown by ().

Data input to the barrel shift is controlled by multiplexers M1, M2 & M3 (combined as mux N6 in FIG. 1) and can be one of the following sources:

1. Accumulator

2, the output of the multiplier sign expansion unit

3. Zero

Data from the X-bus is provided in a barrel shift, between bit positions 16 through 31 for right shifts and between bit positions 0 through 15 for left shifts. Therefore, a maximum range (16 bit left to 15 bit right) operation can use all multibit calculations or logical shift operations on data memory or registers.

data Accumulator  And adder / subtractor

Data accumulator block 100 includes a 40-bit adder / subtractor 145 with automatic result (zero or sign) expansion logic for multiplier results. The 40-bit adder / subtractor 145 may select either of the two accumulators 110, 115 (A, B) as its pre-accumulation source and post-accumulation destination. As shown in FIG. 1, for ADDAC and LAC instructions, data to be accumulated or loaded may optionally be scaled through barrel shift 160 prior to accumulation.

The data adder block 100 shown in FIG. 1 is in fact conceptual and intended only for use as an aid in understanding the data flow required by the instructions exerting it. The block diagram of the actual implementation can vary considerably.

For each of the DSP instructions, several mapped data path selection and function control signals are shown in FIG. 12. An alternative mapping is shown in FIG. 13, where instructions are taken to common control blocks to demonstrate the possibility of decoding efficiency. If possible, the 'don't care' state has been used to compress the decoding requirements (invalid control signals are ignored for this activity). Redundant signals are shown by ().

Result expansion block

When the DSP engine is operating in signed mode (US = 1), the result extension block 165 sign extends the provided 32 bit number to 40 bits. When the DSP engine operates in unsigned mode (US = 0), the result extension block 165 zero-extends the provided 32-bit number to 40 bits. According to one embodiment, the barrel shifter 160 will also need to be able to force the resulting zero expansion. However, this can be accomplished in a variety of ways.

Zero back-fill

To simplify the system description, zero back-fill block 170 always associates 16 at least significant zeros from the X-bus onto the word read. In addition, the barrel shifter 160 is presented to have the same capability. This is again designed and implemented and can be accomplished in a variety of ways.

Adder / subtractor, Overflow  & Saturated

Adder / subtracter 145 is a 40-bit adder that has an optional zero input with one input and real or complement data with another input. The adder 145 can also receive a carrier of the signal, which can be high or low, which must latch and generate two overflow status bits that are rounded to the status register control block. .

The overflow to bit 39 can be used as an overflow of the cataclysm that loses the sign of the accumulator. Overflow to bits 31 to 39 can be used as a recovery overflow. This bit is set whenever any of these bits are not the same. It indicates that data values recorded in accumulators 110 and 115 can no longer be represented as 1.31 fractional values.

When selected, adder 145 has additional saturation blocks that control accumulator data saturation. To determine when and when to saturate, the adder uses the adder result, the overflow status bits described above, and the SATNB and ACCSAT mode control bits. The adder / subtractor 145 and the saturation blocks are hereinafter referred to as the DSP AU (calculation unit). According to one embodiment, when the DSP engine is operating in unsigned mode (US = 1), even if the OA, OB, SA and SB status bits (and associated saturation activity) do not contain any meaning, they are prohibited If enabled, saturation will occur based on the same rules, regardless of the signed / unsigned mode of operation of the DSP engine 100.

Six status register bits can be added to support saturation and overflow. they :

OA: AccA fractional overflow into guard bits (can no longer be represented as a 1.31 fractional value)

   OB: AccB fractional overflow into guard bits (can no longer be represented as a 1.31 fractional value)

OA and OB may be R / W bits in CORCON mode operation register 180.

2. SA: a) Normal Saturation Enable: If AccA overflows with guard bits, SA is set. AccA will saturate to a value of 1.31.

       b) Super Saturation Enable: SA is set if AccA overflows with sign (AccA <39>). AccA will be saturated to a value of 9.31.

       c) Saturation disable: SA is set when AccA overflows with sign (AccA <39>). AccA will contain the (overflowed) result of the operation. If COVTE is set, an arithmetic error trap will be generated. The trap handler can then take appropriate measures to deal with the overflow of the cataclysm.

The SA may also be R / W bits in the CORCON register 180.

3. SB: a) Normal Saturation Enable: If AccB overflows with guard bits, SB is set. AccB will saturate to a value of 1.31.

       b) Super Saturation Enable: SB is set if AccB overflows with sign (AccB <39>). AccB will be saturated to a value of 9.31.

       c) Saturation disable: SB is set if AccB overflows with sign (AccB <39>). AccB will contain the (overflowed) result of the operation. If COVTE is set, an arithmetic error trap will be generated. The trap handler can then take appropriate measures to deal with the overflow of the cataclysm.

SB may also be R / W bits in CORCON register 180.

4. OAB: logical OR of OA and OB

5. SAB: logical OR of SA and SB

When operating in the normal saturation mode (1.31), bit 31 is the sign bit of the 1.31 fraction. The bits remaining in the accumulator are not a real function and will always be sign extended from bit 31. OA / OB will never be set. When operating at super saturation (or no saturation), bit 31 becomes one of the guard bits that together provide an integer portion of the 40-bit signed fraction value. Therefore, the guard bits eat bits 31 to 38, and bit 39 is newly designated as the sign bit. Fractional overflow is detected at any time unless all guard bits and sign bits (ie, bits 31 to 39) are the same.

The OA and OB bits can be modified each time data passes through the DSP AU. If set, the OA and OB bits indicate that the most recent operation overflows with the accumulator guard bits. Also, if set, the OA and OB bits can optionally generate an arithmetic error trap, and the corresponding overflow trap flag enable bits (OVATE, OVBTE) in the INTCON1 register are set. Because of this, the user can take immediate action, for example, to correct the system gain.

OA / OB is updated based on the data value at the DSP AU output (ie, if present, post saturation). As a result, the Q31 saturation mode is selected, and even though the adder indicates that an overflow has occurred (bits 31 to 39 are always the same), the OA / OB will never be set.

OA / OB only updates the following DSP AU operations. All DSP instructions pass data through the DSP AU (and will update the OA / OB), but since the writes to the accumulator SFRs will not be passed through the DSP engine, the OA / OB will not be updated.

The SA and SB bits can be set each time data is passed through the DSP AU, but only cleared by the user or CLRAC instruction (eg they are actually 'sticky'). If set, the SA and SB bits indicate that the accumulator will overflow the maximum range (bit 31 for 32 bit saturation, bit 39 for 40 bit saturation) and will be saturated (if saturation is enabled). If saturation is not enabled, SA and SB do not transition to bit 39, indicating that catastrophic overflow occurs. If the COVTE bit in the INTCON1 register is set and saturation is disabled, the SA and SB bits will generate an arithmetic error trap.

SA and SB status bits are 'sticky'. Once set, despite the results from any subsequent accumulator based operations, the SA and SB status bits may not be cleared by the saturation logic (only by user code, eg CLRAC). Cleared). However, the accumulator content itself is not 'sticky'. This means that all subsequent operations continue to accumulate new results, ie whether the accumulator is already saturated. This results in continued saturation (e.g., the accumulator saturates to a maximum positive value, and a new accumulator attempts to add to this value), or the accumulator contents are changed (e.g., the accumulator is at maximum). Saturating to a positive value, a new accumulator attempts to subtract from this value which reduces the accumulator content by this value).

If the OA and OB bits are not 'sticky', it is based on the evaluation of the operation based on each accumulator.

Overflow and saturation status bits may optionally appear in the status register (of bit OAB) as the logical OR of OA and OB and in the status register (of bit SAB) as the logical OR of SA and SB. Because of this, the programmer can check one bit in the status register to determine which accumulator has overflowed, or can check a bit to determine which accumulator is saturated.

SAB and OAB are not latched or 'sticky'. Whenever OA or OB (for OAB) or SA or SB (for SAB) is set, they will read as one. Whenever both associated bits are valuable, they will be read as zero. However, although the SAB is not 'sticky' and the OAB is a read bit, the 'sticky' attribute of SA and SB causes the SAB to indicate 'sticky'.

The SAB can be written as a means of providing a signal to clear both SA and SB simultaneously. This clear operation does not clear the latch but alternately causes the SAB to be read as clear during the next read. The device supports three saturation and overflow modes.

1. Bit 39 Overflow and Saturation: Using the bit 39 overflow status bit from the adder, and the bit 39 value after addition, the correct sign of the 9.31 result can be determined. The saturation logic then loads the maximum positive 9.31 (Ox7FFFFFFFFF) or the minimum negative 9.31 value (Ox8000000000) into the target accumulator. The SA or SB bit is set and holds the setting until cleared by the user. This is referred to as 'super saturation' and provides protection against false data or unexpected algorithmic problems (eg gain calculations).

2. Bit 31 overflow and saturation: Using bits 31 to 39 overflow status bits from the adder, and the bit 39 value after addition, the correct sign of the 7.31 result can be determined. The saturation logic then loads the maximum positive 1.31 (Ox007FFFFFFF) or the minimum negative 1.31 value (OxFF80000000) into the target accumulator. The SA or SB bit is set and holds the setting until cleared by the user. If this saturation mode is in effect, the guard bits are not used (so the OA, OB or OAB bits are never set).

3. Bit 39 Large Fluctuation Overflow: The Bit 39 overflow status bit from the adder is used to set the SA or SB bit to hold the setting until cleared by the user. No saturation operation is performed, causing the accumulator to overflow (removing its sign). If the COVTE bit in the INTCON1 register is set, a catastrophic overflow can initiate a trap execption.

For AccA, saturation and overflow operations for all adder / subtractor modes are summarized in FIG. 14 (same logic is applied to AccB). Also, some examples are shown in FIG. 15. According to one embodiment, the saturation operation is OprB-OprA. The Boolean equation for OV39 is

OV 39 (for addition operations) = (OprA <39> && OprB <39> && AccA <39>)? ((OprA <39> && OprB <39> && AccA <39>)

OV 39 (for subtraction operations) = (OprB <39> && OprA <39> && Result <39>)？ ((OprA <39> && OprB <39> && Result <39>)

Accumulator  'Write-Back' ( AWB )

Part of the MAC layer of the instruction (exceptions are MPY, MPYN, ED, EDAC, SQR and SQWC) may optionally write a rounded version of the accumulator (not targeted by the instruction) to the data space memory. Writing is performed with the X and Y address spaces combined across the X-bus. Limited instruction decoding space limits the addressing mode options and forces an addition sign so that data is not always rounded and scaled. However, it has been found that this feature is particularly advantageous in FFT and LMS algorithms.

The following addressing modes are supported.

1. W13, Register Direct: The base content of a non-target accumulator is written to W13 as a 1.15 fraction.

2. [W13 ++], register indirection with later increment: The rounded content of the non-target accumulator is written to the address pointed to by the 1.15 fraction. W13 is then increased by two (for word writing).

According to one embodiment, the AWB operation does not change the contents of the source accumulator, and the AWB operation does not update the OA / OB or SA / SB (even if the resulting data overflows or saturates).

Round logic

Round logic is a combining block that performs conventional (biased) or convergent (unbiased) round functions during accumulator write (store). The round mode is determined by the state of the RND bit in the CORCON register 180. As shown in Figure 16, the round logic generates a 16-bit 1.15 data value that is passed to the data space write saturation logic. If rounding is not indicated by the instruction, an incomplete 1.15 data value is stored.

According to one embodiment, the rounding function only requires a 16-bit adder. The MCU ALU can use all instructions besides ED / EDAC, thus performing rounding additions that save area. This may depend on a close DSP engine or the like.

Two rounding modes are shown in FIG. Conventional rounding takes bit 15 of the accumulator, zero extends it, and adds it to the MS word excluding the guard or overflow bits (bits 16 to 31). If the LS word of the adder is between Ox8000 and OxFFFF, the MS word is incremented. If the LS word of the adder is between Ox8000 and Ox7FFF, the MS word remains unchanged. The result of this algorithm will be that the value will be biased slightly positive over a series of random rounding operations.

Convergent (or unbiased) rounding operates in the same manner as conventional rounding, except that the LS word is equal to Ox8000. If so, the LS bit (bit 16 of the adder) of the MS word is checked. If the LS bit is 1, the MS word is incremented. If the LS bit is 0, the MS word is not changed. In fact, assuming bit 16 is substantially random, then this approach will eliminate any rounding bias that may accumulate.

The SAC and SACR instructions store a truncated (SAC) or rounded (SACR) version of the contents of the target accumulator in data memory via an X-bus (subject to data saturation).

According to one embodiment, the MAC layer and accumulator write operation of the instructions will function in the same way of addressing the combined MCU (X and Y) data spaces over the X-bus (ie, the X and Y data spaces only cycle). Separated during the data read portion of Q1, Q2). For this layer of instruction, data is always subject to rounding (mode determined by the RND bit).

Data Space Record Saturation

In addition to DSP AU saturation, records into the data space will also be saturated, without affecting the content of the source accumulator. The data space write saturation logic block rounds the 16-bit 1.15 fractional value from the source accumulator to the round adder. The remaining MS bits of the source accumulator are used to generate an overflow condition of the accumulator. As shown in Figures 16 and 17, they are combined and used to select the appropriate 1.15 fractional value as the output for writing to the data space memory.

According to one embodiment, the overflow logic is independent of the DSP AU overflow logic. As a result, regardless of how the data is located in the accumulator (ie, via the DSP AU or SFR record), the content of the source accumulator will always be saturated exactly.

The SATDW bit in the CORCON register 180 is set (default), and the data (after rounding or truncation) is checked for overflow and adjusted accordingly. For input data larger than Ox007FFF, the data written to memory is forced to a maximum positive 1.15 value, Ox007FFF. For input data smaller than OxFF8000, the data written to memory is forced to a minimum negative 1.15 value, OxFF8000. The MS bit (bit 39) of the source is used to determine the sign of the operand to be checked.

In the case of rounding from bit 15 to bit 16 of the round adder, a rounding overflow (OV) can be defined.

 Since the rounding scheme used here is semantically unidirectional (ie, adding 1 or 0), the only overflow that can be tolerated is Ox7FFF to Ox8000. As a result, overflow that can be detected from the round-up of OxFFFF should be prevented. The proposed implementation shown in FIG. 16 does not cause any negative (pre-round) value to cause data space saturation in the Ox8000 except if the original guard bits (ACC <39>) are not equal to% 1111 1111 1. will be.

If the SATDW bit in the CORCON register 180 is not set, then the input data is always passed unchanged under all conditions. All data records from the DSP engine into the data space can be selectively saturated.

Power Conservation

As discussed above, DSP engine 100 may be the logic of one large asynchronous block that is essentially one in which only accumulator registers are clocked. As a result, if there is no need to consume more power than is potentially needed, there are a number of paths that can eventually be supplied and terminated for data . Although several suggested data path blocks are shown on the block diagram to highlight this point, the last position of these elements will depend on the structural implementation chosen for the final design.

DSP engine mode  Selection

The DSP engine has various modes selectable via the CPU core configuration register CORCON 180 or the interrupt configuration register INTCON1.

Modes of operation:

1. a fraction or integer

2. Signed or Unsigned

3. Conventional or Converging Rounding

4. Auto Saturation On / Off for AccA

5. Auto Saturation On / Off for AccB

6. Auto Saturation On / Off for Writing to Data Memory

7. Accumulator Saturation Mode Selection

8.Trap on overflow on / off of AccA

9. Trap on overflow on / off of AccB

10. Trap on catastrophic overflow on / off of AccA and / or AccB

DSP instruction

There are three broad layers of instructions.

1. Has scaling but no (inherent) operand

2. Single operand with scaling

3. Dual operands without scaling

In addition to instructions that increase DSP performance, the following hardware features may be included.

a. The 'REPEAT n' instruction holds the next instruction in the instruction register and then executes it 'n' times.

b. Nested 'DO' loop hardware program loop control with visible control registers for nesting support

c. "Find First" instructions that determine the first bit setting or clearing starting from the LS or MS bit

d. Modulo addressing mode associated with some working (address) registers

e. Bit reverse addressing mode for X data space writes only

"Find First" commands

There are three variants of the 'Find First' commands.

1.FF1L: Find the First occurrence of 1 starting from Left. This command may be useful for RTOS task management and other bit polling applications.

2.FF1R: Find the First occurrence of 1 starting from Right. This command may be useful for RTOS task management and other bit polling applications.

FBCL: Find the first occurrence of Complement of the MS-bit (sign) starting from Left. This command is useful for data normalization.

All commands work in a similar way. An example for FFIR is shown in FIG. 9.

Pseudo-instructions

According to one embodiment of the microcontroller architecture, all the registers, including AccA and AccB, can be mapped into the register file address space. This increases the degree of flexibility for dual operand DSP instructions that may not be intuitively apparent. For example, a MAC operation may prefetch current (previous MAC) accumulator content as an operand for the next MAC operation.

According to one embodiment, during word or odd byte reads, the 8 bit ACCAH and ACCBH registers (AccA <39:32>& AccB <39:32>) are automatically sign extended to 16 bits (MS byte reads). Will return the sign extension byte).

Claims (29)

At least one multiplier unit that can be controlled to operate in a signed, unsigned, or mixed sign mode;
A multiplier unit mode decoder coupled to the multiplier unit and receiving position information of a first operand and position information of a second operand;
The multiplier unit mode decoder controls the multiplier unit to operate in a signed mode, an unsigned mode, or a combined sign / unsigned mode when in the mixed code mode according to the position information. Processor. The method of claim 1,
And wherein said multiplier unit comprises an n-bit multiplier controllable to perform signed, unsigned, or mixed sign multiplication on two input operands. The method of claim 1,
The multiplier unit,
A multiplier data preprocessor coupled to the multiplier unit for independently sign expanding or zero expanding two input operands;
And a signed multiplier. The method of claim 3,
And said signed multiplier is an n + 1 bit multiplier. The method of claim 1,
And a control register for selecting the signed mode, the unsigned mode, and the mixed sign mode for performing automatic selection of signed, unsigned, or combined signed / unsigned multiplication. Processor. The method of claim 1,
Wherein the position information includes information as to whether a register in the plurality of working registers is an odd register or an even register. The method of claim 1,
The first operand and the second operand are supplied by the data memory,
And the position information includes information on whether the address of the memory is an odd address or an even address. The method of claim 2,
The first operand is selected from the first set of two consecutive registers,
And the second operand is selected from a second set of two consecutive registers. The method of claim 1,
And a barrel shifter having a size to accommodate at least the magnitude of the result produced by the multiplier unit. 10. The method of claim 9,
Further comprising at least one accumulator and an adder coupled to the barrel shifter,
The multiplier unit, the accumulator and the barrel shifter are part of a digital signal processing (DSP) engine. The method of claim 10,
A result expansion unit coupled to the multiplier unit and the barrel shifter;
And zero-backfill coupled to the result expansion unit. The method of claim 10,
And round logic coupled to the accumulator. The method of claim 10,
The DSP engine is a 16-bit DSP engine with a plurality of 16-bit registers,
And the barrel shifter and the accumulator each comprise 40 bits. The method of claim 10,
Further comprising a microcontroller unit,
At least the multiplier unit is shared by the microcontroller unit and the DSP engine to execute arithmetic microcontroller instructions. The method of claim 3,
In signed mode, the multiplier data preprocessor sign-extends all inputs,
In unsigned mode, the multiplier data preprocessor extends all inputs to zero,
In mixed sign mode, the multiplier mode decoder instructs the multiplier data preprocessor to sign extend the input if the source is an odd register number or an odd memory address and zero extend the input if the source is an even register number or an even memory address. Processor characterized in that. In the multiplication method in the processor,
Providing a first n bit operand from a first position to a multiplier unit that can be controlled to operate in signed, unsigned, or combined signed / unsigned mode;
Providing a second operand from a second position to the multiplier unit;
Decode the position relative to the first operand and the second operand and control the multiplier unit to operate in a mixed mode where signed, unsigned, or combined signed / unsigned multiplication is performed according to the positions. And performing a multiplication in the processor. The method of claim 16,
The first operand and the second operand are stored in registers,
Wherein the position comprises whether the register in the plurality of working registers is an odd register or an even register. The method of claim 16,
The first operand and the second operand are provided by a data memory,
And the position comprises whether the address of the memory is an odd address or an even address. The method of claim 17,
The first operand is selected from the first set of two consecutive registers,
And wherein the second operand is selected from a second set of two consecutive registers. The method of claim 16,
And a control register determines whether the multiplier unit will operate in the signed, unsigned, or mixed mode. The method of claim 20,
In signed mode, the first operand and the second operand are signed extended,
In the unsigned mode, the first operand and the second operand are expanded to zero,
In mixed mode, the first operand and the second operand are signed extended if the operand is supplied by an odd register number or odd memory address, and zero expanded when the operand is supplied by an even register number or even memory address. A method of performing multiplication in a processor. A method for performing 2n bit multiplication using 4 n bit data words,
Storing a first operand for 2n bit multiplication in two consecutive registers or a first set of two consecutive memory locations;
Storing a second operand for 2n bit multiplication in a second set of two consecutive registers or two consecutive memory addresses;
Performing a first multiplication by a controllable multiplier unit using the first set of first registers or memory addresses and the second set of first registers or memory addresses, and shifting an associated first result;
Performing a second multiplication by a controllable multiplier unit using the first set of registers or memory addresses and the second set of registers or memory addresses to produce an associated second result;
Performing a third multiplication by a controllable multiplier unit using the first set of second registers or memory addresses and the first set of second registers or memory addresses to produce an associated third result;
And adding the first result, the second result and the third result to produce a final result, and storing the final result in registers or memory.
For each multiplication, the multiplier unit is automatically controlled according to the position of the register or memory address to operate in a signed, unsigned, or combined sign / unsigned mode. To perform 2n bit multiplication. The method of claim 22,
And wherein the position comprises whether the register in the plurality of working registers is an odd register or an even register. The method of claim 22,
Wherein the position comprises whether the address of the memory is an odd address or an even address. The method of claim 22,
And wherein the control register determines which of the signed, unsigned, and mixed sign modes the multiplier unit will operate in. 4n bit data words. The method of claim 25,
In signed mode, all inputs to the multiplier unit are signed extended,
In mixed sign mode, the input to the multiplier unit is signed extended if its input is provided by an odd register number or odd memory address, and zero expanded if its input is provided by an even register number or even memory address. A 2n bit multiplication method using 4 n bit data words, characterized by the above-mentioned. The method of claim 22,
The second result and the third result are shifted,
Performing a fourth multiplication by the controllable multiplier unit using the second set or memory address of the first set and the second register or memory address of the second set to produce an associated fourth result. More,
And the fourth result is added to the first result, the second result, and the third result to generate the final result. The method of claim 27,
And wherein the control register determines which of the signed, unsigned, and mixed sign modes the multiplier unit is to operate in. 4 n bit data words. The method of claim 28,
The multiplier unit comprises a signed multiplier,
In signed mode, all inputs to the multiplier unit are signed extended,
In the unsigned mode, all inputs to the multiplier unit are zero extended,
In mixed sign mode, the input to the multiplier unit is signed extended if its input is provided by an odd register number or odd memory address, and zero expanded if its input is provided by an even register number or even memory address. A 2n bit multiplication method using 4 n bit data words, characterized by the above-mentioned.

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