JP2010258389A - Multiple patterning wiring board - Google Patents

Multiple patterning wiring board Download PDF

Info

Publication number
JP2010258389A
JP2010258389A JP2009110055A JP2009110055A JP2010258389A JP 2010258389 A JP2010258389 A JP 2010258389A JP 2009110055 A JP2009110055 A JP 2009110055A JP 2009110055 A JP2009110055 A JP 2009110055A JP 2010258389 A JP2010258389 A JP 2010258389A
Authority
JP
Japan
Prior art keywords
wiring board
region
protrusion
product
cavity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009110055A
Other languages
Japanese (ja)
Inventor
Tetsuya Kitamura
哲也 北村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyocera SLC Technologies Corp
Original Assignee
Kyocera SLC Technologies Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyocera SLC Technologies Corp filed Critical Kyocera SLC Technologies Corp
Priority to JP2009110055A priority Critical patent/JP2010258389A/en
Publication of JP2010258389A publication Critical patent/JP2010258389A/en
Pending legal-status Critical Current

Links

Images

Landscapes

  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multiple patterning wiring board capable of preventing waste of a board material by making a cut region narrow, and effectively preventing the occurrence of flaws, dents, adhesion or the like to both surfaces of each product region when a plurality of the multiple patterning wiring boards are stacked on one another, and stably stackable by preventing the plurality of multiple patterning wiring boards from easily sliding on one another. <P>SOLUTION: In the multiple patterning wiring board 10, a plurality of product regions 3 each becoming a compact wiring board are arranged and formed side by side in a central part by interposing cut regions 4 therebetween, and a frame-like margin region 5 surrounding the central part is formed in an outer peripheral part. Projecting parts 7 having heights projecting from upper and lower surfaces of the product regions 3 and each formed of solder resist are formed on the upper and lower surfaces of at least either of the cut regions 4 and the margin regions 5. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、中央部に小型の配線基板となる製品領域が間に切断領域を挟んで複数並んで配列形成されているとともに、外周部に前記中央部を取り囲む枠状の捨て代領域が形成されて成る多数個取り配線基板に関するものである。   According to the present invention, a plurality of product areas to be small wiring boards are arranged in a row at a central portion with a cutting region interposed therebetween, and a frame-shaped discard margin region surrounding the central portion is formed on an outer peripheral portion. The present invention relates to a multi-cavity wiring board.

従来、半導体集積回路素子等の電子素子を搭載するための小型の配線基板を複数同時に取り扱う形態として多数個取り配線基板が用いられている。この多数個取り配線基板は、中央部に複数の小型の配線基板となる製品領域を間に切断領域を挟んで一体的に並べて設けるとともに、その外側に枠状の捨て代領域を一体的に形成してなる。そして、各製品領域に半導体集積回路素子等の電子素子を例えば半田バンプを介して搭載するとともに、その電子素子を例えばトランスファーモールド法により樹脂封止し、しかる後、切断領域に沿って切断することにより、小型の配線基板上に電子素子が搭載されて樹脂封止された電子装置が多数個同時集約的に製造される。   2. Description of the Related Art Conventionally, a multi-piece wiring board has been used as a form for simultaneously handling a plurality of small wiring boards for mounting electronic elements such as semiconductor integrated circuit elements. This multi-cavity wiring board has a product area that becomes a plurality of small-sized wiring boards in the center, and is arranged side by side with a cutting area between them, and a frame-shaped discard margin area is formed integrally on the outside. Do it. Then, an electronic element such as a semiconductor integrated circuit element is mounted on each product area through, for example, a solder bump, and the electronic element is resin-sealed by, for example, a transfer mold method, and then cut along the cutting area. As a result, a large number of electronic devices in which electronic elements are mounted on a small wiring board and sealed with a resin are collectively manufactured.

このような多数個取り配線基板においては、各製品領域に半導体集積回路素子等の電子素子の電極と接続するための配線導体が形成されている。配線導体は、例えば銅めっきから成り、近時では幅が10〜20μm程度の微細なパターンを有しており、その一部は各製品領域の上面に露出して、電子素子の電極と接続するための接続パッドを形成している。また、この接続パッドの表面には電子素子の電極と接続するための半田バンプが予め被着されている場合が多い。   In such a multi-piece wiring board, wiring conductors for connecting to electrodes of electronic elements such as semiconductor integrated circuit elements are formed in each product region. The wiring conductor is made of, for example, copper plating and has a fine pattern with a width of about 10 to 20 μm in recent times. A part of the wiring conductor is exposed on the upper surface of each product region and is connected to the electrode of the electronic element. The connection pad for forming is formed. In many cases, solder bumps for connecting to the electrodes of the electronic elements are previously deposited on the surface of the connection pads.

しかしながら、このような多数個取り配線基板は、その取扱い時に複数枚を積み重ねて取り扱われることがある。多数個取り配線基板を複数枚重ねて取り扱うと、上側の多数個取り配線基板と下側の多数個取り配線基板とがお互いに擦れたり、圧接されたりして、各製品領域において配線導体や半田バンプに傷や凹みを形成してしまうことがある。このような傷や凹みは、配線導体に断線やショートを引き起こしたり、電子素子の電極を接続パッドに半田バンプを介して接続する際の接続不良を引き起こしたりする危険性を高くする。   However, there are cases where such a multi-piece wiring board is handled by stacking a plurality of pieces at the time of handling. When multiple PCBs are stacked and handled, the upper PCB and the lower PCB are rubbed or pressed against each other, resulting in wiring conductors and solder in each product area. A bump or a dent may be formed on the bump. Such scratches and dents increase the risk of causing a disconnection or a short circuit in the wiring conductor, or causing a connection failure when connecting the electrode of the electronic element to the connection pad via the solder bump.

そこで、多数個取り配線基板の切断領域や捨て代領域における上面に、製品領域の半田バンプよりも突出するダミー半田バンプを設けることにより、多数個取り配線基板を互いに積み重ねた際に製品領域の半田バンプに発生する傷や凹み等を防止する方法が提案されている。しかしながら、多数個取り配線基板の上面にダミー半田バンプを設ける場合、ダミー半田バンプを十分な高さとするために多数個取り配線基板の切断領域に直径が400μm程度の半田ペーストを印刷してこれをリフローする必要がある。そのため、切断領域の幅が少なくとも400μmを超える広いものとなり、そのような広い幅の切断領域を製品領域間に設けることから使用する基板材料に無駄が生じやすい。さらに、切断領域や捨て代領域の上面のみにダミー半田バンプを設けるので、複数の多数個取り配線基板を積み重ねた場合に、下側の多数個取り配線基板のダミー半田バンプが上側の多数個取り配線基板の下面に直接当たることになる。そのため、下側の多数個取り配線基板のダミー半田バンプと上側の多数個取り配線基板における製品領域の下面とが擦れて、上側の多数個取り配線基板における製品領域の下面に下側の多数個取り配線基板のダミー半田バンプの成分が付着してしまい、上側の多数個取り配線基板の製品領域における電気的な絶縁信頼性を低下させてしまう危険性がある。また、ダミー半田バンプを切断領域や捨て代領域の上下両面に形成することも考えられるが、この場合、半田バンプの頂面は半田が溶融したときの表面張力により平滑な球面状となるため、上側の基板のダミー半田バンプと下側の基板のダミー半田バンプとが当接すると、互いに滑ってずれてしまい、良好に積み重ねることが困難となる。   Therefore, by providing dummy solder bumps that protrude beyond the solder bumps in the product area on the upper surface in the cutting area and the disposal allowance area of the multi-piece wiring board, soldering in the product area when the multi-piece wiring boards are stacked on each other is provided. A method for preventing scratches, dents, and the like generated on the bumps has been proposed. However, when a dummy solder bump is provided on the upper surface of the multi-cavity wiring board, a solder paste having a diameter of about 400 μm is printed on the cutting area of the multi-cavity wiring board so that the dummy solder bump has a sufficient height. Need to reflow. For this reason, the width of the cutting region becomes wider than at least 400 μm. Since such a wide cutting region is provided between the product regions, the substrate material to be used is likely to be wasted. Furthermore, since dummy solder bumps are provided only on the upper surface of the cutting area and the disposal allowance area, when a plurality of multi-cavity wiring boards are stacked, the upper multiple multi-cavity wiring board dummy solder bumps are removed. It directly hits the lower surface of the wiring board. Therefore, the dummy solder bumps of the lower multi-cavity wiring board and the lower surface of the product area of the upper multi-cavity wiring board rub against each other, and the lower multiple There is a risk that the components of the dummy solder bumps on the wiring board will adhere and the electrical insulation reliability in the product area of the upper multiple wiring board will be lowered. In addition, it is possible to form dummy solder bumps on both the upper and lower surfaces of the cutting area and discarding area, but in this case, the top surface of the solder bumps becomes a smooth spherical shape due to the surface tension when the solder melts, If the dummy solder bumps on the upper substrate and the dummy solder bumps on the lower substrate come into contact with each other, they will slip and shift, making it difficult to stack well.

特開2003−218542号公報JP 2003-218542 A

本発明の課題は、切断領域を狭いものとして基板材料の無駄を防止することができるとともに、複数の多数個取り配線基板を積み重ねた場合に、各製品領域の両面に対して傷や凹み、或いは付着等が発生することを有効に防止することができ、さらには、互いに滑りにくく安定して積み重ねることが可能な多数個取り配線基板を提供することにある。   An object of the present invention is to prevent a waste of substrate material by narrowing a cutting region, and when a plurality of multi-piece wiring boards are stacked, scratches or dents on both surfaces of each product region, or Another object of the present invention is to provide a multi-piece wiring board that can effectively prevent the occurrence of adhesion and the like and that can be stably stacked without slipping each other.

本発明の多数個取り配線基板は、中央部に小型の配線基板となる製品領域が間に切断領域を挟んで複数並んで配列形成されているとともに、外周部に前記中央部を取り囲む枠状の捨て代領域が形成されて成る多数個取り配線基板であって、前記切断領域および前記捨て代領域の少なくとも一方における上下面に前記製品領域の上下面から突出する高さのソルダーレジストから成る突起部が形成されていることを特徴とするものである。   The multi-cavity wiring board according to the present invention has a frame-like shape in which a plurality of product areas to be a small wiring board are arranged in a central part side by side with a cutting area in between, and a peripheral part surrounds the central part A multi-cavity wiring board having a disposal margin area formed thereon, and a protrusion comprising a solder resist having a height protruding from the upper and lower surfaces of the product area on the upper and lower surfaces of at least one of the cutting area and the disposal margin area Is formed.

本発明の多数個取り配線基板によれば、切断領域および捨て代領域の少なくとも一方における上下面に製品領域の上下面から突出する高さのソルダーレジストから成る突起部が形成されていることから、複数の多数個取り配線基板を積み重ねた場合に、下側の多数個取り配線基板における上面側の突起部と上側の多数個取り配線基板における下面側の突起部とが少なくとも互いに部分的に重なり合うように前記突起部を配置すれば、複数の多数個取り配線基板を積み重ねた場合に、製品領域の上下面に突起部が直接当接することがないので製品領域の上下両面を傷や凹み、付着から保護することができる。   According to the multi-cavity wiring board of the present invention, since the upper and lower surfaces of at least one of the cutting region and the disposal margin region are formed with protrusions made of a solder resist having a height protruding from the upper and lower surfaces of the product region, When a plurality of multi-cavity wiring boards are stacked, the upper surface protrusions of the lower multi-cavity wiring board and the lower surface protrusions of the upper multi-cavity wiring board are at least partially overlapping each other. If a plurality of multi-layered wiring boards are stacked, the protrusions do not directly contact the upper and lower surfaces of the product area, so that the upper and lower surfaces of the product area are not damaged or dented. Can be protected.

また、上面側の突起部と下面側の突起部とを、その一方の内側に他方が隣接して位置するように配置すれば、複数の多数個取り配線基板を積み重ねた場合に、上側の多数個取り配線基板における下面側の突起部と下側の多数個取り配線基板における上面側の突起部とが互いに水平方向に係止し合うこととなり、複数の多数個取り配線基板を互いにずれることなく、安定して積み重ねることができる。   Also, if the upper surface side protrusion and the lower surface side protrusion are arranged so that the other is located adjacent to the inside of one of the upper surface side protrusions, a plurality of upper side The protrusion on the lower surface side of the multi-cavity wiring board and the protrusion on the upper surface side of the lower multi-cavity wiring board are engaged with each other in the horizontal direction, and a plurality of multi-cavity wiring boards are not displaced from each other. Can be stacked stably.

図1(a)は、本発明の多数個取り配線基板の実施形態の一例を示す上面図であり、図1(b)は、図1(a)に示す多数個取り配線基板を二枚積み重ねた場合の図1(a)の切断線A−Aにおける断面図である。FIG. 1A is a top view showing an example of an embodiment of a multi-cavity wiring board according to the present invention, and FIG. 1B is a stack of the multi-cavity wiring boards shown in FIG. FIG. 2 is a cross-sectional view taken along a cutting line AA in FIG. 図2(a)は、本発明の多数個取り配線基板の実施形態の他の例を示す上面図であり、図2(b)は、図2(a)に示す多数個取り配線基板を二枚積み重ねた場合の図2(a)の切断線A−Aにおける断面図である。2A is a top view showing another example of the embodiment of the multi-cavity wiring board of the present invention, and FIG. 2B is a plan view of the multi-cavity wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.2 (a) at the time of stacking | stacking. 図3(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図3(b)は、図3(a)に示す多数個取り配線基板を二枚積み重ねた場合の図3(a)の切断線A−Aにおける断面図である。FIG. 3A is a top view showing still another example of the embodiment of the multi-cavity wiring board of the present invention, and FIG. 3B is a plan view of the multi-cavity wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.3 (a) at the time of stacking two sheets. 図4(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図4(b)は、図4(a)に示す多数個取り配線基板を二枚積み重ねた場合の図4(a)の切断線A−Aにおける断面図である。FIG. 4A is a top view showing still another example of the embodiment of the multi-piece wiring board of the present invention, and FIG. 4B shows the multi-piece wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.4 (a) at the time of stacking two sheets. 図5(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図5(b)は、図5(a)に示す多数個取り配線基板を二枚積み重ねた場合の図5(a)の切断線A−Aにおける断面図である。FIG. 5A is a top view showing still another example of the embodiment of the multi-piece wiring board of the present invention, and FIG. 5B shows the multi-piece wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.5 (a) at the time of stacking two sheets. 図6(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図6(b)は、図6(a)に示す多数個取り配線基板を二枚積み重ねた場合の図6(a)の切断線A−Aにおける断面図である。FIG. 6A is a top view showing still another example of the embodiment of the multi-cavity wiring board of the present invention, and FIG. 6B is a plan view of the multi-cavity wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.6 (a) at the time of stacking two sheets. 図7(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図7(b)は、図7(a)に示す多数個取り配線基板を二枚積み重ねた場合の図7(a)の切断線A−Aにおける断面図である。FIG. 7A is a top view showing still another example of the embodiment of the multi-cavity wiring board of the present invention, and FIG. 7B is a plan view of the multi-cavity wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.7 (a) at the time of stacking two sheets. 図8(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図8(b)は、図8(a)に示す多数個取り配線基板を二枚積み重ねた場合の図8(a)の切断線A−Aにおける断面図である。FIG. 8A is a top view showing still another example of the embodiment of the multi-cavity wiring board of the present invention, and FIG. 8B is a plan view of the multi-cavity wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.8 (a) at the time of stacking two sheets. 図9(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図9(b)は、図9(a)に示す多数個取り配線基板を二枚積み重ねた場合の図9(a)の切断線A−Aにおける断面図である。FIG. 9A is a top view showing still another example of the embodiment of the multi-cavity wiring board of the present invention, and FIG. 9B is a plan view of the multi-cavity wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.9 (a) at the time of stacking two sheets. 図10(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図10(b)は、図10(a)に示す多数個取り配線基板を二枚積み重ねた場合の図10(a)の切断線A−Aにおける断面図である。FIG. 10A is a top view showing still another example of the embodiment of the multi-piece wiring board of the present invention, and FIG. 10B shows the multi-piece wiring board shown in FIG. It is sectional drawing in the cutting line AA of Fig.10 (a) at the time of stacking two sheets. 図11(a)は、本発明の多数個取り配線基板の実施形態の更に他の例を示す上面図であり、図11(b)は、図11(a)に示す多数個取り配線基板を二枚積み重ねた場合の図11(a)の切断線A−Aにおける断面図である。FIG. 11A is a top view showing still another example of the embodiment of the multi-piece wiring board of the present invention, and FIG. 11B shows the multi-piece wiring board shown in FIG. It is sectional drawing in cutting line AA of Fig.11 (a) at the time of stacking two sheets.

次に、本発明の多数個取り配線基板の実施形態の一例を添付の図1(a),(b)を基に説明する。図1(a),(b)に示すように、本例の多数個取り配線基板10は、絶縁基板1の内部および表面に配線導体2を備えている。絶縁基板1は、例えばガラスクロスに熱硬化性樹脂を含浸させて成る繊維強化絶縁樹脂材料や熱硬化性樹脂に酸化珪素等の無機絶縁フィラーを分散させてなるフィラー含有絶縁樹脂材料から成る複数の絶縁層を積層することにより形成されており、各絶縁層には配線導体2を上下に導通させるためのスルーホールやビアホールと呼ばれる貫通孔が形成されている。また、配線導体2は、銅箔や銅めっき層から成る導電材料を各絶縁層に所定パターンに被着させることにより形成されている。   Next, an example of an embodiment of the multi-piece wiring board according to the present invention will be described with reference to FIGS. 1 (a) and 1 (b). As shown in FIGS. 1A and 1B, the multi-piece wiring board 10 of this example includes wiring conductors 2 inside and on the surface of the insulating board 1. The insulating substrate 1 is made of, for example, a plurality of fiber-reinforced insulating resin materials obtained by impregnating a glass cloth with a thermosetting resin or filler-containing insulating resin materials obtained by dispersing an inorganic insulating filler such as silicon oxide in a thermosetting resin. The insulating layer is formed by laminating, and in each insulating layer, a through-hole called a through hole or a via hole for electrically connecting the wiring conductor 2 is formed. The wiring conductor 2 is formed by depositing a conductive material made of copper foil or a copper plating layer on each insulating layer in a predetermined pattern.

多数個取り配線基板10の中央部には、半導体集積回路素子等の電子素子(不図示)を搭載するための小型の配線基板となる四角形状の製品領域3が間に帯状の切断領域4を挟んで複数並んで配列形成されており、さらにその外周部には前記中央部を取り囲むようにして四角枠状の捨て代領域5が形成されている。なお、この例では、製品領域3を2列×3列の配列で6個形成した例を示しているが、配列する製品領域3の個数や配列方法は必要に応じて適宜変更すればよい。   In the central portion of the multi-piece wiring substrate 10, a rectangular product region 3 serving as a small wiring substrate for mounting an electronic element (not shown) such as a semiconductor integrated circuit element is provided with a band-shaped cutting region 4 therebetween. A plurality of rows are arranged side by side, and a rectangular frame-shaped discard margin region 5 is formed on the outer peripheral portion so as to surround the central portion. In this example, an example is shown in which six product regions 3 are formed in a 2 × 3 array. However, the number of product regions 3 to be arranged and the arrangement method may be appropriately changed as necessary.

各製品領域4には、搭載される電子素子に電気的に接続される配線導体2がその上面から下面にかけて例えば幅が10〜20μm程度の微細な配線を含む所定のパターンに配設されている。配線導体2のうち、各製品領域3の上面に露出した一部は電子素子の電極端子に電気的に接続される接続パッドを形成しており、この接続パッドには電子素子の電極端子と電気的に接続するための半田バンプ6が被着されている。配線導体2は、周知のサブトラクティブ法やセミアディティブ法、転写法等により形成されている。また、半田バンプ6は接続パッドに半田ペーストを印刷した後にリフローする方法や接続パッドに半田をめっきする方法により形成されている。なお、この例では接続パッドが円形である場合を示しているが、接続パッドは正方形や長方形等の他の形状であってもよい。   In each product region 4, wiring conductors 2 that are electrically connected to mounted electronic elements are arranged in a predetermined pattern including fine wiring having a width of, for example, about 10 to 20 μm from the upper surface to the lower surface. . A part of the wiring conductor 2 exposed on the upper surface of each product region 3 forms a connection pad that is electrically connected to the electrode terminal of the electronic element. The connection pad is electrically connected to the electrode terminal of the electronic element. Solder bumps 6 are attached for the purpose of connection. The wiring conductor 2 is formed by a known subtractive method, semi-additive method, transfer method, or the like. The solder bumps 6 are formed by a method of reflowing after printing a solder paste on the connection pads or a method of plating the connection pads with solder. In this example, the connection pad is circular, but the connection pad may have another shape such as a square or a rectangle.

切断領域4は、複数の製品領域3の間に介在することにより複数の製品領域3を一体的に保持するとともに各製品領域3を切り出して個片の配線基板とするための切断代であり、この切断領域4をダイシングマシーンやルータ、レーザ切断装置等により切断することにより多数個取り配線基板10における各製品領域3が個片の配線基板として切り出されて独立する。   The cutting region 4 is a cutting allowance for integrally holding the plurality of product regions 3 by being interposed between the plurality of product regions 3 and cutting each product region 3 into a piece of wiring board, By cutting the cutting area 4 with a dicing machine, a router, a laser cutting device or the like, each product area 3 in the multi-piece wiring board 10 is cut out as a single wiring board and becomes independent.

捨て代領域5は、多数個取り配線基板10の取扱いを容易とするための支持部として機能する領域であり、この捨て代領域5を多数個取り配線基板10の加工時の位置決め部や保持部として使用することにより各製品領域3に必要な加工を施すことが可能となる。   The disposal allowance area 5 is an area that functions as a support for facilitating the handling of the multi-cavity wiring board 10. The disposal allowance area 5 is a positioning part or holding part when processing the multi-cavity wiring board 10. As a result, it is possible to perform necessary processing on each product region 3.

さらに、本例の多数個取り配線基板10においては、捨て代領域5における上下面にソルダーレジストから成る頂面が平坦な突起部7が格子状のパターンに形成されている。突起部7は製品領域3の上下面から半田バンプ6の高さよりも突出する高さで形成されており、複数の多数個取り配線基板10を上下に積み重ねたときに、上側の多数個取り配線基板10における下面側の突起部7と下側の多数個取り配線基板10における上面側の突起部7とが互いに重なり合うようになっている。このように本例の多数個取り配線基板10によれば、捨て代領域5における上下面にソルダーレジストから成る頂面が平坦な突起部7が格子状のパターンに形成されており、複数の多数個取り配線基板10を上下に積み重ねたときに、上側の多数個取り配線基板10における下面側の突起部7と下側の多数個取り配線基板10における上面側の突起部7とが互いに重なり合うことから、製品領域3の上下面に突起部7が直接当接することがなく、従って製品領域3の上下面が傷や凹み、付着等から有効に保護される。さらに、複数の多数個取り配線基板10を上下に積み重ねた場合に、上側の多数個取り配線基板10の突起部7と下側の多数個取り配線基板10の突起部7とが当接しても、その当接は平坦な頂面同士の当接となり、安定して積み重ねることが可能である。   Furthermore, in the multi-cavity wiring substrate 10 of this example, protrusions 7 having a flat top surface made of solder resist are formed in a lattice pattern on the upper and lower surfaces in the disposal allowance region 5. The protrusions 7 are formed with a height that protrudes from the upper and lower surfaces of the product region 3 beyond the height of the solder bumps 6, and when a plurality of multi-chip wiring boards 10 are stacked vertically, the upper multi-chip wiring is formed. The protrusion 7 on the lower surface side of the substrate 10 and the protrusion 7 on the upper surface side of the lower multi-cavity wiring substrate 10 overlap each other. As described above, according to the multi-cavity wiring substrate 10 of this example, the protrusions 7 having a flat top surface made of a solder resist are formed in a lattice pattern on the upper and lower surfaces in the disposal allowance region 5, and a plurality of many When the multi-cavity wiring boards 10 are stacked one above the other, the lower projection 7 on the upper multi-cavity wiring board 10 and the upper projection 7 on the lower multi-wiring wiring board 10 overlap each other. Therefore, the protrusions 7 do not directly contact the upper and lower surfaces of the product region 3, so that the upper and lower surfaces of the product region 3 are effectively protected from scratches, dents, adhesion and the like. Furthermore, when a plurality of multi-cavity wiring boards 10 are stacked one above the other, even if the protrusions 7 of the upper multi-cavity wiring board 10 and the protrusions 7 of the lower multi-cavity wiring board 10 come into contact with each other. The abutment becomes abutment between flat top surfaces and can be stably stacked.

このような突起部7は、絶縁基板1の上下面にソルダーレジスト用の感光性のドライフィルムレジストを貼着するとともに、そのドライフィルムレジストを周知のフォトリソグラフィー技術を採用して所定のパターンに露光および現像した後、熱硬化および紫外線硬化させることにより形成される。突起部7は、このようにソルダーレジスト用の感光性のドライフィルムレジストをフォトリソグラフィー技術により所定のパターンに露光および現像した後、熱硬化および紫外線硬化させることにより形成されることから、その頂面が平坦なものとなるとともに、その幅を例えば10〜30μm程度の狭いものとすることができる。したがって、突起部7を設ける切断領域4の幅を例えば30μm程度以下の狭いものとして多数個取り配線基板10における基板材料の無駄を減少させることができる。   Such protrusions 7 are formed by sticking a photosensitive dry film resist for solder resist on the upper and lower surfaces of the insulating substrate 1 and exposing the dry film resist to a predetermined pattern using a well-known photolithography technique. And after development, it is formed by heat curing and ultraviolet curing. Since the protrusion 7 is formed by subjecting the photosensitive dry film resist for solder resist to a predetermined pattern by exposure and development by a photolithographic technique, followed by thermosetting and ultraviolet curing, the top surface of the protrusion 7 is formed. Becomes flat and the width thereof can be narrow, for example, about 10 to 30 μm. Therefore, the waste of the substrate material in the multi-piece wiring board 10 can be reduced by setting the width of the cutting region 4 provided with the protrusions 7 to be as narrow as about 30 μm or less.

そして、本例の多数個取り配線基板10によれば、各製品領域3に半導体集積回路素子等の電子素子を例えば半田バンプ6を介して搭載するとともに、その電子素子を例えばトランスファーモールド法により樹脂封止し、しかる後、切断領域4に沿って切断することにより、小型の配線基板上に電子素子が搭載されて樹脂封止された電子装置が多数個同時集約的に製造される。   According to the multi-cavity wiring substrate 10 of this example, an electronic element such as a semiconductor integrated circuit element is mounted on each product region 3 via, for example, the solder bumps 6 and the electronic element is resinated by, for example, transfer molding. After sealing, and then cutting along the cutting region 4, a large number of electronic devices in which electronic elements are mounted on a small wiring board and sealed with a resin are manufactured at once.

さらに、本発明の多数個取り配線基板の実施形態における他の例を図2(a),(b)〜図11(a),(b)に示す。なお、図2(a),(b)〜図11(a),(b)に示す例において、上述の実施形態の一例と実質的に同じ部分には図1(a),(b)と同じ符号を付し、その詳細な説明は省略する。   Furthermore, other examples in the embodiment of the multi-piece wiring board of the present invention are shown in FIGS. 2 (a) and 2 (b) to FIGS. 11 (a) and 11 (b). In the example shown in FIGS. 2A and 2B to FIGS. 11A and 11B, substantially the same parts as those in the above-described embodiment are shown in FIGS. 1A and 1B. The same reference numerals are given, and detailed description thereof is omitted.

図2(a),(b)に示す例の多数個取り配線基板20は、捨て代領域5にソルダーレジストから成る幅が0.5〜5mm程度の枠状の突起部7を有している。本例の多数個取り配線基板20においては、このように捨て代領域5に幅の広い枠状の突起部7を有していることから、本例の多数個取り配線基板20を複数上下に積み重ねた場合に、捨て代領域5に設けた幅の広い枠状の突起部7同士が互いに当接することとなるので、上下の多数個取り配線基板20同士を極めて安定して積み重ねることができる。また、捨て代領域5における上下面が平坦な面となるため、トランスモールド法により樹脂封止する際に、捨て代領域5に設けた枠状の突起部7とトランスファーモールドの金型とを良好に密着させることができる。   The multi-cavity wiring board 20 in the example shown in FIGS. 2A and 2B has a frame-shaped projection 7 having a width of about 0.5 to 5 mm made of a solder resist in the discard margin area 5. . Since the multi-cavity wiring board 20 of this example has the wide frame-shaped protrusions 7 in the discard margin region 5 as described above, a plurality of multi-cavity wiring boards 20 of this example are vertically arranged. When stacked, the wide frame-shaped projections 7 provided in the disposal margin region 5 come into contact with each other, so that the upper and lower multi-piece wiring boards 20 can be stacked extremely stably. In addition, since the upper and lower surfaces in the disposal margin region 5 are flat surfaces, the frame-shaped protrusion 7 provided in the disposal margin region 5 and the mold of the transfer mold are excellent when resin sealing is performed by the transmold method. Can be adhered to.

図3(a),(b)に示す例の多数個取り配線基板30は、捨て代領域5における上面の内周部に枠状の突起部7aを有しているとともに、捨て代領域5における下面の外周部に前記突起部7aの外周よりも若干大きな内周を有する枠状の突起部7bを有している。このように、捨て代領域5の下面に上面の突起部7aの外周部よりも若干大きな内周を有する枠状の突起部7bを有していることから、複数の多数個取り配線基板30を上下に積み重ねた場合に、下側の多数個取り配線基板30における上面側の突起部7aの外周縁と上側の多数個取り配線基板30における下面側の突起部7bの内周縁とが互いに係止し合うこととなり、複数の多数個取り配線基板30を互いにずれることなく、安定して積み重ねることができる。   The multi-piece wiring board 30 in the example shown in FIGS. 3A and 3B has a frame-shaped protrusion 7 a on the inner peripheral portion of the upper surface in the disposal allowance area 5, and in the discard allowance area 5. A frame-like projection 7b having an inner circumference slightly larger than the outer circumference of the projection 7a is provided on the outer circumference of the lower surface. As described above, since the bottom surface of the discard margin region 5 has the frame-shaped protrusion 7b having an inner periphery slightly larger than the outer periphery of the upper protrusion 7a, a plurality of multi-piece wiring boards 30 are provided. When stacked one above the other, the outer peripheral edge of the upper-side projection 7a in the lower multi-cavity wiring board 30 and the inner periphery of the lower-side projection 7b in the upper multi-cavity wiring board 30 are locked together. As a result, a plurality of multi-piece wiring boards 30 can be stably stacked without being displaced from each other.

図4(a),(b)に示す例の多数個取り配線基板40は、切断領域4における上面に図4(a)の縦方向に延びる帯状の突起部7aを有するとともに、切断領域4における下面に図4(a)の横方向に延びる帯状の突起部7bを有している。このように、切断領域4の上面と下面とに互いに直角に交差する方向に延びる突起部7aおよび7bを有することから、複数の多数個取り配線基板40を上下に積み重ねた場合に、上下の多数個取り配線基板40同士が多少ずれたとしても、上側の多数個取り配線基板40における下面側の突起部7bと下側の多数個取り配線基板40における上面側の突起部7aとが互いに部分的に重なり合うことから、製品領域3の上下面を有効に保護することができるとともに、各製品領域3に半導体集積回路素子等の電子素子を搭載するとともに、その電子素子をトランスファーモールド法により樹脂封止する際に突起部7aおよび7bに沿ってモールド樹脂を良好に流動させることができる。   4A and 4B has a strip-shaped protrusion 7a extending in the vertical direction of FIG. 4A on the upper surface of the cutting region 4, and in the cutting region 4. In the example shown in FIGS. The bottom surface has a belt-like protrusion 7b extending in the lateral direction of FIG. As described above, since the upper surface and the lower surface of the cutting region 4 have the protrusions 7a and 7b extending perpendicularly to each other, when a plurality of multi-piece wiring boards 40 are stacked one above the other, Even if the individual circuit boards 40 are slightly displaced from each other, the lower projection 7b on the upper multi-cavity wiring board 40 and the upper projection 7a on the lower multi-acquisition wiring board 40 are partially separated from each other. Therefore, the upper and lower surfaces of the product areas 3 can be effectively protected, and an electronic element such as a semiconductor integrated circuit element is mounted on each product area 3, and the electronic elements are sealed with a transfer mold method. In doing so, the mold resin can be made to flow well along the protrusions 7a and 7b.

図5(a),(b)に示す例の多数個取り配線基板50は、切断領域4における交点部に十字形状の突起部7を有している。この場合、各製品領域3に半導体集積回路素子等の電子素子を搭載するとともに、その電子素子をトランスファーモールド法により樹脂封止する際に隣接する突起部7同士の間から各製品領域3内にモールド樹脂を良好に流動させることができる。   The multi-piece wiring board 50 in the example shown in FIGS. 5A and 5B has a cross-shaped protrusion 7 at the intersection in the cutting region 4. In this case, an electronic element such as a semiconductor integrated circuit element is mounted in each product region 3 and when the electronic element is resin-sealed by a transfer molding method, the region between adjacent protrusions 7 is placed in each product region 3. The mold resin can be flowed satisfactorily.

図6(a),(b)に示す例の多数個取り配線基板60は、切断領域4における交点部を除く部位に帯状の突起部7を有している。この場合も、各製品領域3に半導体集積回路素子等の電子素子を搭載するとともに、その電子素子をトランスファーモールド法により樹脂封止する際に隣接する突起部7同士の間から各製品領域3内にモールド樹脂を良好に流動させることができる。   The multi-cavity wiring board 60 in the example shown in FIGS. 6A and 6B has a belt-like protrusion 7 at a portion other than the intersection in the cutting region 4. Also in this case, an electronic element such as a semiconductor integrated circuit element is mounted on each product region 3 and the inside of each product region 3 is formed between adjacent protrusions 7 when the electronic device is resin-sealed by a transfer molding method. The mold resin can be made to flow well.

図7(a),(b)に示す例の多数個取り配線基板70は、切断領域4における交点部のひとつおきに十字形状の突起部7を有している。この場合も、各製品領域3に半導体集積回路素子等の電子素子を搭載するとともに、その電子素子をトランスファーモールド法により樹脂封止する際に隣接する突起部7同士の間から各製品領域3内にモールド樹脂を良好に流動させることができる。   The multi-piece wiring board 70 in the example shown in FIGS. 7A and 7B has a cross-shaped projection 7 at every other intersection in the cutting region 4. Also in this case, an electronic element such as a semiconductor integrated circuit element is mounted on each product region 3 and the inside of each product region 3 is formed between adjacent protrusions 7 when the electronic device is resin-sealed by a transfer molding method. The mold resin can be made to flow well.

図8(a),(b)に示す例の多数個取り配線基板80は、切断領域4に島状の突起部7を断続的に並べて有している。この場合も、各製品領域3に半導体集積回路素子等の電子素子を搭載するとともに、その電子素子をトランスファーモールド法により樹脂封止する際に隣接する突起部7同士の間から各製品領域3内にモールド樹脂を良好に流動させることができる。   The multi-piece wiring board 80 in the example shown in FIGS. 8A and 8B has island-like protrusions 7 arranged intermittently in the cutting region 4. Also in this case, an electronic element such as a semiconductor integrated circuit element is mounted on each product region 3 and the inside of each product region 3 is formed between adjacent protrusions 7 when the electronic device is resin-sealed by a transfer molding method. The mold resin can be made to flow well.

図9(a),(b)に示す例の多数個取り配線基板90は、捨て代領域5に島状の突起部7を断続的に枠状に並べて有している。このように、捨て代領域5に島状の突起部7を断続的に枠状に並べて設けても良い。   The multi-cavity wiring board 90 in the example shown in FIGS. 9A and 9B has island-like protrusions 7 arranged intermittently in a frame shape in the disposal margin region 5. As described above, the island-shaped protrusions 7 may be intermittently arranged in a frame shape in the discard margin region 5.

図10(a),(b)に示す多数個取り配線基板100は、切断領域4および捨て代領域5の他に、製品領域3の上面に半田バンプ6の全体を取り囲むようにして追加の突起部7cを有している。この場合、製品領域3の上面をさらに有効に保護することができる。   10 (a) and 10 (b), in addition to the cutting region 4 and the disposal margin region 5, the multi-cavity wiring substrate 100 has an additional protrusion on the upper surface of the product region 3 so as to surround the entire solder bump 6. It has a portion 7c. In this case, the upper surface of the product region 3 can be more effectively protected.

図11(a),(b)に示す多数個取り配線基板110は、製品領域3の上面に半田バンプ6の個々を別々に取り囲むようにして追加の突起部7cを有している。この場合、個々の半田バンプ6をより有効に保護することができる。   11A and 11B has an additional protrusion 7c on the upper surface of the product region 3 so as to surround each of the solder bumps 6 separately. In this case, the individual solder bumps 6 can be protected more effectively.

1 絶縁基板
2 配線導体
3 製品領域
4 切断領域
5 捨て代領域
6 半田バンプ
7 突起部
DESCRIPTION OF SYMBOLS 1 Insulation board | substrate 2 Wiring conductor 3 Product area 4 Cutting area 5 Discarding allowance area 6 Solder bump 7 Protrusion part

Claims (11)

中央部に小型の配線基板となる製品領域が間に切断領域を挟んで複数並んで配列形成されているとともに、外周部に前記中央部を取り囲む枠状の捨て代領域が形成されて成る多数個取り配線基板であって、前記切断領域および前記捨て代領域の少なくとも一方における上下面に前記製品領域の上下面から突出する高さのソルダーレジストから成る突起部が形成されていることを特徴とする多数個取り配線基板。   A plurality of product areas, which are small wiring boards in the center, are arranged side by side with a cutting area between them, and a plurality of frame-shaped discard margin areas surrounding the center are formed on the outer periphery. In the wiring board, a protrusion made of a solder resist having a height protruding from the upper and lower surfaces of the product region is formed on the upper and lower surfaces of at least one of the cutting region and the discarding region. Multi-piece wiring board. 前記多数個取り配線基板を上下に透視した場合に、上面側の前記突起部と下面側の前記突起部とが少なくとも互いに部分的に重なり合うように配置されていることを特徴とする請求項1記載の多数個取り配線基板。   2. The projections on the upper surface side and the projections on the lower surface side are arranged so as to at least partially overlap each other when the multi-piece wiring board is seen through vertically. Multi-cavity wiring board. 前記突起部は、前記切断領域に前記製品領域を取り囲む格子状に形成されていることを特徴とする請求項1または2に記載の多数個取り配線基板。   The multi-cavity wiring board according to claim 1, wherein the protrusion is formed in a lattice shape surrounding the product region in the cutting region. 前記突起部は、前記切断領域に連続的に形成されていることを特徴とする請求項1乃至3のいずれかに記載の多数個取り配線基板。   The multi-cavity wiring board according to claim 1, wherein the protrusion is formed continuously in the cutting region. 前記突起部は、前記切断領域に断続的に形成されていることを特徴とする請求項1乃至3のいずれかに記載の多数個取り配線基板。   The multi-cavity wiring board according to claim 1, wherein the protrusion is intermittently formed in the cutting region. 前記多数個取り配線基板を上下に透視した場合に、上面側の前記突起部と下面側の前記突起部とが互いに直角に交差するように配置されていることを特徴とする請求項3乃至5のいずれかに記載の多数個取り配線基板。   6. The projections on the upper surface side and the projections on the lower surface side are arranged so as to intersect at right angles when the multi-piece wiring board is seen through vertically. The multi-cavity wiring board according to any one of the above. 前記突起部は、前記捨て代領域に枠状に形成されていることを特徴とする請求項1乃至6のいずれかに記載の多数個取り配線基板。   The multi-cavity wiring board according to claim 1, wherein the protrusion is formed in a frame shape in the discard margin region. 前記突起部は、前記捨て代領域に連続的に形成されていることを特徴とする請求項7記載の多数個取り配線基板。   The multi-cavity wiring board according to claim 7, wherein the protrusion is formed continuously in the discard margin region. 前記突起部は、前記捨て代領域に断続的に形成されていることを特徴とする請求項7記載の多数個取り配線基板。   The multi-cavity wiring board according to claim 7, wherein the protrusion is intermittently formed in the discard margin region. 前記多数個取り配線基板を上下に透視した場合に、上面側の前記突起部と下面側の前記突起部とが一方の前記突起部の内側に他方の前記突起部が隣接して位置するように配置されていることを特徴とする請求項7乃至9に記載の配線基板。   When the multi-piece wiring board is seen through vertically, the protrusion on the upper surface side and the protrusion on the lower surface side are positioned so that the other protrusion is adjacent to the inside of the one protrusion. The wiring board according to claim 7, wherein the wiring board is arranged. 前記製品領域の上下面の少なくとも一方に、前記突起部と同じ高さのソルダーレジストから成る別の突起部が形成されていることを特徴とする請求項1乃至10のいずれかに記載の多数個取り配線基板。   The multiple projections according to any one of claims 1 to 10, wherein another projection made of a solder resist having the same height as the projection is formed on at least one of the upper and lower surfaces of the product region. Wiring board.
JP2009110055A 2009-04-28 2009-04-28 Multiple patterning wiring board Pending JP2010258389A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009110055A JP2010258389A (en) 2009-04-28 2009-04-28 Multiple patterning wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009110055A JP2010258389A (en) 2009-04-28 2009-04-28 Multiple patterning wiring board

Publications (1)

Publication Number Publication Date
JP2010258389A true JP2010258389A (en) 2010-11-11

Family

ID=43318926

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009110055A Pending JP2010258389A (en) 2009-04-28 2009-04-28 Multiple patterning wiring board

Country Status (1)

Country Link
JP (1) JP2010258389A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107174U (en) * 1988-01-11 1989-07-19
JPH0738230A (en) * 1993-06-28 1995-02-07 Fuji Electric Co Ltd Manufacture of thick film integrated circuit
JP2007207934A (en) * 2006-01-31 2007-08-16 Kyocera Kinseki Corp Sheet-like aggregate substrate
JP2007227873A (en) * 2006-01-27 2007-09-06 Kyocera Corp Multiple wiring board

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01107174U (en) * 1988-01-11 1989-07-19
JPH0738230A (en) * 1993-06-28 1995-02-07 Fuji Electric Co Ltd Manufacture of thick film integrated circuit
JP2007227873A (en) * 2006-01-27 2007-09-06 Kyocera Corp Multiple wiring board
JP2007207934A (en) * 2006-01-31 2007-08-16 Kyocera Kinseki Corp Sheet-like aggregate substrate

Similar Documents

Publication Publication Date Title
US11637070B2 (en) Method of fabricating a semiconductor package
US7573722B2 (en) Electronic carrier board applicable to surface mounted technology (SMT)
US7098407B2 (en) Non-solder mask defined (NSMD) type wiring substrate for ball grid array (BGA) package and method for manufacturing such a wiring substrate
US8336201B2 (en) Method of manufacturing printed circuit board having flow preventing dam
KR20090034081A (en) Stack-type semiconductor package apparatus and manufacturing method the same
US9949372B2 (en) Printed wiring board and method for manufacturing the same
US20140146500A1 (en) Multi-piece substrate
US7952199B2 (en) Circuit board including solder ball land having hole and semiconductor package having the circuit board
TW201405745A (en) Package substrate, package structure and method for manufacturing package structure
WO2018054315A1 (en) Packaging structure and packaging method
US10950464B2 (en) Electronic device module and manufacturing method thereof
EP3291285A1 (en) Semiconductor package structure with a polymer gel surrounding solders connecting a chip to a substrate and manufacturing method thereof
US8853866B2 (en) Semiconductor device and stacked-type semiconductor device
KR101477818B1 (en) Printed circuit board and method of manufacturing the same
US8098496B2 (en) Wiring board for semiconductor device
KR20090056560A (en) Substrate for semiconductor package and semiconductor package having the same
TWI530240B (en) Printed circuit board and method for manufacturing same
JP4650269B2 (en) Manufacturing method of stacked semiconductor device
JP4556671B2 (en) Semiconductor package and flexible circuit board
JP2004247464A (en) Semiconductor device and manufacturing method therefor
JP5933271B2 (en) Wiring board, electronic unit, and method of manufacturing wiring board
JP2010258389A (en) Multiple patterning wiring board
KR20060017294A (en) Small sized semiconductor integrated circuit package and printed circuit substrate
JP2004134478A (en) Semiconductor package and its manufacturing method
JP2005340864A (en) Manufacturing method of semiconductor device

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20111107

A977 Report on retrieval

Effective date: 20121011

Free format text: JAPANESE INTERMEDIATE CODE: A971007

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121127

A02 Decision of refusal

Effective date: 20130327

Free format text: JAPANESE INTERMEDIATE CODE: A02