JP2010257035A - Computer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer monitoring interrupts from a plurality of data sources and performing transfer of data without missing. <P>SOLUTION: The computer 100 includes: a plurality of data buffer circuits 4-1 to 4-N for temporarily holding a plurality of pieces of the data and sending them to an MPU (Micro Processing Unit); a plurality of interrupt signal edge detection circuits 2-1 to 2-N sequentially detecting change points from interrupt request signals from the data sources 1-1 to 1-N and generating edge signals; a plurality of FIFO (First In First Out) buffer circuits 3-1 to 3-N temporarily holding the edge signals from the interrupt signal edge detection circuits 2-1 to 2-N; an interrupt sampler circuit 5 registering outputs of the FIFO buffer circuits 3-1 to 3-N into a queue; and an interrupt controller 6 reading the queue of the interrupt sampler circuit 5 and generating an interrupt signal to the MPU 7. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a computer that receives data from a plurality of data sources at an arbitrary timing.

  As computers become larger and faster every year, so-called distributed processing has been attempted, such as dividing a single system into a plurality of subsystems and integrating them. While there is a merit that it becomes easy to systematize by distributed processing, there is a demerit that information transmission between subsystems becomes complicated. There are frequent cases where the output of an arbitrary data source must be received at an arbitrary output timing. Therefore, it is desired that data can be exchanged between subsystems or between lower systems and higher systems more reliably, more efficiently, and more easily realized.

  In an application field using an embedded device or a PC, an interrupt method is widely known as means for efficiently capturing data from an external data source (see Patent Document 1). The interrupt method can be said to be superior to the polling method because accurate timing and accurate data acquisition can be easily realized.

  However, when interrupts occur simultaneously from a plurality of data sources, it is not easy to deal with the simultaneous processing, and there are many cases where data is lost. The processing for dealing with this tends to be complicated.

JP-A-5-143360

  An object of the present invention is to provide a computer capable of monitoring interrupt requests from a plurality of data sources and exchanging data without missing them.

  According to a first aspect of the present invention, there is provided a computer for receiving data from a plurality of data sources at an arbitrary timing, a plurality of data buffer circuits for temporarily holding the plurality of data and sending the data to an MPU; A plurality of interrupt signal edge detection circuits that sequentially detect change points from an interrupt request signal from a data source and generate an edge signal, and a plurality of FIFOs that temporarily hold the edge signal from the interrupt signal edge detection circuit A buffer circuit; an interrupt sampler circuit that registers the output of the FIFO buffer circuit in a queue; and an interrupt controller that reads the queue of the interrupt sampler circuit and generates an interrupt signal to the MPU. Features.

  According to the present invention, it is possible to monitor interrupts from a plurality of data sources and exchange data without missing them. As a result, according to the present invention, the time restriction on the interrupt processing software is eased, and development and testing are facilitated. As a result, it is easy to realize decentralization by subsystems. It becomes easy to do.

It is a block diagram which shows the computer which concerns on Embodiment 1 of this invention. It is a figure for demonstrating an example of the processing flow of the hardware from generation | occurrence | production of an interruption request | requirement to registering interruption information into a queue in Embodiment 1 of this invention. It is a figure for demonstrating an example of the processing flow of the hardware until it notifies interruption request | requirement registered into the queue in Embodiment 1 of this invention to MPU. It is a figure for demonstrating an example of the processing flow of the software of MPU with respect to the interruption request in Embodiment 1 of this invention. It is a figure for demonstrating an example of the processing flow of the software of MPU with respect to the interruption message in Embodiment 1 of this invention. It is a figure which shows the time chart with respect to a processing flow when the interruption request generate | occur | produces simultaneously from three data sources in Embodiment 1 of this invention.

Next, embodiments of the present invention will be described in detail with reference to the drawings.
(Embodiment 1)
FIG. 1 is a block diagram showing a computer according to Embodiment 1 of the present invention. As shown in FIG. 1, the computer 100 according to the first embodiment of the present invention includes a plurality of data buffer circuits 4-1, 4-2,..., 4-N and a plurality of interrupt signal edge detection circuits 2-1. , 2-N, a plurality of FIFO buffer circuits 3-1, 3-2,..., 3-N, an interrupt sampler circuit 5, and an interrupt controller 6.

  A plurality of data sources 1-1, 1-2,..., 1-N are connected to input terminals of the plurality of data buffer circuits 4-1, 4-2,. The output terminals of the plurality of data buffer circuits 4-1, 4-2,..., 4-N are connected to the input terminal of the MPU 7. The input terminals of the plurality of interrupt signal edge detection circuits 2-1, 2-2,..., 2-N are connected to the output terminals of the plurality of data sources 1-1, 1-2,. Yes. The output terminals of the plurality of interrupt signal edge detection circuits 2-1, 2-2,..., 2-N are connected to the input terminals of the plurality of FIFO buffer circuits 3-1, 3-2,. Yes. The output terminals of the plurality of FIFO buffer circuits 3-1, 3-2 to 3 -N are connected to the input terminal of the interrupt sampler circuit 5. The output terminal of the interrupt sampler circuit 5 is connected to the input terminal of the interrupt controller 6. An output terminal of the interrupt controller 6 is connected to an input terminal of an MPU (Micro Processing Unit) 7.

  The computer 100 receives data from the plurality of data sources 1-1, 1-2,. A plurality of data buffer circuits 4-1, 4-2,..., 4-N temporarily hold a plurality of data from the plurality of data sources 1-1, 1-2,. It is for sending. A plurality of interrupt signal edge detection circuits 2-1, 2-2,..., 2-N sequentially detect change points from interrupt request signals from the data sources 1-1, 1-2,. To generate an edge signal. The plurality of FIFO buffer circuits 3-1, 3-2,..., 3-N temporarily hold edge signals from the interrupt signal edge detection circuits 2-1, 2-2,. The interrupt sampler circuit 5 registers the outputs of the FIFO buffer circuits 3-1, 3-2, ..., 3-N in a queue. The interrupt controller 6 reads the queue of the interrupt sampler circuit 6 and generates an interrupt signal to the MPU 7.

  The number of data sources (interrupt generation sources) 1-1, 1-2,..., 1-N is N. There are no restrictions on the number of connections N other than physical restrictions such as the shape and size of the connectors of the signal lines from the data sources 1-1, 1-2,. The data sources (interrupt generation sources) 1-1, 1-2,..., 1-N are connected to the computer 100 by a signal line 11 for requesting an interrupt and a data signal line 12 to be passed.

  The interrupt signal edge detection circuits 2-1, 2-2, ..., 2-N are interrupt request signals from the data sources 1-1, 1-2, ..., 1-N (writing from the data source to the data buffer circuit). The edge signal is detected (normalization of the signal assertion period) for the edge signal 13 is generated with respect to the completion signal. The edge signal 13 will be described later, but the interrupt request completion response 11 or the data sources 1-1, 1-2,..., 1-N to the data buffer circuits 4-1, 4-2,. Is generated based on a signal indicating that writing has been completed. .., 2-N are arranged as many as the number N of data sources 1-1, 1-2,..., 1-N, and the data sources 1-1, 1-2,. ..., signals from 1-N are processed in parallel.

  The FIFO buffer circuits 3-1, 3-2,..., 3-N temporarily hold an interrupt edge signal as interrupt information via a signal line 13 in a FIFO (First In First Out) buffer. The capacity of this buffer may be small because both reading and writing are executed by hardware, and both have no restrictions on the weight. , 3-N are arranged as many as the number N of data sources 1-1, 1-2,..., 1-N, and the data sources 1-1, 1-2, ..., signals from 1-N are processed in parallel.

  The data buffer circuits 4-1, 4-2,..., 4-N are FIFO buffers for temporarily storing data received from the data sources 1-1, 1-2,. Data buffers 1-1, 4-2,..., 4-N are arranged as many as the number N of data sources 1-1, 1-2,. , 1-N are processed in parallel.

  The interrupt sampler 5 is a FIFO buffer for registering an interrupt request in a queue and a circuit for controlling the FIFO buffer. When N-th FIFO buffer circuits 3-1, 3-2,..., 3-N are not empty (empty), they are sequentially read (dequeued), and data source number (1 to N) information is added. Then, it writes into the interrupt sampler 5 via the signal line 14 (enqueue).

  In the sequential reading, the time loss due to the sequential reading can be ignored by sampling at a timing sufficiently faster than the actual response time of the interrupt. It is generally easy to set the sampling cycle of sequential reading performed by hardware processing to several tens to several hundreds MHz (several tens to several ns). On the other hand, the accuracy of interrupt timing is several hundred ns to several μs. This is because it is assumed to be realistic.

  The interrupt controller 6 is a circuit that performs arbitration between software interrupt processing in the MPU 7 and the interrupt sampler circuit 5. The interrupt controller 6 reads the queue of the interrupt sampler circuit 6 to generate an interrupt signal to the MPU 7, and sequentially generates an interrupt to the MPU 7 via the signal line 16 in the order of generation. Looking at each interrupt, the interrupt request signal 16 and its interrupt completion signal 17 are paired.

  The MPU 7 is a part that receives an interrupt and executes interrupt processing by software. The memory device 8 is a work memory device of the MPU 7. In order to simplify the description, it is assumed that the data from the N data sources 1-1, 1-2,.

  The data buffer circuits 4-1, 4-2,..., 4-N, the interrupt controller 6, the MPU 7, and the memory device 8 are connected by a data bus 10 and a control bus 9. The data bus 10 is an aggregate of signal lines for exchanging data (the bus width depends on the data to be handled), and circuits connected to the periphery of the bus are connected to the bus only during access. The control bus 9 is a collection of signal lines indicating interrupt requests, signal lines for determining the read / write timing of the data bus, and the like. There are other address buses, but they are omitted because they are not the essence of the present invention.

  Next, the operation of the computer 100 according to Embodiment 1 of the present invention will be described in detail with reference to the drawings. The operation of the computer 100 is broadly divided into (i) hardware processing until the interrupt request is registered in the queue (see FIG. 2), and (ii) until the interrupt request registered in the queue is notified to the MPU. Hardware processing (see FIG. 3), (iii) interrupt processing and software processing for the interrupt (see FIG. 4), and (iv) software processing for the interrupt message (see FIG. 5). These are all executed independently and in parallel.

  (I) When there is an interrupt request from the N connected data sources 1-1, 1-2,..., 1-N, the history of interrupt requests is received in the FIFO buffer circuit 3-1, 3-2,. , 3-N (processing 31 to 34 in FIG. 2) and corresponding interrupt data are written to the data buffer circuits 4-1, 4-2,..., 4-N in the order of arrival (processing 35 in FIG. 2). ) Is executed in parallel. In the process 34 of FIG. 2, N types of information sources are integrated into one system. Here, integration means that each interrupt generation source is converted into channel number information and processed by one system circuit and one system buffer.

.., 2-N, FIFO buffer circuits 3-1, 3-2,..., 3-N, data buffer circuits 4-1, 4-2,. Since -N is arranged as hardware by the number of data sources 1-1, 1-2,..., 1-N, interrupts cannot be missed at this stage. There is a delay before it is registered in the matrix. The maximum time T is expressed by the following equation.
T = number of data sources N [U] / sampling period K [Hz] (Equation 1)
In general, if N is 2 to 20 and K is 100 MHz, T is 200 ns at the maximum. This can be said to be an order that can be sufficiently ignored as compared with the interrupt timing accuracy described above (see paragraph [0018]).

There are the following two types of interrupt requests from the data sources 1-1, 1-2,..., 1-N.
(A) One form is to receive only an interrupt request from the data sources 1-1, 1-2,..., 1-N, and actively transmit necessary data to the data sources 1-1, 1-2,. In the form of taking out from -N, it is often seen in the form of a signal path with the main purpose of notifying the occurrence of an event. This format tends to be a process with a relatively small amount of data, a low occurrence frequency, and a processing time allowance. In this case, the operations are executed in the order of processing 31 to 34 to processing 35. The edge signal 13 is generated from the interrupt request signal 11.

  (B) The other format is a format in which necessary data is passively received from the data sources 1-1, 1-2,..., 1-N, and an interrupt is actively generated by receiving the data. It is often seen in the form of communication channels that focus on data notification such as packet communication. This format tends to be a process that has a relatively large amount of data, a high frequency of occurrence, and a processing time that is not excessive. In this case, the operation is executed in the order of the process 35 to the processes 31-34. The edge signal 13 is generated from a signal indicating that writing has been completed from the data sources 1-1, 1-2,..., 1-N to the data buffer circuits 4-1, 4-2,. .

  Although the execution order and the generation method of the edge signal 13 are different in the above (A) and (B), the present invention is for interrupts from a plurality of data sources 1-1, 1-2,. The present invention is not limited to the above differences.

  (Ii) The interrupt controller 6 always extracts the interrupt information registered in the queue in the interrupt sampler circuit 5 one by one and issues the interrupt signal 16 to the MPU 7 (processes 36 to 41 in FIG. 3). The interrupt sampler circuit 5 performs processing for the next interrupt information in response to the interrupt completion response signal 17 from the MPU 77. As a result, multiple interrupts to the MPU 7 do not occur. Note that “A mod B” in the process 41 represents a remainder obtained by dividing A by B. n repeats the values 0, 1, 2, 3 ... N-2, N-1.

  (Iii) The processing in FIG. 4 is software processing in the MPU 7. As soon as the interrupt signal 18 is received, execution control is transferred to the jump destination (interrupt processing routine) of the corresponding interrupt vector (process 42 in FIG. 4). Processing in the interrupt processing routine varies depending on the execution environment. In an environment where a large-scale OS such as Windows (registered trademark) is installed, the interrupt event occurrence message is simply posted to the message queue (process 43 in FIG. 4), and the actual data is not read. A completion response signal 19 is issued to exit the processing. This is a part corresponding to a device driver.

  On the other hand, in an environment where no OS is installed or an environment where a simple OS is used, there is no need to divide the device driver and application software, so instead of processing 43 after removing (iv) Alternatively, the process 46 of FIG. 5 may be directly executed. The present invention does not consider the difference in execution environment.

  (Iv) The processing of FIG. 5 is also software processing in the MPU 7. The event handler is an execution process for the process 43 of FIG. 4, but data is actually read in the event handler (process 46). The execution timing is normally managed on the OS side, so there is no need to consider real-time characteristics.

  Next, with reference to FIG. 6, the interrupt processing timing when issued simultaneously from three data sources will be described. The three interrupt timings are described as being slightly shifted for convenience of explanation, but are assumed to be input almost simultaneously (50, 51, 52).

  Reference numerals 52, 53, and 54 denote waveforms at the edges, and interrupt information is written to the FIFO buffer times 3-1, 3-2,..., 3-N at this timing. The interrupt information is read out almost at the same time as the writing, and is added to the buffer in the interrupt sampler 5 after adding the information of the data source number. A counter 56 indicates the number of interrupt information input to the interrupt sampler 5. This counter is normally 0, but the number of information is +1 for writing and -1 for reading. The timing of +1 is indicated by 70, and the timing of -1 is indicated by 71. The writing and reading are not necessarily in pairs. Simultaneously with the read signal 57, an interrupt request signal 16 is output to the MPU 7.

  Reference numeral 58 denotes the MPU 7 software processing execution timing in response to the 57 interrupt request. 59 indicates the timing at which an interrupt process completion response is output upon completion of the process.

  Thus, the time delay due to hardware processing is a constant and negligible order, but the processing time in software depends on the contents of interrupt processing. Moreover, the use is also various. That is, by interposing software, the time variation from the interrupt request 11 from the data sources 1-1, 1-2,..., 1-N to the interrupt processing completion response 19 is large (the worst value cannot be estimated). ), Time estimation is impossible.

  However, the original purpose of interrupt processing must be considered from the viewpoint that data can be received at a predetermined timing. From this point of view, preparing the data buffer circuits 4-1, 4-2,. That is, the time until data output from the data sources 1-1, 1-2,..., 1-N is written to the data buffer circuits 4-1, 4-2,. In the invention, the writing process is executed by hardware processing and there is no restriction on the weight, so writing can be performed at the same rate as the output rate from the data sources 1-1, 1-2,. It is. On the other hand, the data buffer circuits 4-1, 4-2,..., 4-N need not be read immediately, and the data buffer circuits 4-1, 4-2,. It suffices to read within a range that does not become.

  As described above, the data buffer circuits 4-1, 4-2,..., 4-N serve as a buffer (for data) with respect to real-time processing. Similarly, in the data buffer circuits 4-1, 4-2,..., 4-N, the buffer in the interrupt sampler 5 serves as a buffer for interrupt information.

ここで、

とする。任意のn(n=1, 2, …, N)に対して

を満たす必要がなくなることが、緩衝の効果である。すなわち、式（３）から、式（２）に時間制約が緩和されたことになる。 It is common knowledge that the permissible time for the interrupt interval and the permissible time for the interrupt processing are originally designed to satisfy the following equation (2).

here,

And For any n (n = 1, 2,…, N)

It is a buffering effect that it is not necessary to satisfy the above. That is, the time constraint is relaxed from Equation (3) to Equation (2).

ここで、 As a further effect of the buffer, even if the expression (2) is not satisfied instantaneously, if the expressions (4) and (5) are satisfied, no interruption or data loss occurs.

here,

And

  According to the method of the present invention, the restriction of the software processing time for interrupt processing only needs to satisfy Expression (2), and in addition, multiple interrupt processing does not occur on the MPU 7. This eliminates the need for complicated considerations such as software reentrancy, and greatly facilitates software development and testing.

  In particular, in the measurement field and the like, there are very many cases where a plurality of sensors are attached and the data is sampled in real time, and this is an area where the present invention is easily effective.

1-1 to 1-N data source 2-1 to 2-N interrupt signal edge detection circuit
3-1 to 3-N FIFO buffer circuit 4-1 to 4-N data buffer circuit 5 Interrupt sampler circuit 6 Interrupt controller 7 MPU
8 Memory device 9 Control bus 10 Data bus

Claims (1)

In a computer that receives data from a plurality of data sources at an arbitrary timing,
A plurality of data buffer circuits for temporarily holding the plurality of data and sending them to the MPU;
A plurality of interrupt signal edge detection circuits that sequentially detect change points from the interrupt request signal from the data source and generate an edge signal;
A plurality of FIFO buffer circuits for temporarily holding the edge signal from the interrupt signal edge detection circuit;
An interrupt sampler circuit that registers the output of the FIFO buffer circuit in a queue;
An interrupt controller that reads the queue of the interrupt sampler circuit and generates an interrupt signal to the MPU;
A computer comprising:

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