WO2023229616A1

WO2023229616A1 - Distributed firmware interfacing processors and intergrated circuits

Info

Publication number: WO2023229616A1
Application number: PCT/US2022/037981
Authority: WO
Inventors: Hugh Roger MCCALMAN; Christopher Michael CORNISH
Original assignee: Rakuten Symphony Uk Ltd; Rakuten Mobile Usa Llc
Priority date: 2022-05-25
Filing date: 2022-07-22
Publication date: 2023-11-30

Abstract

A method and apparatus to interface a Central Processing Unit (CPU) and a Field Programable Gate Array (FPGA). The method and apparatus configured to accesses a large number of FPGA destination address locations with a small number of CPU address lines via any compatible bus interface where the CPU accesses the large number of address locations of the FPGA via a compatible bus interface, sends one or more commands to the FPGA, and the FPGA fills memory space of a First-In-First-Out (FIFO) memory buffer with one or more commands. The FPGA processes the one or more commands, fills another FIFO with the processing results, and asserts a command complete interrupt line on the CPU. The CPU reads the processing response of the one or more commands processed by the FPGA according to the asserted command complete interrupt and clears the command complete interrupt.

Description

DISTRIBUTED FIRMWARE INTERFACING PROCESSORS AND INTERGRATED CIRCUITS

TECHNICAL FIELD

[0001] In some example embodiments, the subject matter herein generally relates the field communications and in particular to interfacing processors.

BACKGROUND

[0002] Computer processors like a Central Processing Unit (CPU) and Field Programmable Gate Array (FPGA) often communicate with each in a variety of different applications. In addition, one or more CPUs and/or one or more FPGAs may interface with peripheral devices such as remote memory space. The interface may be between one or more CPUs and one or more FPGAs, may be between units or devices, between Printed Circuit Boards (PCBs), may be between elements on the same PCB or any combination of the foregoing.

[0003] Applications with a limited number of address lines are limited to the number of peripheral devices that they may communicate at any given time. For example a CPU with a limited number of address lines may be limited to the number of peripheral devices the CPU may communicate based on the limited number of address lines of the CPU. In the case where a CPU with a limited number of address lines has a need to communicate with a number of peripheral devices that exceeds the number of CPU address lines, additional CPUs may be necessary.

[0004] To simplify the interface, improve performance, and reduce cost, it would be desirable for applications with a limited number of address lines to access a large remote memory space. Thus, a need exists for a method and apparatus that allows a CPU with a limited number of address lines to communicate with a large number of peripheral devices.

SUMMARY

[0005] A system of one or more computers can be configured to perform particular operations or actions by virtue of having software, firmware, hardware, or a combination of them installed on the system that in operation causes or cause the system to perform the actions. One or more computer programs can be configured to perform particular operations or actions by virtue of including instructions that, when executed by data processing apparatus, cause the apparatus to perform the actions.

[0006] In one general aspect, a method may include accessing a large number of FPGA destination address locations with a small number of CPU address lines via any compatible bus interface. The method may include sending by the CPU one or more commands to the FPGA and filling memory space of the FPGA with the one or more commands. The method may in addition include processing the one or more commands by the FPGA and may moreover include asserting by the FPGA a response waiting interrupt line on the CPU. The method may also include reading a command response by the CPU and may furthermore include clearing the response waiting interrupt by the CPU. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0007] In another aspect, a processor interface apparatus may include a Central Processing Unit (CPU) having a small number of address lines. The processor interface apparatus may also include a Field Programable Gate Array (FPGA), the FPGA configured with a large number of address locations. The processor interface apparatus may furthermore include the CPU configured to: access the large number of address locations of the FPGA via a compatible bus interface, send one or more commands to the FPGA, and fill memory space of the FPGA with the one or more commands. The FPGA configured to: process the one or more commands; and assert a response waiting interrupt line on the CPU where the CPU is configured to read a command response according to the one or more commands processed by the FPGA based on the asserted response waiting in response interrupt. Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

[0008] Implementations may include one or more of the following features. The method where the large number of FPGA destination address locations is equal to or less than 65,536, and where the small number of CPU address lines is a sixteen bit access of the CPU, the sixteen bit access derived from four address lines. The method may include passing command messages between the CPU to a plurality of peripherals of the FPGA where one command may control one or more of the plurality of the peripherals of the FPGA based on an address of the peripheral. A clock timing of the peripherals is independent from the clock timing of the bus interface, and the method may include identifying unknown command messages via error detection codes. The method may include a read cycle control and a write cycle control, where the read cycle control and the write cycle control operate independently from each other. The method may include, the FPGA buffers the one or more commands into a First- In- First-Out (FIFO) memory buffer, and the FPGA fills another FIFO memory buffer with the processing result of the one or more commands. The method where a message structure includes a header and an operation specific payload, the header including a version of the bus interface, an operation to be performed, a message sequence identifier, and length of the payload. Implementations of the described techniques may include hardware, a method or process, or a computer tangible medium.

[0009] Implementations may also include one or more of the following features. The processor interface apparatus where the large number of address locations is equal to or less then 65,536, and where in the small number of CPU address lines is a sixteen bit access of the CPU, the sixteen bit access derived from four address lines. The processor interface apparatus where the CPU is further configured to pass command messages to a plurality of peripherals of the FPGA, and where one command may control one or more of the plurality of the peripherals of the FPGA based on an address of the peripheral. The processor interface apparatus where a clock timing of the peripherals is independent from the clock timing of the bus interface. The processor interface apparatus where unknown command messages are identified via error detection codes. The processor interface apparatus where the CPU further may include a read cycle control and a write cycle control, where the read cycle control and the write cycle control operate independently from each other. The processor interface apparatus where the FPGA is configured with two or more First-In-First-Out (FIFO) memory buffers, where the FPGA buffers the one or more commands into one of the two or more FIFO memory buffers, and the FPGA fills another of the two or more FIFO memory buffer with the processing result of the one or more commands. The processor interface apparatus where a message structure includes a header and an operation specific payload, the header including a version of the bus interface, an operation to be performed, a message sequence identifier, and length of the payload.

[0010] Other embodiments of this aspect include corresponding computer systems, apparatus, and computer programs recorded on one or more computer storage devices, each configured to perform the actions of the methods.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the following drawings:

[0012] Fig. 1 is a block diagram showing major parts of an interface between an FPGA coupled to one or more peripheral devices and a CPU;

[0013] Fig. 2 illustrates a state machine according to an embodiment;

[0014] Fig. 3 is a flowchart according to an embodiment; and

[0015] Fig. 4 is a flowchart of according to some embodiments.

DETAILED DESCRIPTION

[0016] Fig. 1 illustrates a block diagram showing major parts of an interface between an FPGA coupled to one or more peripheral devices and a CPU. The interfaces between the blocks are kept to a minimum number of simple signals that have a single specific function.

[0017] An access signal controller 102 is a main interface to the CPU (not shown) and generates the read write cycles on the bus 104. While Fig. 1 illustrates an example using a generic access signal controller 102 and bus 104. It should be understood that any compatible bus interface may be used, for example a peripheral component interconnect (PCI) bus, a host port interface (HPI), and the like may be used. That is, the design allows the interface, access signal controller 102 and bus 104 to be exchanged with any compatible bus interface. Thus, any compatible processor and bus interface may be implemented consistent with the disclosure.

[0018] An interface controller 108 manages the handling of commands including sending commands to a plurality of peripherals A-n 112. The interface controller 108 manages the data/control OR returns the read data and controls the signals from the plurality of peripheral devices 112. The plurality of peripheral devices perform commands generated by the CPU. The FPGA may interface with the CPU (not shown) via two independent First-In-First-Out (FIFO) memory buffers which are controlled by a direct memory access (DMA) engine within the CPU. The DMA engine transfers data to/from the CPU to/from the two independent FIFOs of the FPGA.

[0019] To minimize signaling and ease routing, an external memory interface may be used to communicate between a CPU and FPGA where the CPU and FPGA use the same message interface, for example an External Memory Interface (EMIF) is an example of a memory interface between the CPU and FPGA.

[0020] A CPU may use four address lines (A1-A4) to provide a 16 register by 16 bits interface. One register address is used for the message interface. The CPU will write commands to this address and the FPGA will buffer the command into a FIFO memory. Once commands are processed by the FPGA, the FPGA will fill another Fl FO with the processing result.

[0021] Thus, a CPU or similar processor with a small number of address lines may exercise control of a large number of destination address. For example, the large number of FPGA destination address locations may be as many as 65,536, and where the small number of CPU address lines is a sixteen bit access of the CPU, the sixteen bit access derived from four address lines.

[0022] Fig. 2 illustrates a state machine according to an embodiment. At 202 a CPU is in a idle state, and at 204 the CPU generates a new request, for example a command. The CPU sends the command (cmd) at 206, raises a command ready flag at 208, and waits for the FPGA to read the command at 210. The FPGA processes the command at 212 and at 214 generates a response that command is complete. The FPGA then asserts a command complete interrupt at 216. The CPU processes the response at 218 and clears the command complete interrupt at 220.

[0023] A CPU will use 1 register address for the message interface and will write data to this address. The FPGA processing may be divided into peripherals each which has its own address identifier.

[0024] The FPGA will buffer the command data in a FIFO memory. The FIFO will process the command message and fill another FIFO memory with the result. The FPGA will assert a response waiting interrupt line on the CPU. The FPGA may use an existing general-purpose input/output (GIPO) to assert the interrupt line. The CPU will then read the response from the FPGA FIFO indicating that the message exchange is now complete.

[0025] Fig. 3 is a flowchart of an example process 300. In some implementations, one or more process blocks of Fig. 3 may be performed by a one or more including a CPU and FPGA.

[0026] As shown in Fig. 3, process 300 may include accessing a large number of FPGA destination address locations with a small number of CPU address lines via any compatible bus interface 302. For example, a CPU may access a large number of FPGA (65,536) destination address locations with a small number of address lines, for example four address lines, via any compatible bus interface, as described above.

[0027] As also shown in Fig. 3, process 300 may include sending by the CPU the one or more commands to the FPGA 304. The process 300 may include filling memory space of the FPGA with one or more commands 306. For example, the CPU may fill a FIFO memory of the FPGA with one or more commands, as described above. As also shown in Fig. 3, process 300 may include processing the one or more commands by the FPGA 308. As shown at 310, process 300 may include filling memory space of the FPGA with one or more command responses. For example, the FPGA may fill another FIFO of the FPGA with one or more command responses, as described above.

[0028] As further shown in Fig. 3, process 300 may include asserting by the FPGA a response waiting interrupt line on the CPU 312. As also shown in Fig. 3, process 300 may include reading a command response by the CPU 314. As further shown in Fig. 3, process 300 may include clearing the response waiting interrupt by the CPU 316.

[0029] Process 300 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.

[0030] Fig. 4 is a flowchart of an example process 400. In some implementations, one or more process blocks of Fig. 4 may be performed by a single device. [0031] Process 400 may include additional implementations, such as any single implementation or any combination of implementations described below and/or in connection with one or more other processes described elsewhere herein.

[0032] In a first implementation, process 400 may include passing command messages between the CPU to a plurality of peripherals of the FPGA where one command may control a plurality of the peripherals of the FPGA based on an address of the peripheral at 402, were a clock timing of the peripherals is independent from the clock timing of the bus interface. The number of peripheral addresses may be as much as 65,536.

[0033] In a second implementation, alone or in combination with one or more of the first implementation, process 400 may include identifying unknown command messages via error detection codes at 404.

[0034] In a third implementation, alone or in combination with one or more of the first and second implementations, process 400 may include a read cycle control and a write cycle control, where the read cycle control and the write cycle control operate independently from each other at 406.

[0035] In a forth implementation, alone or in combination with one or more of the first through third implementations, the FPGA buffers the one or more commands into a First-In-First-Out (FIFO) memory buffer, and the FPGA fills another FIFO memory buffer with the processing result of the one or more commands at 408.

[0036] The message structure for the above commands and corresponding responses includes a header, an operation specific payload, the header including a version of the bus interface, an operation to be performed, a message sequence identifier, and length of the payload.

[0037] Although Fig. 4 shows example blocks of process 400, in some implementations, process 400 may include additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in Fig. 4. Additionally, or alternatively, two or more of the blocks of process 400 may be performed in parallel.

[0038] While aspects of the disclosure have been illustrated and described in detail in the drawings and foregoing description, such illustrations and description are to be considered illustrative or exemplary and not restrictive; the disclosure is not limited to the disclosed embodiments. [0039] Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed features, from a study of the drawings, the disclosure, and the appended claims.

[0040] In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality.

[0041] A single processor, device or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

[0042] Operations like acquiring, accessing, determining, obtaining, outputting, providing, store or storing, calculating, simulating, receiving, warning, and stopping can be implemented as program code means of a computer program and/or as dedicated hardware.

[0043] A computer program may be stored and/or distributed on a suitable medium, such as an optical storage medium or a solid-state medium, supplied together with or as part of other hardware, but may also be distributed in other forms, such as via the Internet or other wired or wireless telecommunication systems.

Claims

CLAIMS:

1. A method of interfacing a Central Processing Unit (CPU) and a Field Programable Gate Array (FPGA), the method comprising: accessing a large number of FPGA destination address locations with a small number of CPU address lines via any compatible bus interface; sending by the CPU the one or more commands to the FPGA; filling memory space of the FPGA with one or more commands; processing the one or more commands by the FPGA; asserting by the FPGA a response waiting interrupt line on the CPU; reading a command response by the CPU; and clearing the response waiting interrupt by the CPU.

2. The method according to claim 1 , wherein the large number of FPGA destination address locations is equal to or less than 65,536, and wherein the small number of CPU address lines is a sixteen bit access of the CPU, the sixteen bit access derived from four address lines.

3. The method according to claim 1 , further comprising passing command messages between the CPU to a plurality of peripherals of the FPGA wherein one command may control one or more of the plurality of the peripherals of the FPGA based on an address of the peripheral.

4. The method according to claim 3, wherein a clock timing of the peripherals is independent from the clock timing of the bus interface.

5. The method according to claim 1 , further comprising identifying unknown command messages via error detection codes.

6. The method according to claim 1 , further comprising a read cycle control and a write cycle control, wherein the read cycle control and the write cycle control operate independently from each other.

7. The method according to claim 1 , wherein the FPGA buffers the one or more commands into a First- In- First-Out (FIFO) memory buffer, and the FPGA fills another FIFO memory buffer with a processing result of the one or more commands.

8. The method according to claim 1 , wherein a message structure includes a header and an operation specific payload, the header including a version of the bus interface, an operation to be performed, a message sequence identifier, and length of the payload.

9. A processor interface apparatus comprising: a Central Processing Unit (CPU) having a small number of address lines; and a Field Programable Gate Array (FPGA), the FPGA configured with a large number of address locations; the CPU configured to: access the large number of address locations of the FPGA via a compatible bus interface; send one or more commands to the FPGA; and fill memory space of the FPGA with the one or more commands; the FPGA configured to: process the one or more commands; and assert a response waiting interrupt line on the CPU; and the CPU further configured to: read a command response according to the one or more commands processed by the FPGA based on the asserted response waiting interrupt; and clear the response waiting interrupt.

10. The processor interface apparatus of claim 9, where the large number of address locations is equal to or less then 65,536, and where in the small number of CPU address lines is a sixteen bit access of the CPU, the sixteen bit access derived from four address lines.

11 . The processor interface apparatus of claim 9, wherein the CPU is further configured to pass command messages to a plurality of peripherals of the FPGA, and wherein one command may control one or more of plurality of the peripherals of the FPGA based on an address of the peripheral.

12. The processor interface apparatus of claim 11 , wherein a clock timing of the peripherals is independent from the clock timing of the bus interface.

13. The processor interface apparatus of claim 9, wherein unknown command messages are identified via error detection codes.

14. The processor interface apparatus of claim 9, wherein the CPU further comprises a read cycle control and a write cycle control, wherein the read cycle control and the write cycle control operate independently from each other.

15. The processor interface apparatus of claim 9, wherein the FPGA is configured with two or more First-In-First-Out (FIFO) memory buffers, wherein the FPGA buffers the one or more commands into one of the two or more FIFO memory buffers, and the FPGA fills another of the two or more FIFO memory buffer with a processing result of the one or more commands.

16. The processor interface apparatus of claim 9, wherein a message structure includes a header and an operation specific payload, the header including a version of the bus interface, an operation to be performed, a message sequence identifier, and length of the payload.