JP2007285737A - Semiconductor test device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor test device capable of improving the throughput of DUT (device under test) inspection. <P>SOLUTION: In the semiconductor test device wherein a measurement operation part and a controller are connected via a system bus, and which is so configured that a plurality of interrupt processings are performed between the measurement operation part and the controller, the operation part includes an interrupt control means which performs control giving priorities to a plurality of interruptions to the controller. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor inspection apparatus, and more particularly to an improvement in throughput by improving an interrupt operation associated with measurement data transfer.

  A type of semiconductor testing device such as a memory tester or LSI tester that determines the pass / fail of the device under measurement (hereinafter referred to as DUT). Once the DUT measurement data is temporarily stored in the memory that constitutes the measurement calculation unit, the measurement data is To the computing unit to perform the necessary arithmetic processing for pass / fail judgment, and transfer the measurement data processed by the measurement arithmetic unit to the control unit for controlling the operation of the entire apparatus and performing the DUT pass / fail judgment and other computations There is something configured to do.

  FIG. 3 is a block diagram showing the main part of an example of a conventional semiconductor inspection apparatus. In FIG. 3, the measurement calculation unit 10 and the control unit 20 are connected to each other via a system bus 30.

  The measurement calculation unit 10 performs storage calculation processing of measurement data and transfers the processed data to the control unit 20, and includes a measurement data memory 11, a calculation unit 12, a bus command adder 13, a buffer memory 14, and a bus interface. 15 or the like.

  The measurement data memory 11 stores DUT measurement data measured by a test head (not shown).

  The arithmetic unit 12 sequentially reads out the data stored in the measurement data memory 11 and performs arithmetic processing necessary for measurement.

  The bus command adder 13 generates and adds a predetermined command so that the calculation result data of the calculator 12 can be transmitted to the control unit 20 via the system bus 30.

  The buffer memory 14 compensates for a speed difference between the arithmetic unit 12 or bus command adder 13 in the preceding stage and the bus interface 15 in the subsequent stage, and uses a first-in first-out (FIFO) type memory.

  The bus interface 15 performs protocol conversion for performing data transmission between the internal bus 16 of the measurement calculation unit 10 and the system bus 30.

  The control unit 20 controls the measurement calculation unit 10 and processes calculation result data, and includes a processor 21, an interrupt reception circuit 22, a buffer memory 23, a bus interface 24, and the like.

  The processor 21 performs various controls and calculation result data processing.

  The interrupt receiving circuit 22 receives an interrupt access from the measurement calculation unit 10 and interrupts the processor 21.

  The buffer memory 23 stores calculation result data written using a program of the processor 21 and a DMA (direct memory access) module provided in the bus interface 15.

  The bus interface 24 performs protocol conversion for performing data transmission between the internal bus 25 of the control unit 20 and the system bus 30.

The operation of the configuration of FIG. 3 will be described using the timing chart of FIG.
The measurement data of the DUT is written into the measurement data memory 11.

  The measurement calculation unit 10 starts a series of operations in response to a command from the control unit 20. Data (d1 to d8) stored in the measurement data memory 11 are sequentially read out to the calculator 12 for performing a predetermined calculation. When the measurement data necessary for calculation is read, end data (end) is transmitted.

  The computing unit 12 performs a predetermined computation and outputs a group of computation result data (c1 to c4) and computation result end data (cend) to the bus command generator 13. The number of calculation result data and the calculation time depend on the calculation type and data contents.

  The bus command generator 13 adds the bus command (cd) to the calculation results (c 1 to c 4) of the calculator 12 and outputs the result to the buffer memory 14.

  The data stored in the buffer memory 14 is read to the bus interface 15 and transferred and stored in the buffer memory 23 of the control unit 20 via the system bus 30 and the bus interface 24 of the control unit 20. The buffer memory 23 of the control unit 20 is DMAed by a DMA module provided in the bus interface 15.

  The bus interface 15 converts a bus command into a protocol of the system bus 30 and generates a system bus cycle.

  When receiving the calculation result end data (cend) transmitted from the measurement calculation unit 10, the interrupt reception circuit 22 of the control unit 20 generates an interrupt signal and notifies the processor 21 of the end of the calculation result data. The processor 21 processes the sent calculation result data and transmits the next data transfer command to the measurement calculation unit 10.

Patent Document 1 discloses a technique that can improve the throughput of semiconductor testing.
JP2002-1331397

  By the way, according to the configuration of FIG. 3, the speed of the computing unit 12 constituting the measurement computation unit 10 varies depending on the computation type and computation result data. Therefore, when these processes are performed continuously, a relatively long stop occurs between the end of a series of calculation result data transfer and the output of the next measurement data transfer command to the measurement calculation unit 10. Time may occur.

  However, if the stop time becomes long, the number of inspections of DUTs per unit time of the semiconductor inspection apparatus decreases and inspection efficiency is lowered.

  The present invention pays attention to such a conventional problem, and an object thereof is to provide a semiconductor inspection apparatus capable of improving the throughput of the DUT inspection.

The invention of claim 1 that achieves the above-mentioned object is as follows.
In the semiconductor inspection apparatus configured to apply a plurality of interrupt processing between the measurement calculation unit and the control unit, the measurement calculation unit and the control unit are connected via the system bus.
The arithmetic unit is provided with interrupt control means for giving priority to and controlling a plurality of interrupts for the control unit.

The invention of claim 2 is the semiconductor inspection apparatus according to claim 1,
The interrupt control means includes: an interrupt permission setting unit that individually grants permission to a plurality of interrupts; a priority setting unit that sets priorities for a plurality of permitted interrupts; and a temporary interrupt with a priority set. It is characterized by comprising an interrupt storage unit for storing it automatically.

According to a third aspect of the present invention, in the semiconductor inspection apparatus according to the first aspect,
The arithmetic unit is provided with interrupt signal separating means for separating an interrupt signal from an internal bus of the arithmetic unit.

A fourth aspect of the present invention is the semiconductor inspection apparatus according to any one of the first to third aspects,
The interrupt includes a group of measurement data transfer end notification from the measurement data memory to the arithmetic unit in the measurement arithmetic unit and a series of arithmetic result data transfer end notification from the arithmetic unit of the measurement arithmetic unit to the control unit. To do.

  As a result, the transfer of calculation result data, the group of measurement data from the measurement data memory to the calculator, the calculation, and the like can be processed in parallel between the measurement calculation unit and the control unit, thereby increasing the throughput of the DUT inspection. be able to.

  Hereinafter, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention, and the same reference numerals are given to portions common to FIG. The difference between the configurations of FIG. 1 and FIG. 3 is that an interrupt separation circuit 17 and an interrupt control circuit 18 are added.

  The interrupt signal separation circuit 17 separates data related to the interrupt from the data flowing through the internal bus 16 so as not to flow to the bus interface 15 and sends the separated data to the interrupt control circuit 18.

  The interrupt control circuit 18 manages and controls interrupt permission, priority, and the like for a plurality of interrupt signals generated in the measurement arithmetic unit 10, and includes an interrupt permission setting unit 181, a priority setting unit 182, and an interrupt storage unit 183. It consists of

  The interrupt permission setting unit 181 selectively sets whether to permit an interrupt individually for each of a plurality of interrupt signals. In this embodiment, the interrupt permission setting unit 181 includes an interrupt signal that is output when reading of measurement data from the measurement data memory 11 to the computing unit 12 is completed, and an interrupt signal that is separated by the interrupt signal separation circuit 17. In this example, other interrupt signals such as error information are input and one or more of these interrupt signals are selectively permitted.

  The priority order setting unit 182 performs prioritization as to which interrupt signal is sent first when a plurality of permitted interrupt signals are received at the same time. It is possible to give priority to an interrupt signal output when reading of measurement data is completed.

  The interrupt storage unit 183 temporarily outputs the plurality of interrupt signals output from the priority setting unit 182 according to the priority order so that the next interrupt signal is not output to the bus interface 15 until the interrupt processing being executed is completed. Are stored in sequence.

FIG. 2 is a timing chart for explaining the operation of FIG.
The measurement data of the DUT is written into the measurement data memory 11.

  The measurement calculation unit 10 starts a series of operations in response to a command from the control unit 20. Data (d1 to d8) stored in the measurement data memory 11 are sequentially read out to the calculator 12 for performing a predetermined calculation. When the measurement data necessary for the calculation is read, end data (end) for notifying the end of the group of measurement data transfer from the measurement data memory 11 to the calculator 12 is sent, and an interrupt permission setting unit of the interrupt control circuit 18 is sent. An interrupt signal is sent to 181 to notify the end of the group of measurement data transfer. The interrupt permission setting unit 181 includes an interrupt signal for notifying the end of a group of measurement data transfer, and other interrupt signals such as an interrupt signal flowing through the internal bus 16 separated by the interrupt signal separation circuit 17 and error information. Entered.

  The computing unit 12 performs necessary computations, and outputs a series of computation result data (c1 to c4) and computation result end data (cend) to the bus command generator 13. The number of calculation result data and the calculation time depend on the calculation type and data contents.

  The bus command generator 13 adds the bus command (cd) to the calculation results (c 1 to c 4) of the calculator 12 and outputs the result to the buffer memory 14.

  The data stored in the buffer memory 14 is read to the bus interface 15 and transferred and stored in the buffer memory 23 of the control unit 20 via the system bus 30 and the bus interface 24 of the control unit 20. The buffer memory 23 of the control unit 20 is DMAed by a DMA module provided in the bus interface 15.

  The bus interface 15 converts a bus command into a protocol of the system bus 30 and generates a system bus cycle.

  When interrupt permission is given to a group of measurement data transfer end notification interrupt signals input to the interrupt permission setting unit 181 of the interrupt control circuit 18, the interrupt storage unit 183 stores the interrupt permission through the priority setting unit 182. . If there is no other waiting interrupt signal at that time, it is immediately sent to the bus interface 15, and as an interrupt access (fin) to the processor 21 of the control unit 20, the system bus 30, the bus interface 24 of the control unit 20 and the interrupt receiving circuit 22 is transmitted.

  When the processor 21 receives the interrupt signal of the group of measurement data transfer completion notification, the processor 21 clears the interrupt storage unit 183 and requests the measurement data memory 11 to transfer the next group of measurement data to the computing unit 12. Start up.

  As a result, before the transfer of a series of calculation result data is completed, the measurement data memory 11 can be activated to request the next group of data transfer, so that the stop time can be shortened compared to the conventional case. And the throughput of the DUT inspection can be improved.

  The operation result transfer end data (cend) after the series of operation result data is transferred is separated as an interrupt signal by the interrupt signal separation circuit 17 and sent to the interrupt control circuit 18 without being sent to the bus interface 15. The interrupt control circuit 18 temporarily stores the interrupt signal indicating the completion of the operation result transfer in the interrupt storage unit 183. If there is an interrupt signal waiting, the interrupt control circuit 18 generates the next interrupt cycle after the interrupt processing is completed.

  Thereby, it is possible to prevent the interrupt to the processor 21 from overlapping. When receiving an interrupt cycle based on the operation result transfer end data (cend), the interrupt receiving circuit 22 of the control unit 20 generates an interrupt signal and notifies the processor 21 of the end of operation result data transfer.

  In the present invention, a mechanism is provided in which an interrupt for notifying the end of transfer of a group of measurement data from the measurement data memory can be applied separately from the interrupt for notifying the end of transfer of calculation result data. As a result, in the conventional apparatus, the next operation command cannot be issued until the transfer of the calculation result data is completed, but the transfer of the next group of measurement data from the measurement data memory is performed in parallel with the transfer of the calculation result data. This makes it possible to increase the throughput of the DUT inspection.

  In the above embodiment, the example in which the next group of measurement data is transferred from the measurement data memory to the calculator in parallel with the transfer of the calculation result data has been described. However, the calculation and the data transfer can be processed in parallel. is there.

  As described above, according to the present invention, a semiconductor inspection apparatus with high throughput can be realized.

It is a block diagram which shows one Example of this invention. 2 is a timing chart illustrating the operation of FIG. 1. It is a block diagram which shows the principal part of an example of the conventional semiconductor inspection apparatus. 4 is a timing chart for explaining the operation of FIG. 3.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Measurement calculating part 11 Measurement data memory 12 Calculator 13 Bus command generator 14 Buffer memory 15 Bus interface 16 Internal bus 17 Interrupt signal separation circuit 18 Interrupt control circuit 181 Interrupt permission setting part 182 Priority setting part 183 Interrupt storage part 20 Control Unit 21 Processor 22 Interrupt reception circuit 23 Buffer memory 24 Bus interface 25 Internal bus 30 System bus

Claims (4)

In the semiconductor inspection apparatus configured to apply a plurality of interrupt processing between the measurement calculation unit and the control unit, the measurement calculation unit and the control unit are connected via the system bus.
A semiconductor inspection apparatus, wherein the arithmetic unit is provided with interrupt control means for controlling a plurality of interrupts for the control unit with priority.   The interrupt control means includes an interrupt permission setting unit that individually grants permission to a plurality of interrupts, a priority setting unit that sets priorities for a plurality of permitted interrupts, and a temporary interrupt with a set priority. 2. The semiconductor inspection apparatus according to claim 1, further comprising an interrupt storage unit for storing the same.   2. The semiconductor inspection apparatus according to claim 1, wherein the arithmetic unit is provided with interrupt signal separating means for isolating an interrupt signal from an internal bus of the arithmetic unit. The interrupt includes a group of measurement data transfer end notification from the measurement data memory to the arithmetic unit in the measurement arithmetic unit and a series of arithmetic result data transfer end notification from the arithmetic unit of the measurement arithmetic unit to the control unit. The semiconductor inspection apparatus according to claim 1.

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