JP2012093944A - Information processor and information processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide high-speed reading to a calculation register while securing data reliability.SOLUTION: The information processor comprises: a load request generation part; a load buffer for storing load data to individual load requests and transferring them into a calculation register; a memory network for inputting the load request generated by the load request generation part, reading the load data to the load request from a main memory, and controlling the main memory so that accompanying information, generated by the main memory, indicating the order in which the load data is read from the load buffer should be sent out prior to the load data; and an alignment determination part for detecting delay of arrival of the load data corresponding to the accompanying information on the basis thereof and adjusting a start time of reading from the load buffer to the calculation register on the basis of delay of arrival of the load data.

Description

  The present invention relates to an information processing apparatus.

  Conventionally, (1) a plurality of load requests specified by an instruction is generated from one load instruction, (2) load data for each load request is temporarily stored in a load buffer, and (3) all load data Is known to be stored in a load buffer, and (4) an information processing device is known that transfers load data from the load buffer to an arithmetic register. Such an information processing apparatus is disclosed in Patent Document 1, for example.

  FIG. 10 is a diagram illustrating a configuration of an integer determination unit that determines that load data is stored in a load buffer in a conventional information processing apparatus. In FIG. 10, reference numeral 701 denotes a TAG recognition timing adjustment circuit, which carries around TAGs received by four ports for eight cycles, and has a function of identifying and counting TAGs at a timing corresponding to the reading order from the load buffer. The operation of this alignment determination unit is shown in FIGS. 11A and 11B.

  FIG. 11A is a time chart showing the operation of the alignment determination unit, and FIG. 11B is a time chart following FIG. 11A. 11A and 11B, the vertical axis represents a sequence identification number (hereinafter referred to as “No.”), and the horizontal axis represents the number of clocks. 11A and 11B show an operation in the case of storing load data in the load buffer # 0 when the TAG arrives ideally in the conventional alignment determination unit. Note that the ideal arrival of the TAG is shown in No. 4-7. In the conventional integer determination unit, No. 1 in FIG. As shown at 24, the load buffer # 0 alignment determination counter counts the number of TAGs for 32 elements. In FIG. It is determined that the load data is stored in the load buffer by completing counting of the number of TAGs for 32 elements at 24 clocks 25.

JP 2009-252133 A

  However, in a conventional information processing apparatus including an integer determination unit, all the replies are identified by identifying the accompanying information (TAG) at each timing carried by the register after the load data is temporarily stored in the load buffer. It is determined whether or not (load data) is aligned (alignment determination). For this reason, the conventional information processing apparatus has a problem that it takes a long time to start the transfer of load data from the load buffer to the arithmetic register after performing the alignment determination.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide an information processing apparatus capable of shortening the time required to load data to an operation register.

  One aspect of the information processing apparatus according to the present invention is a load request disassembling unit that generates a plurality of load requests from one load instruction, a load buffer that stores load data for each of the load requests, and transfers the load data to an arithmetic register. The load request generated by the load request decomposition unit is input, the load data for the load request is read from the main memory, and the load data generated by the main memory is read out from the load buffer. And detecting a delay in arrival of the load data corresponding to the accompanying information based on the accompanying information received from the memory network and a memory network that controls the accompanying information to be transmitted prior to the load data. , Said b Based on the delay of the arrival of the Dodeta, characterized in that and a alignment judging unit for adjusting the read start time of the load data from the load buffer to the arithmetic register.

  The information processing apparatus according to the present invention can provide an information processing apparatus that can reduce the time required to load data to the arithmetic register.

It is a figure which shows the structure of the information processing apparatus which concerns on embodiment of this invention. It is a figure which shows the structure of the alignment determination part in the information processing apparatus which concerns on embodiment of this invention. It is a figure which shows how the load data from the memory with respect to the load request decomposed | disassembled into 32 pieces is stored in a load buffer in the information processing apparatus which concerns on embodiment of this invention. It is a figure which shows the connection relation of a load buffer and an arithmetic register in the information processing apparatus which concerns on this Embodiment. It is a flowchart which shows operation | movement of the information processing apparatus which concerns on embodiment of this invention. 5 is a table showing counter set values set for each element number in the information processing apparatus according to the embodiment of the present invention. It is a time chart which shows operation | movement of the information processing apparatus which concerns on embodiment of this invention. It is a time chart which shows operation | movement of the information processing apparatus which concerns on embodiment of this invention, and is a time chart following FIG. 7A. 6 is a time chart showing an operation when the arrival order of TAG (and load data) is disturbed in the information processing apparatus according to the embodiment of the present invention. FIG. 8B is a time chart showing the operation when the arrival order of TAG (and load data) is disturbed in the information processing apparatus according to the embodiment of the present invention, and is a time chart following FIG. 8A. It is a time chart which shows operation | movement when the arrival order of TAG (and load data) is disturbed in a comparative example. FIG. 9B is a time chart showing the operation when the arrival order of TAG (and load data) is disturbed in the comparative example, and is a time chart following FIG. 9A. It is a figure which shows the structure of the conventional alignment determination part. It is a time chart which shows operation | movement of the conventional information processing apparatus. It is a time chart which shows operation | movement of the conventional information processing apparatus, and is a time chart following FIG. 11A.

  Hereinafter, an information processing apparatus according to the present invention will be described with reference to the accompanying drawings. First, before detailed description of the invention, the outline of the information processing apparatus according to the present invention will be described with reference to FIG. 1 showing an information processing apparatus according to an embodiment described later. The information processing apparatus includes a load request decomposition unit 103, a memory network (bound) 104, a memory network (return) 106, an alignment determination unit 107, and a load buffer 109.

  The load request decomposition unit 103 generates a plurality of load requests from one load instruction. The memory network (bound) 104 receives the load request generated by the load request decomposing unit 103 and reads load data corresponding to the load request from the main memory 105. The memory network (return) 106 sends the accompanying information generated by the main memory 105 to the alignment determination unit 107 prior to the load data. The accompanying information includes information indicating the order of reading the load data from the load buffer 109.

  The alignment determination unit 107 detects the arrival delay of the load data corresponding to the accompanying information based on the accompanying information received from the memory network (return) 106. Then, the alignment determination unit 107 adjusts the load data read start time from the load buffer 109 to the arithmetic register 110 based on the detected delay of arrival of the load data. The load buffer 109 stores load data for each load request and transfers it to the arithmetic register 110.

  In addition, the load request decomposition unit 103 sends the number of load requests to the alignment determination unit 107. The alignment determination unit 107 adjusts the start time of reading from the load buffer 109 to the arithmetic register 110 by comparing the number of load requests with the number of received accompanying information.

  As described above, the information processing apparatus according to the present invention sends the accompanying information to the alignment determining unit 107 prior to the load data, and the alignment determining unit 107 detects a delay in arrival of the load data based on the accompanying information. This makes it possible to wait for the arrival of load data as in the past, and to determine whether or not all the load data has been prepared. Can be determined whether has arrived in the load buffer. As a result, it is possible to reduce the time required to start the transfer of load data from the load buffer 109 to the arithmetic register 110.

Embodiment.
Next, a detailed configuration of the present invention will be described. FIG. 1 is a diagram showing a configuration of an information processing apparatus according to an embodiment of the present invention. In FIG. 1, reference numeral 101 denotes an instruction issuing unit that issues a load instruction. Reference numeral 102 denotes a use load buffer determination unit which determines the load buffer number used by the load instruction issued in 101 and sends it to 103 together with the load instruction. Reference numeral 103 denotes a load request decomposition unit which decomposes a load instruction into a load request for the designated number of elements and sends it to 104, and also notifies the load buffer number and load instruction information determined in 102 to the load buffer use notification. To the alignment determination unit 107. When decomposing into load requests for the number of elements, the load request decomposing unit 103 attaches and sends the load buffer storage position information to the load request as accompanying information.

  Reference numeral 104 denotes a memory network (bound), which distributes the load request and accompanying information sent from the load request decomposing unit 103 to a bank corresponding to the memory address, and performs arbitration between the load requests as necessary to the main memory 105. Send it out. Reference numeral 105 denotes a main memory which reads out data at an address designated by the load request from a RAM (Random Access Memory) and sends it to the memory network (return) 106. At that time, the main memory 105 uses the time difference from the start of the read sequence until the data is read, and sends the load request accompanying information to the memory network (return) 106 10 cycles before the data is sent. A dotted arrow in FIG. 1 indicates a path of accompanying information (hereinafter referred to as TAG) of the return side load request.

  Reference numeral 106 denotes a memory network (return), which identifies the destination port from the TAG information received from the main memory 105, arbitrates the TAG and load data, the TAG is sent to the alignment determination unit 107, and the data is sent to the load buffer 109. Send it out. At that time, the memory network (return) 106 sends the TAG and the load data to the alignment determination unit 107 and the load buffer 109 while maintaining the timing of the TAG and the load data sent 10 cycles ahead of the data. Send it out.

  An alignment determination unit 107 identifies a load buffer number from the TAG received from the memory network (return) 106, determines that TAGs corresponding to the number of elements specified by the load instruction have returned, and the load buffer 109 In addition, a load data transfer start instruction to the arithmetic register is sent to the arithmetic register 110. The alignment determination unit 107 sends the received TAG to the reply TAG timing adjustment unit 108.

  Reference numeral 108 denotes a reply TAG timing adjustment unit, which receives a reply TAG for four ports from the alignment determination unit 107, adjusts the timing for nine cycles, and matches the timing at which data is sent from the memory network (return) 106 to the load buffer 109. TAG is sent to the load buffer 109. A load buffer 109 receives load data and TAG for four ports, identifies the load buffer storage position from the TAG, and stores the load data. In addition, the load buffer 109 receives the operation register transfer start instruction from the alignment determination unit 107, sequentially reads the load data of the designated load buffer number, and sends it to the operation register 110.

  An operation register 110 receives an operation register transfer instruction from the alignment determination unit 107, and stores the load data sent from the load buffer 109 in a designated register. In addition, upon receiving an operation start instruction from the alignment determination unit 107, the operation register 110 sequentially reads stored data and sends it to the operation unit 111. An arithmetic unit 111 receives an instruction from the alignment determination unit 107, performs a specified operation on the load data sent from the operation register 110, and stores the load data in the operation register 110. Note that the operation of storing the output of the arithmetic unit 111 in the arithmetic register 110 is a general operation and is not shown in the figure.

  FIG. 2 is a diagram showing a configuration of the alignment determination unit in the information processing apparatus according to the embodiment of the present invention. Here, the load buffer 109 that holds the load data is composed of a load buffer # 0 and a load buffer # 1. The alignment determination unit 107 includes a part that manages the transfer timing of the load buffer # 0 to the arithmetic register 110 and a part that manages the transfer timing of the load buffer # 1 to the arithmetic register 110.

  The management part on the load buffer # 0 side includes a TAG number counter 201, a counter set value maximum value detection circuit 202, an alignment determination counter control circuit 210, an alignment determination counter 271, a load instruction information storage register 270, and an alignment timing adjustment counter control circuit 211. , An alignment timing adjustment counter 272 and an arithmetic register transfer start condition confirmation circuit 220 are provided.

  On the other hand, the management part on the load buffer # 1 side includes a TAG number counter 203, a counter set value maximum value detection circuit 204, an alignment determination counter control circuit 212, an alignment determination counter 275, a load instruction information storage register 274, and an alignment timing adjustment counter control. A circuit 213, an alignment timing adjustment counter 276, and an arithmetic register transfer start condition confirmation circuit 221 are provided.

  In FIG. 2, reference numeral 250 denotes a TAG reception register which receives TAGs for four ports sent from the memory network (return) 106 and holds them for one cycle. The TAG reception register 250 is shared by the load buffers # 0 and # 1.

  The management part on the load buffer # 0 side and the management part on the load buffer # 1 side have substantially the same configuration. Hereinafter, each element will be described by taking the load buffer # 0 side as an example. Reference numeral 201 denotes a TAG counter for the load buffer # 0, which counts the number of TAGs in one clock addressed to the load buffer # 0. In the present embodiment, the maximum value of the count result is “4”, which is the same as the number of ports.

  Reference numeral 202 denotes a counter set value maximum value detection circuit for the load buffer # 0, which identifies the element number from the TAG addressed to the load buffer # 0 and detects the maximum value of the counter set value corresponding to the element number. Specifically, the counter set value maximum value detection circuit 202 refers to each counter set value corresponding to an element number included in a plurality of TAGs according to a predetermined table in FIG. Of these, the maximum counter set value is held. In other words, the counter set value maximum value detection circuit 202 detects the delay of the load data corresponding to the TAG based on the element number included in the TAG. Further, the counter set value maximum value detection circuit 202 holds the maximum value of the counter set value corresponding to the element number, so that the transfer start time is based on the maximum delay time among the delay times of the plurality of load data. Plays the function of adjusting.

  Reference numeral 210 denotes an alignment determination counter control circuit for the load buffer # 0. The alignment determination counter control circuit 210 subtracts the output value of the TAG number counter 201 from the value of the alignment determination counter 271 and returns it to the alignment determination counter 271. Further, upon receiving the load buffer usage notification from the load request decomposition unit 103, the alignment determination counter control circuit 210 for the load buffer # 0 has a function of identifying the number of elements information and setting the number of elements in the alignment determination counter 271. Have.

  Reference numeral 211 denotes an alignment timing adjustment counter control circuit for the load buffer # 0, which compares the maximum counter set value output from the counter set value maximum value detection circuit 202 with the value of the alignment timing adjustment counter 272, and sets the counter set. When the output value of the maximum value detection circuit 202 is equal to or greater than the value of the alignment timing adjustment counter 272, the output value of the counter set value maximum value detection circuit 202 is set in the alignment timing adjustment counter 272. In other cases, the alignment timing adjustment counter control circuit 211 sets the value held in the alignment timing adjustment counter 272 to −1 and then holds the value in the alignment timing adjustment counter 272. That is, the alignment timing adjustment counter control circuit 211 has a function of detecting a delay in the arrival of the load data based on the accompanying information and adjusting the transfer start time in consideration of the arrival delay.

  The alignment timing adjustment counter control circuit 211 does not perform any special control at the timing when the load buffer use notification is received from the load request decomposition unit 103, and performs the above operation when the TAG returns from the memory network (return) 106. I do.

  A load instruction information storage register 270 for the load buffer # 0 has a function of holding load instruction information such as an operation register number when a load buffer use notification is received from the load request decomposition unit 103. The load instruction information storage register 270 is reset at the timing of sending the operation register transfer start instruction. Reference numeral 271 denotes an alignment determination counter for the load buffer # 0, in which the remaining load data element values from the main memory 105 are stored. Reference numeral 272 denotes an alignment timing adjustment counter for the load buffer # 0. When the value of the alignment determination counter 271 becomes “0”, the number of cycles until the operation register transfer start instruction is sent (the number of wait cycles) is stored. Is done.

An arithmetic register transfer start condition confirmation circuit 220 for load buffer # 0 outputs an arithmetic register transfer start signal to the arbitration circuit 230 when all of the following requirements (1) to (5) are satisfied.
(1) A valid load instruction is stored in the load instruction information storage register 270. (2) The output of the alignment determination counter 271 is “0”. (3) The output of the alignment timing adjustment counter 272 is “0”. (4) Load data transfer path is not busy (5) Transfer destination operation register is not busy

  Also, 273 shared by the load buffer # 0 and the load buffer # 1 is a busy flag group. The busy flag group includes a busy flag for a load data transfer path from the load buffer 109 to the arithmetic register 110, a write timing control flag for the arithmetic register in consideration of data coherency, and the like. Since data path control and coherency control are general operations, detailed functions and operations are omitted here. Reference numeral 230 denotes an arbitration circuit. When an arithmetic register transfer start signal is sent from both of the arithmetic register transfer start condition confirmation circuits 220 and 221, arbitration such as enabling the preceding load instruction is performed to start arithmetic register transfer. The signal is output to the signal holding register 280. An arithmetic register transfer start signal holding register 280 holds an arithmetic register transfer start signal for one cycle.

  Hereinafter, the load buffer # 1 side also has an element having the same function as each element for the load buffer # 0. That is, 203 is a TAG number counter (for load buffer # 1) and has the same function as the TAG number counter (for load buffer # 0) 201. A counter set value maximum value detection circuit (for load buffer # 1) 204 has a function equivalent to that of the counter set value maximum value detection circuit (for load buffer # 0) 202. A load instruction information storage register (for load buffer # 1) 274 has a function equivalent to that of the load instruction information storage register (for load buffer # 0) 270. Reference numeral 275 denotes an alignment determination counter (for load buffer # 1), which has a function equivalent to that of the alignment determination counter (for load buffer # 0) 271.

  Reference numeral 276 denotes an alignment timing adjustment counter (for load buffer # 1), which has the same function as the alignment timing adjustment counter (for load buffer # 0) 272. An alignment determination counter control circuit (for load buffer # 1) 212 has the same function as the alignment determination counter control circuit (for load buffer # 0) 210. Reference numeral 213 denotes an alignment timing adjustment counter control circuit (for load buffer # 1), which has a function equivalent to that of the alignment timing adjustment counter control circuit (for load buffer # 0) 211. Reference numeral 221 denotes an arithmetic register transfer start condition confirmation circuit (for load buffer # 1), which has the same function as the arithmetic register transfer start condition confirmation circuit (for load buffer # 0) 220.

  Next, a detailed configuration of the load buffer 109 will be described. FIG. 3 shows a state in which 32 pieces of load data e00 to e31 from the memory are stored in the load buffer 109 in response to a load request that has been divided into 32 pieces. The load buffer 109 includes load buffer elements 300 to 303. The load buffer elements 300 to 303 are assigned to the load buffer # 0 and the load buffer # 1, respectively. FIG. 3 shows that the load buffer elements 300 to 303 have a capacity for storing load data for two load instructions at the same time.

  Specifically, the load buffer element 300 is a part of the load buffer for storing the load data input to the port # 0, and the load data e00, e04, e08, e12, e16, e20, e24, e28 are stored. Is done. When an operation register transfer start signal is input from the alignment determination unit 107, the load buffer element 300 reads the load data in the order of e00, e04, e08, e12, e16, e20, e24, e28 and sends them to the operation register 110. To do.

  The load buffer element 301 is a part of the load buffer that stores the load data input to the port # 1, and has the same function as the load buffer element 300. Unlike the load buffer element 300, load data e01, e05, e09, e13, e17, e21, e25, e29 are stored. The reading order is read to the arithmetic register 110 in order from e01.

  The load buffer element 302 is a part of the load buffer that stores the load data input to the port # 2, and has the same function as the load buffer element 300. As load data to be stored, load data e02, e06, e10, e14, e18, e22, e26, e30 are stored. The order of reading is sequentially read from the load data e02. The load buffer element 303 is a part of the load buffer that stores the load data input to the port # 3, and has the same function as the load buffer element 300. Load data to be stored are load data e03, e07, e11, e15, e19, e23, e27, e31, which are read in order from e03.

  FIG. 4 is a diagram illustrating a connection relationship between the load buffer and the arithmetic register in the information processing apparatus according to the present embodiment. The load buffer 109 is composed of load buffer elements 300 to 303 each including four SRAMs (Static Random Access Memory). The TAG and the load data arrive at the load buffer element 300 at the same timing. However, the load buffer element 300 generates an SRAM write address from the TAG, and loads the load data to the SRAM at the timing two cycles after the load data arrives. Write.

  When the arithmetic register transfer start signal arrives from the alignment determination unit 107, the load buffer element 300 generates a read address from the arithmetic register transfer start signal, and loads the read data read three cycles after the arithmetic register transfer start signal arrives. It is sent to the arithmetic register 110. After the operation register transfer start signal arrives, the load buffer 109 increments the read address until the reading of the designated number of elements is completed, and continuously sends the load data to the operation register 110.

  Next, the operation of the information processing apparatus configured as described above will be described. FIG. 5 is a flowchart showing the operation of the information processing apparatus according to the embodiment of the present invention, and FIGS. 7A and 7B are time charts showing the operation of the information processing apparatus according to the embodiment of the present invention. 7A and 7B, the vertical axis represents the sequence identification number, and the horizontal axis represents the number of clocks. In this description, the sequence identification number is indicated as “No.”, and the number of clocks is indicated as “clock”. First, when a load instruction having 32 elements is issued from the instruction issuing unit 101, the used load buffer determining unit 102 determines a load buffer number (for example, # 0) to be used. Further, the used load buffer determination unit 102 generates a load request corresponding to the same 32 elements as the number of elements (S400).

  The load request decomposition unit 103 decomposes the load request generated by the use load buffer determination unit 102 into load requests having 32 elements, and arranges load buffer usage notifications consisting of load buffer number # 0 and load instruction information. The data is sent to the determination unit 107 (S401). Note that the load buffer use notification sent from the load request decomposition unit 103 is No. in the time chart of FIG. 22 clocks 2 are shown.

  When receiving the load buffer use notification from the load request decomposition unit 103, the alignment determination unit 107 sets the load command information in the load command information storage register 270 (S401). Then, the alignment determination unit 107 sets the number of elements “32” in the alignment determination counter 271 (S402). The operation of setting the number of elements “32” in the alignment determination counter 271 for the load buffer # 0 corresponds to No. in the time chart of FIG. 24 clocks 3 are shown.

  Here, the load request for 32 elements generated by the load request decomposition unit 103 is routed to the memory bank designated by the address in the memory network (bound) 104 and sent to one memory bank of the main memory 105. . When the main memory 105 receives the load request, the main memory 105 starts a RAM read sequence. The main memory 105 sends the TAG to the memory network (return) 106 10 cycles before outputting the read load data. Thereafter, the main memory 105 sends the load data to the memory network (return) 106 after 10 cycles of the TAG.

  The memory network (return) 106 identifies port information from the received TAG, performs routing, and sends it to the alignment determination unit 107. The alignment determination unit 107 identifies the TAGs that have arrived, and counts the number of arrival TAGs in the load buffer # 0 and the number of arrival TAGs in the load buffer # 1 in 201 and 203 (S403). For the number of arrival TAGs counted by the alignment determination unit 107, No. 1 in FIG. 20. Specifically, no. At 20, the number of arrival TAGs identified by clock 7 is “4”.

  The alignment determination counter control circuit 210 has a No. stored in the alignment determination counter 271. “28”, which is a value obtained by subtracting the output value “4” of the arrival tag number 201 arriving at the clock 7 from the value “32” of the clock 7 of 24, is set in the alignment determination counter 271 (S404). This operation is shown in No. 24 clock 8 in the time chart of FIG. 7B.

  The counter set value maximum value detection circuit 202 for the load buffer # 0 identifies the element number from the arrival TAG of the load buffer # 0, and obtains the counter set value corresponding to the element number according to the table of FIG. Specifically, in clock 7, No. Element 00 is assigned to port # 0 of No. 4 5 is port 01, element 01 is No. 6 is port 02, element 02 is No. The element 03 arrives at the port # 3 of 7. Referring to FIG. 6, the counter set values corresponding to the elements 00, 01, 02, and 03 are “7”, “7”, “7”, “7”, and “7” in order. Therefore, the output value of the counter set value maximum value detection circuit 202 is set to “7” which is the maximum value. This maximum value is output to the alignment timing adjustment counter control circuit 211 (S405). This operation is performed in accordance with No. 1 in the time chart of FIG. 27 clocks 7 are shown.

  Next, the alignment timing adjustment counter control circuit 211 compares the output value “7” of the counter set value maximum value detection circuit 202 with the stored value “0” of the alignment timing adjustment counter 272 for the load buffer # 0 (S406). ). Here, since the output value “7” of the counter set value maximum value detection circuit 202 is equal to or greater than the stored value “0” of the alignment timing adjustment counter 272 (NO in S406), the alignment timing adjustment counter control circuit 211 The output value “7” of the set value maximum value detection circuit 202 is set in the alignment timing adjustment counter 272 (S408). This operation is performed in accordance with No. 1 in the time chart of FIG. Thirty clocks 8 are shown.

  Next, the arithmetic register transfer start condition confirmation circuit 220 determines whether or not both the alignment timing adjustment counter value and the alignment determination counter value are “0” (S409). Here, since the value of the alignment determination counter is “28” and the value of the alignment timing adjustment counter is “7” in clock 8 in FIG. 7B (NO in S409), the process returns to step S403. In the time chart of FIG. At 32 clock 8, the arithmetic register transfer start condition confirmation circuit 220 does not validate the arithmetic register transfer start signal.

  Returning to step S403, the alignment determining unit 107 identifies the TAGs that have arrived, and counts 201 and 202 the number of arrival TAGs in the load buffer # 0 and the number of arrival TAGs in the load buffer # 1. Here, in FIG. In the clock 8 of 4 to 7, the element 04 arrives at the port # 0, the element 05 arrives at the port # 1, the element 06 arrives at the port # 2, and the element 07 arrives at the port # 3. Therefore, the output value of the TAG number counter 201 which is the number of arrival TAGs is “4”. This operation is performed in accordance with No. of the time chart of FIG. Twenty clocks 8 are shown.

  In step S 404, the alignment determination counter control circuit 210 subtracts the output value “4” of the TAG number counter 201 from the value “28” stored in the alignment determination counter 271 and sets “24” to the alignment determination counter 271. set. This operation is performed in accordance with No. 1 in FIG. 24 clocks 9 are shown.

  In step S405, the counter set value maximum value detection circuit 202 identifies the element number from the arrival TAG of the load buffer # 0, and obtains the counter set value corresponding to the element number according to the table of FIG. Here, in the clock 8, the counter set values corresponding to the element numbers of the respective ports are “6”, “6”, “6”, “6” and all “6” in order. Therefore, the counter set value maximum value detection circuit 202 outputs the maximum value “6” to the alignment timing adjustment counter control circuit 211. This operation is performed in accordance with No. 1 in FIG. 27 clocks 8 are shown.

  In step S406, since the output value “6” of the counter set value maximum value detection circuit 202 is smaller than the stored value “7” of the alignment timing adjustment counter 272 (YES in step S406), the alignment timing adjustment counter control circuit 211 7 "is decremented by 1, and the calculated value" 6 "is set in the alignment timing adjustment counter 272. This operation is performed in accordance with No. 1 in FIG. Thirty clocks 9 are shown.

  In step S409, the arithmetic register transfer start condition confirmation circuit 220 determines whether the outputs of the alignment determination counter 271 and the alignment timing adjustment counter 272 are “0”. Since neither is “0” (NO in step S409), the process returns to step S403. That is, No. 7 in FIG. As indicated by 32 of clock 9, the arithmetic register transfer start condition confirmation circuit 220 does not validate the arithmetic register transfer start signal.

  Thereafter, the processes of steps 403 to S409 are repeated until TAGs of 28 elements out of 32 elements arrive at the alignment determination unit 107. During this time, the value of the alignment determination counter 271 changes in order of “28”, “24”, “20”, “16”, “12”, “8”, “4”. On the other hand, the value of the alignment timing adjustment counter 272 changes to “7”, “6”, “5”, “4”, “3”, “2”, “1”.

  Next, No. in the time chart of FIG. In the 4 to 7 clocks 14, the last 4 elements of 32 elements have arrived. Specifically, element 28 arrives at port # 0, element 29 arrives at port # 1, element 30 arrives at port # 2, and element 31 arrives at port # 3. Therefore, in step S403, the output value of the TAG number counter 201 is “4”. This operation is performed in accordance with No. 7 in FIG. Twenty clocks 14 are shown.

  In step S <b> 404, “0” is stored in the alignment determination counter 271 by subtracting the output value “4” of the TAG number counter 201 from the value “4” held in the alignment determination counter 271. This operation is performed in accordance with No. 1 in FIG. 24 clocks 15 are shown.

  Subsequently, the process proceeds to step S405, and a counter set value corresponding to each element number is calculated with reference to the table of FIG. Here, in FIG. 6, the counter set values corresponding to the respective usage numbers are “0”, “0”, “0”, “0” and all “0” in order. Therefore, the counter set value maximum value detection circuit 202 outputs “0”, which is the maximum value, to the alignment timing adjustment counter control circuit 211. This operation is performed in accordance with No. 1 in FIG. 27 clocks 14 are shown.

  In step S406, the alignment timing adjustment counter control circuit 211 determines that the output value “0” of the counter set value maximum value detection circuit 202 is smaller than the stored value “1” of the alignment timing adjustment counter 272 (YES in step S406). The stored value “1” of the timing adjustment counter 272 is set to −1 and “0” is set to the alignment timing adjustment counter 272 (step S407). This operation is performed in accordance with No. 1 in the time chart of FIG. Thirty clocks 15 are shown.

  In step S409, the operation register transfer start condition confirmation circuit 220 confirms that the outputs of the alignment determination counter 271 and the alignment timing adjustment counter 272 are both “0”. The operation register transfer start condition confirmation circuit 220 confirms that valid load instruction information is stored in the load instruction information storage register 270 and that the busy flag is not set, and the operation register transfer start signal is validated. And

  Here, since there is no valid load instruction information on the load buffer # 1 side, the output of the operation register transfer start condition confirmation circuit 221 for the load buffer # 1 is not validated. The arbitration circuit 230 selects the operation register transfer start signal output from the operation register transfer start condition confirmation circuit 220 for the load buffer # 0 and outputs the operation register transfer start signal to the operation register transfer start signal holding register 280. This operation is performed in accordance with No. 1 in the time chart of FIG. 32 clocks 16 are shown.

  Thereafter, an arithmetic register transfer start signal is sent from the arithmetic register transfer start signal holding register 280 to the load buffer 109 and the arithmetic register 110 (step S410). In the load buffer 109, an operation register transfer start instruction is received by the register and a read address is generated. This operation is performed in accordance with No. 1 in the time chart of FIG. 34 clocks 17.

  Then, the alignment determining unit 107 sends an operation register transfer start instruction to the load buffers 109 and 110, and at the same time, sends a load buffer # 0 release notification to the load request decomposing unit 103 in step S411 to load the load instruction information. The storage register 270 is cleared. This operation is designated as No. in the time chart of FIG. Forty-nine clocks 17 are shown.

  The load buffer 109 increments the read address, sequentially reads the load data, and sends it to the arithmetic register 110. After receiving the operation register transfer start instruction from the alignment determination unit 107, the operation register 110 stores the load data sent from the load buffer 109 in the instructed operation register.

  Thereafter, the load buffer 109 reads all 32 elements, and the arithmetic register 110 stores the received load data for 32 elements. Thereby, a series of operations for one load instruction is completed.

  Next, the operation of the information processing apparatus according to the present embodiment will be described with reference to FIGS. 8A and 8B. 8A and 8B are time charts when the arrival order of TAG (and load data) is disturbed. In addition, since there is no change about a basic operation | movement, it demonstrates paying attention to a characteristic location. 8A and 8B corresponds to the identification number (No.) of the sequence in FIGS. 7A and 7B, and therefore each sequence name is omitted in FIGS. 8A and 8B. .

  7A and 7B show a case where TAGs arrive ideally in order. For example, in FIGS. 4 arrives at the alignment determination unit 107 at clock 7. However, in FIG. Element 00 arrives at 4 clock 15. In FIG. 8A, the element 28 arrives one cycle later (clock 16). Further, in FIG. As shown by the clock 14 in FIG. 4, there is a timing when the TAG does not arrive. Note that in an actual information processing apparatus, due to the influence of memory bank busy, network contention, etc., as shown in FIGS. 8A and 8B, the order of arriving elements is switched or gaps are frequently generated. .

  Next, the operation of the information processing apparatus in the case of FIGS. 8A and 8B will be described according to the flowchart of FIG. Steps S400 to S402 are the same as described above, and will be omitted. In step S403, the number of TAGs that arrive within one clock is counted. For example, in the clock 7 of FIG. 8A, the number of arrivals of the TAG addressed to the load buffer # 0 is “3”. The output value of the TAG number counter 201 at 20 clocks 7 is also “3”.

  In step S <b> 404, “29”, which is a value obtained by subtracting the arrival tag number “3” from the value “32” of the alignment determination counter 271 held in the clock 7, is stored in the alignment determination counter 271. This operation is no. 24 clocks 8 are shown.

  In step S405, the maximum count set value is calculated. Specifically, No. 8 in FIG. Elements 26 and 31 arrive at 4 to 7 in the clock 14. Referring to FIG. 6, the counter set values corresponding to the elements 26 and 31 are “1” and “0”. Therefore, the maximum value “1” is output from the counter set value maximum value detection circuit 202.

  In step S406, it is determined whether or not the value of the alignment timing adjustment counter 272 is larger than the output value of the counter set value maximum value detection circuit 202. Since the value “1” of the alignment timing adjustment counter 272 is the same as the output value “1” of the counter set value maximum value detection circuit 202 at the clock 14 (NO in step S406), the output of the counter set value maximum value detection circuit 202 is output. The value “1” is set in the alignment timing adjustment counter 272 (step S408).

  On the other hand, when focusing on the characteristic clock, no. In the clocks 4 to 7, the element 00 and the element 30 that have arrived late have arrived, and the counter set values corresponding to the elements 00 and 30 are “7” and “0”. Therefore, in step S405, the maximum value “7” is output from the counter set value maximum value detection circuit 202. In step S406, since the value “1” of the alignment timing adjustment counter 272 is smaller than the output value “7” of the counter set value maximum value detection circuit 202 (NO in step S406), the output of the counter set value maximum value detection circuit 202 is output. The value “7” is set in the alignment timing adjustment counter 272.

  Next, in FIG. In the clocks 4 to 7, the elements 28, 29, and 23 have arrived. In step S405, the counter set values corresponding to the elements are “0”, “0”, and “2”, respectively, so the maximum value “2” is output from the counter set value maximum value detection circuit 202. In step S406, the value “7” of the alignment timing adjustment counter 272 is larger than “2” which is the output value of the counter set value maximum value detection circuit 202 (YES in S406). Is set in the alignment timing adjustment counter 272.

  In clock 16, since the last three TAGs have arrived, “0” is set to the value of the alignment determination counter 271 in step S404.

  After that, no TAG arrived. The value of the alignment timing adjustment counter 272 indicated by 30 is decremented by 1 and becomes “0” at the clock 23. In the clock 23, since the values of the alignment determination counter 271 (No. 24) and the alignment timing adjustment counter 272 (No. 30) are both “0”, the arithmetic register transfer start condition confirmation circuit 220 is at this timing. A valid operation register transfer start signal is output. This operation is shown in FIG. 32 clocks 24 are shown.

  7A and 7B, the operation register transfer start signal is sent to the load buffer 109 and the operation register 110 through the arbitration circuit 230 and the operation register transfer start signal holding register 280. Thereby, transfer of load data is started.

  As described above, in the information processing apparatus according to the present embodiment, the two counter controls of the alignment determination counter 271 and the alignment timing adjustment counter 272 are linked to each other, so that the load buffer does not impair data consistency and the fastest. Load data can be stored in the arithmetic register 110 at the timing.

  In addition, the information processing apparatus according to the present embodiment has a configuration in which the TAG is transmitted prior to the load data, so that the data transfer from the load buffer to the arithmetic register can be started at an optimal timing using the counter. . Therefore, it is possible to shorten the load TAT and improve the processing capacity of the apparatus with a small area investment.

  Next, the effect of the present embodiment will be further described using a comparative example of FIGS. 9A and 9B. In this embodiment, the transfer start time is adjusted by comparing the maximum value of the counter set value maximum value detection circuit 202 with the value of the alignment timing adjustment counter 272. On the other hand, in the comparative example of FIGS. 9A and 9B, when the output value of the counter set value maximum value detection circuit 202 is “1” or more, the maximum value of the counter set value maximum value detection circuit 202 and the alignment timing adjustment are adjusted. It is assumed that the alignment timing adjustment counter 272 has logic for setting the output value of the counter set value maximum value detection circuit 202 without comparing with the value of the counter 272. Note that the TAG arrival timings in FIGS. 9A and 9B are the same as those in FIGS. 8A and 9B. Since each sequence number (No.) corresponds to (No.) in FIGS. 7A and 7B, illustration is omitted.

  In this comparative example, no. The value of the alignment timing adjustment counter 272 shown at 30 is set to “2”. Therefore, the counter value is decremented and No. 2 after two cycles. At 30 clocks 19, the value of the alignment timing adjustment counter 272 becomes “0”. With this as a trigger, an operation register transfer start instruction is sent to the load buffer 109 and the operation register 110, and load data transfer is started. 9A and 9B, since the maximum value of the counter set value maximum value detection circuit 202 is not compared with the value of the alignment timing adjustment counter 272, before the load data of the element 00 is stored in the load buffer. It can be seen that reading is started. Therefore, it can be seen that the data consistency is lost in the comparative example.

  On the other hand, in the information processing apparatus according to the present embodiment, the maximum value of the counter set value maximum value detection circuit 202 is compared with the value of the alignment timing adjustment counter 272, and reading is performed in consideration of the maximum delay time of TAG arrival. Can start. Therefore, as shown in FIGS. 8A and 8B, the load data can be read without losing data consistency.

  Further, in the conventional information processing apparatus described in the background art, the timing of the reply TAG is adjusted by the register 701 as shown in FIG. 11A. In other words, it is identified that the reply TAG is valid at the timing corresponding to the reading order. Therefore, when the necessary logic is configured, it is necessary to use a special RAM having 8 or more simultaneous readings or a register, and there is a problem that a necessary area increases.

  On the other hand, the reply TAG timing adjustment function of the information processing apparatus according to the present embodiment only needs to add a function for adjusting the timing for transferring the load data for 9 cycles as described in the function 108. Therefore, it is possible to configure with one write port and one read port (1R1W) general-purpose RAM, and there is an advantage that a required area is small.

  The present invention is not limited to the above description, and various design changes can be implemented by those skilled in the art. For example, the number of memory banks in the main memory 105 and the number of ports in the load buffer 109 do not need to match, and various variations can be taken. In addition, the SRAM configuration of the load buffer 109, the number of load buffers, and the number of output lines to the arithmetic register 110 can be varied. It is also possible to adopt an instruction set configuration in which one load instruction is decomposed into 32 or fewer or 32 or more load requests.

  In addition, it is possible to cope with clock speedup by register insertion. Also, when the number of load requests generated from one load instruction increases, the TAT shortening effect is increased by sending the TAG in advance of the load data because the data transfer cycle from the load buffer to the operation register increases. .

  Specifically, in an instruction set in which 64 load requests are generated from one load instruction, when implemented as an extension of the embodiment, the transfer cycle from the load buffer to the operation register is 16 cycles, which is an increase of 8 cycles from the embodiment. To do. In this case, when the TAG is sent 10 cycles earlier than the load data in the embodiment, the maximum load TAT shortening effect can be obtained if the TAG is sent 18 cycles earlier.

  In this case, the counter set value correspondence table of FIG. 6 can be created by the following procedure. That is, in order to obtain the maximum TAT shortening effect, in the configuration in which the TAG is sent 18 cycles earlier, the element numbers “60”, “61”, “62”, “63” of the last cycle in the load buffer reading order. The counter set value of “0” is set to 0, and the counter set values of element numbers “56”, “57”, “58”, and “59” read immediately before are set to 1. In this way, the correspondence table can be created by increasing the counter set value every time the reading order is advanced. In this case, the count set value of element numbers 0, 1, 2, and 3 is 15.

  The information processing method shown in the flowchart of FIG. 5 can also be implemented as a program, and this program can also be stored in various recording media.

101 Instruction issuing unit 102 Load buffer determining unit 103 Load request decomposing unit 105 Main memory 104, 106 Memory network 107 Alignment determining unit 109 Load buffer 110 Arithmetic register 111 Arithmetic unit 201, 203 TAG counters 202, 204 Maximum counter set value Detection circuits 210 and 212 Alignment determination counter control circuits 211 and 213 Alignment timing adjustment counter control circuits 220 and 221 Arithmetic register transfer start condition confirmation circuit 230 Arbitration circuits 270 and 274 Load instruction information storage registers 271 and 275 Alignment determination counters 272 and 276 Alignment Timing adjustment counter 273 Busy flag group 280 Operation register transfer start signal holding register 300 to 303 Load buffer element

Claims (8)

A load request decomposition unit for generating a plurality of load requests from one load instruction;
A load buffer for storing load data for each of the load requests and transferring the load data to an operation register;
The load request generated by the load request decomposition unit is input, the load data corresponding to the load request is read from the main memory, and the load data generated by the main memory is read out from the load buffer. A memory network for controlling the accompanying information to be transmitted prior to the load data;
Based on the accompanying information sent in advance, the delay of arrival of the load data corresponding to the accompanying information is detected, and based on the arrival delay of the load data, the load buffer to the arithmetic register An information processing apparatus comprising: an alignment determination unit that adjusts a read start time of load data. The load request decomposition unit sends the number of load requests to the alignment determination unit,
The information processing apparatus according to claim 1, wherein the alignment determination unit adjusts the read start time by comparing the number of the load requests with the number of the associated information received.   The information processing apparatus according to claim 1, further comprising an accompanying information timing adjustment unit that adjusts the accompanying information to a timing of the load buffer corresponding to the accompanying information and sends the adjusted information to the load buffer.   The alignment determination unit, based on a delay in arrival of the load data corresponding to the accompanying information that arrived most late among a plurality of the accompanying information, the load data from the load buffer to the operation register The information processing apparatus according to claim 1, wherein the read start time is adjusted.   The alignment determining unit refers to a table in which the order of reading the load data from the load buffer and a delay time for delaying the read start time are referred to, thereby determining the read start time based on the accompanying information. The information processing apparatus according to claim 1, wherein the information processing apparatus is set.   The alignment determination unit sets the delay time of the read start time by referring to the table for each accompanying information that arrives, and updates the read start time according to the largest delay time. 5. The information processing apparatus according to 5. Generate multiple load requests from one load instruction,
Input the generated load request, read the load data for the load request from the main memory,
The accompanying information generated by the main memory indicating the order in which the load data is read from the load buffer to the operation register is sent prior to the load data,
Detecting a delay in arrival of the load data corresponding to the accompanying information based on the accompanying information sent in advance;
An information processing method of adjusting a read start time of the load data from the load buffer to the arithmetic register based on a delay in arrival of the load data.   The information processing method according to claim 7, wherein the read start time is adjusted by comparing the number of the load requests with the number of the associated information received.

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