JP2010256262A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To overcome the problem that a semiconductor integrated circuit device employing a conventional clock gating technology can not deal with a scan test. <P>SOLUTION: The semiconductor integrated circuit device includes: a plurality of flip-flops SFFa-SFFc for maintaining a value of one of a scan data SIN and an input data DIN based on a mode control signal SMC; a data transfer sensing circuit 32 for monitoring values of data input terminals and data output terminals of a plurality of the flip-flops SFFa-SFFc, sensing a data transfer state, and causing a clock control signal CCSa to be an enable state while the data is transferred; a clock gating circuit 16 for supplying a clock signal to a plurality of the flip-flops SFFa-SFFc in response to the clock control signal CCSa; and an operation mode decision circuit for causing the clock control signal CCSa to be the enable state while the mode control signal SMC is in the enable state. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device including a flip-flop that forms a scan chain during a scan test.

  In recent years, in semiconductor integrated circuit devices, reduction of power consumption is desired. In particular, in a semiconductor integrated circuit device mounted on a battery-driven device such as a mobile phone terminal, reduction of power consumption is a major issue in order to extend the usage time of the device. In recent semiconductor integrated circuit devices, CMOS (Complementary Metal Oxide Semiconductor) transistors are often used. In a circuit composed of CMOS transistors, power consumption can be reduced because power consumption occurs only when the logic level in the circuit changes.

  In addition, a circuit using a CMOS transistor often uses a synchronous circuit (for example, a trigger circuit or a flip-flop) that operates in synchronization with a clock signal. Therefore, the power consumption of the semiconductor integrated circuit device can also be reduced by reducing the frequency of the clock signal supplied to the flip-flop or the like. An example of a technique for reducing the power consumption of a semiconductor integrated circuit device by controlling a clock signal is disclosed in Patent Document 1.

  A block diagram of the semiconductor integrated circuit device 100 described in Patent Document 1 is shown in FIG. As shown in FIG. 3, the semiconductor integrated circuit device 100 includes a data input terminal 101, a clock input terminal 102, data output terminals 103 and 104, a D latch circuit 110, combinational circuits 120a to 120c, flip-flops 121a to 121c, and data transfer sensing. A circuit 122 and transfer detectors 123a to 123c are included.

  In the semiconductor integrated circuit device 100, the input data DIN input from the data input terminal 101 is processed by the combinational circuits 120a to 120c, and the processing results are output from the output terminals 103 and 104 as output data DOUT. In the semiconductor integrated circuit device 100, flip-flops 121a to 121c are provided on the output side of the combinational circuits 120a to 120c. That is, in the semiconductor integrated circuit device 100, the flip-flops 121a to 121c perform data transfer between the combinational circuits in synchronization with the clock signal.

  At this time, a clock signal is given to the flip-flops 121a to 121c via the D latch circuit 110. A clock control signal and a clock signal are input to the D latch circuit 110. The D latch circuit 110 supplies a clock signal to the flip-flops 121a to 121c when the clock control signal is in an enabled state (for example, low level), and when the clock control signal is in a disabled state (for example, high level). The supply of the clock signal to the flip-flops 121a to 121c is stopped.

  In the semiconductor integrated circuit device 100, the data transfer sensing circuit 132 generates a clock control signal. The data transfer sensing circuit 132 enables the clock control signal when data transfer is detected by the transfer detectors 123a to 123c. That is, in the semiconductor integrated circuit device 100, the clock signal is supplied to the flip-flops 121a to 121c only when the data transfer state is detected in any of the flip-flops 121a to 121c. Thereby, the semiconductor integrated circuit device 100 reduces the power consumption by reducing the number of clock signals supplied to the flip-flops 121a to 121c. Such a technique for outputting and stopping the clock signal according to other signals is referred to as a clock gating technique.

  An application example of such a clock gating technique is disclosed in Patent Document 2. A logic circuit 200 disclosed in Patent Document 2 is shown in FIG. As shown in FIG. 4, the logic circuit 200 includes a first flip-flop circuit 251, a control circuit 253, a gated clock unit, a gated clock release unit, and a second flip-flop circuit 261. A data signal is input to the first flip-flop circuit 251 in synchronization with the clock. The control circuit 253 generates a clock enable signal EN. The gated clock means includes a flip-flop circuit 254 and an AND circuit 255. The gated clock means gates the clock supplied to the first flip-flop circuit 251 in response to the clock enable signal EN. The gated clock release means has an OR circuit 256. The gated clock release means releases the gate of the clock by the gated clock means in response to the scan test mode signal SCAN. In addition, the logic circuit 200 includes an observation second flip-flop circuit 261 to which the clock enable signal EN output from the control circuit 253 is input in synchronization with the clock, and the second flip-flop circuit 261 is used. Then, the output signal of the control circuit 253 is observed.

JP 2006-229745 A JP 2006-3249 A

  In recent years, in a semiconductor integrated circuit device such as an ASIC (Application Specific Integrated Circuit), a primitive block is prepared in advance by an ASIC vendor, and a user combines the primitive block according to the application. As a result, the ASIC vendor provides the user with an environment that can easily realize a large-scale and complicated circuit.

  In such an ASIC design flow, circuit design is generally performed by RTL (Resister Transfer Level: language description design), and a netlist using primitive blocks is created. Thereafter, a test circuit such as a scan chain is configured for the netlist generated based on the RTL. A design in which such a test circuit is previously incorporated in the circuit is referred to as DFT (Design For Test). The DFT can increase the failure detection rate by a test after manufacturing the semiconductor integrated circuit device.

  However, in the ASIC, various input / output configurations are prepared as scan flip-flops used in the DFT in order to cope with various design configurations. The scan flip-flop is arranged by appropriately replacing the flip-flop of the net list generated based on the RTL. The scan flip-flop is designed to perform an operation defined in the RTL in the normal operation and to configure a shift register during the scan test.

  In such an ASIC, when the clock gating technique described in Patent Document 1 is applied, there is a problem that a clock signal is not supplied to the scan flip-flop during a scan test. This is because there is no data transfer sensing circuit corresponding to the scan flip-flop scan data. A diagram for explaining this problem is shown in FIG. In the example shown in FIG. 5, the transfer detection unit 133 of the data transfer sensing circuit 132 described in Patent Document 1 is applied to the scan flip-flop SFF. As shown in FIG. 5, when the transfer detection unit 133 is connected to the scan flip-flop, the values of the scan data SIN and the output data DOUT cannot be monitored, and data transfer in the scan flip-flop cannot be detected during the scan test.

  Further, in the ASIC, it is difficult to provide a data transfer sensing circuit corresponding to the scan data in each of the scan flip-flops because of circuit size restrictions. FIG. 6 shows a diagram for explaining this problem. As shown in FIG. 6, in order to detect data transfer between the scan data SIN and the output data DOUT in the scan flip-flop SFF, it is necessary to provide a selector SEL in each scan flip-flop. That is, the clock gating technique described in Patent Document 1 has a problem that it cannot be applied to a semiconductor integrated circuit device having a scan flip-flop.

  In addition, when the clock gating technique described in Patent Document 2 is applied to an ASIC, a gated clock unit and a gated clock release unit must be provided in each of the can test flip-flops. However, since the number of circuit elements and the circuit scale are limited in the ASIC, there is a problem that the gated clock means and the gated clock release means cannot be provided for all scan flip-flops. In other words, even the clock gating technique described in Patent Document 2 has a problem that it cannot be applied to a semiconductor integrated circuit device having a scan flip-flop.

  One aspect of a semiconductor integrated circuit device according to the present invention includes: a plurality of flip-flops that hold one of scan data and input data according to a clock signal based on a mode control signal; and the plurality of flip-flops Data that monitors a value of a data input terminal and a data output terminal to detect a data transfer state via any of the plurality of flip-flops, and enables a clock control signal during a period in which the data transfer is performed A transfer sensing circuit; a clock gating circuit for supplying the clock signal to the plurality of flip-flops during a period in which the clock control signal is in an enabled state; and a clock control signal in the period in which the mode control signal is in an enabled state. An operation mode discrimination circuit for enabling.

  According to the semiconductor integrated circuit device of the present invention, the operation mode discriminating circuit determines the enable state and the disable state of the clock control signal input to the clock gating circuit that controls the supply and stop of the clock signal to the plurality of flip-flops. Control. That is, switching between supply and stop of the clock signal to the plurality of flip-flops can be controlled by one operation mode determination circuit (or one mode control signal). As a result, in the semiconductor integrated circuit device according to the present invention, the operation of the scan flip-flop and the effect of reducing the power consumption by the clock gating circuit are realized even in the semiconductor integrated circuit device having a limited circuit scale or the number of circuit elements. can do.

  According to the semiconductor integrated circuit device of the present invention, power consumption can be reduced by the clock gating technique in the semiconductor integrated circuit device having the scan flip-flop.

1 is a block diagram of a semiconductor integrated circuit device according to a first exemplary embodiment; FIG. 3 is a block diagram of a semiconductor integrated circuit device according to a second embodiment; 1 is a block diagram of a semiconductor integrated circuit device described in Patent Document 1. FIG. 10 is a block diagram of a logic circuit described in Patent Document 2. FIG. FIG. 4 is a block diagram illustrating a problem of the semiconductor integrated circuit illustrated in FIG. 3. FIG. 4 is a block diagram illustrating a problem of the semiconductor integrated circuit illustrated in FIG. 3.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a semiconductor integrated circuit device 1 according to the first embodiment. As shown in FIG. 1, the semiconductor integrated circuit device 1 according to the first embodiment includes input terminals 2 to 4 and 8, output terminals 5 to 7, buffer circuits 10 to 15, clock gating circuit 16, clock control signal observation. The circuit 17 includes an operation mode determination circuit 18, a plurality of combinational circuits 30a to 30c, a data transfer sensing circuit 32, and a plurality of flip-flops (for example, scan flip-flops SFFa to SFFc).

  The input terminal 2 is an input terminal for input data DIN to the combinational circuit 30a. The input terminal 3 is an input terminal for the clock signal CLK. The input terminal 4 is an input terminal for scan data SIN used when a scan test is performed on the semiconductor integrated circuit device 1. The input terminal 8 is an input terminal for a mode control signal SMC that specifies an operation mode of the semiconductor integrated circuit device 1. The output terminal 5 is an output terminal for output data output from the combinational circuit 30b. The output data output from the output terminal 5 is output via the scan flip-flop SFFb. The output terminal 6 is an output terminal for output data output from the combinational circuit 30c. Also, scan test result data is output from the output terminal 6 during the scan test. The output data output from the output terminal 6 is output via the scan flip-flop SFFc. The output terminal 7 is an output terminal for a clock observation signal output from the clock control signal observation circuit 17.

  Buffer circuits 10, 11, and 15 are input buffers. The buffer circuit 10 is provided between the input terminal 2 and the combination circuit 30a, and transmits the input data DIN input to the input terminal 2 to the combination circuit 30a. The buffer circuit 11 is provided between the input terminal 3 and the clock gating circuit 16 and transmits the clock signal CLK input to the input terminal 3 to the clock gating circuit 16. The buffer circuit 15 is provided between the input terminal 4 and the scan flip-flop SFFa, and transmits the scan data SIN input to the input terminal 4 to the scan flip-flop SFFa.

  The buffer circuit 14 is a buffer circuit intended for impedance conversion. The buffer circuit 14 distributes the gating clock signal GCLK output from the clock gating circuit 16 to the plurality of scan flip-flops SFFa. The buffer circuits 12 and 13 are output buffers. The buffer circuit 12 is provided between the scan flip-flop SFFb and the output terminal 5, and transmits output data output from the scan flip-flop SFFb to the output terminal 5. The buffer circuit 13 is provided between the scan flip-flop SFFc and the output terminal 7 and transmits data output from the scan flip-flop SFFc to the output terminal 6.

  The clock gating circuit 16 supplies a clock signal (gating clock signal GCLK in the present embodiment) to the flip-flops SFFa to SFFc during a period in which the clock control signal CCSa is in an enabled state. In this embodiment, a D latch circuit is used as the clock gating circuit 16. A clock signal CLK input via the input terminal 3 and the buffer circuit 11 is input to the data input terminal of the D latch circuit, and a clock control signal CCSa is input to the clock input terminal. The clock gating circuit 16 outputs the clock signal CLK as the gating clock signal GCLK when the clock control signal CCSa is in an enabled state (for example, a state in which the clock control signal CCSa is at a low level and instructs the output of the gating clock signal GCLK). . On the other hand, the clock gating circuit 16 fixes the output signal at the low level when the clock control signal CCSa is in the disable state (for example, a state in which the clock control signal CCSa is at a high level and instructs to stop the gating clock signal GCLK). Alternatively, the gating clock signal GCLK is stopped). Details of the clock control signal CCSa will be described later.

  The clock control signal observation circuit 17 observes the value of the clock control signal output from the data transfer sensing circuit 32 and outputs the observation value to the output terminal 7. In the present embodiment, the clock control signal includes the clock control signal CCSa and the advance clock control signal CCSb. In the first embodiment, the advance clock control signal CCSb is observed. In this embodiment, a flip-flop FF is used as the clock control signal observation circuit 17. In the flip-flop FF, the pre-clock control signal CCSb is input to the data input terminal, and the gating clock signal GCLK is input to the clock input terminal. Then, the flip-flop FF takes in the value of the advance clock control signal CCSb in accordance with the rising edge of the gating clock signal GCLK and outputs the value. Note that the clock signal CLK can be input to the flip-flop FF instead of the gating clock signal GCLK.

  The operation mode determination circuit 18 disables the clock control signal CCSa while the mode control signal SMC is enabled. More specifically, when the mode control signal is in an enabled state (for example, a low level indicating a scan test shift mode), the operation mode determination circuit 18 does not depend on the value of the prior clock control signal CCSb. The clock control signal CCSa is enabled (for example, low level).

  In this embodiment, the operation mode determination circuit 18 includes an AND circuit 20 with an inverting input. In the AND circuit 20 with an inverting input, the advance clock control signal CCSb is input to the normal input terminal, and the mode control signal SMC is input to the inverting input terminal. Then, the AND circuit 20 with an inverting input outputs a logical product operation result of the value of the prior clock control signal CCSb and the inverted value of the mode control signal SMC as the clock control signal CCSa.

  The combinational circuits 30a to 30c are asynchronous circuits. In the example shown in FIG. 1, the result of processing the input data DIN by the combinational circuit 30a is transmitted to the combinational circuits 30b and 30c. The combinational circuits 30b and 30c process the data output from the combinational circuit 30a, respectively, and output them as output data to the corresponding output terminals. The combinational circuits 30a to 30b are test target circuits in the scan test.

  The scan flip-flops SFFa to SFFc hold one value of the scan data SIN and the input data DIN according to the gating clock signal GCLK based on the mode control signal SMC. The scan flip-flops SFFa to SFFC have a scan data input terminal (terminal indicated by SIN in the figure), a data input terminal (terminal indicated by D in the figure), a clock input terminal (terminal indicated by C in the figure), and mode control. It has a signal input terminal (terminal indicated by SMC in the figure) and an output terminal (terminal moistened by Q in the figure).

  The scan flip-flops SFFa to SFFc are provided between the combinational circuits 30a to 30c. More specifically, in the scan flip-flop SFFa, the output signal of the combinational circuit 30a is input to the data input terminal, and the output terminal is connected to the input terminal of the combinational circuit 30b and the input terminal of the combinational circuit 30c. In the scan flip-flop SFFb, the output signal of the combinational circuit 30 b is input to the data input terminal, and the output terminal is connected to the output terminal 5 via the buffer circuit 12. In the scan flip-flop SFFc, the output signal of the combinational circuit 30 c is input to the data input terminal, and the output terminal is connected to the output terminal 6 via the buffer circuit 13.

  In the scan flip-flop SFFa, the scan data input terminal is connected to the input terminal 4 via the buffer circuit 15, and the mode control signal SMC is input to the mode control signal input terminal. In the scan flip-flop SFFb, the scan data input terminal is connected to the output terminal of the scan flip-flop SFFb, and the mode control signal SMC is input to the mode control signal input terminal. In the scan flip-flop SFFc, the scan data input terminal is connected to the output terminal of the scan flip-flop SFFb, and the mode control signal SMC is input to the mode control signal input terminal.

  Here, the operation of the scan flip-flops SFFa to SFFc will be described. The scan flip-flops SFFa to SFFc transmit different data according to the value of the mode control signal SMC. First, when the mode control signal SMC is disabled (for example, at a high level), the scan flip-flops SFFa to SFFc are in a scan test capture mode or a normal operation mode. In the capture mode or the normal operation mode, the scan flip-flops SFFa to SFFc hold the data input to the data input terminal according to the gating clock signal GCLK, and output the held value. On the other hand, when the mode control signal SMC is in an enabled state (for example, high level), the scan flip-flops SFFa to SFFc are in the scan test shift mode. In the shift mode, the scan flip-flops SFFa to SFFc hold the data input to the scan data input terminal according to the gating clock signal GCLK, and output the held data. In this shift mode, the scan flip-flops SFFa to SFFc have the same connection form as the shift register.

  Note that scan flip-flops SFFa to SFFc can be in various circuit forms. For example, a circuit configuration having a flip-flop and a selector and switching data to be supplied to the flip-flop by the selector according to the mode control signal SMC, or two flip-flops, and either one of the two according to the mode control signal SMC A circuit configuration for activating the flip-flop is conceivable.

  The data transfer sensing circuit 32 monitors the values of the data input terminals and data output terminals of the scan flip-flops SFFa to SFFc and senses the data transfer state via any one of the scan flip-flops SFFa to SFFc. The clock control signal (for example, the pre-clock control signal CCSb) is enabled during the open period. The data transfer sensing circuit 32 includes a resistor R and monitoring units 33a to 33c. Here, the data transfer sensing circuit 32 according to the present embodiment enables the advance clock control signal CCSb to be in an enabled state if data transfer is performed by any one of the scan flip-flops SFFa to SFFc. Monitoring units 33a to 33c are provided for the flip-flops SFFa to SFFc, respectively. For example, the monitoring unit 33a corresponds to the scan flip-flop SFFa, the monitoring unit 33b corresponds to the scan flip-flop SFFb, and the monitoring unit 33c corresponds to the scan flip-flop SFFc.

  The resistor R has one terminal connected to the power supply terminal VDD and the other terminal connected to the output terminals of the monitoring units 33a to 33c. The monitoring units 33a to 33c include ExOR circuits 41a to 41c and NMOS transistors MNa to MNc. ExOR circuits 41a-41c serve as transfer sensing units that monitor data input terminals and data output terminals of the corresponding scan flip-flops SFFa-SFFc, sense data transfer states, and output data transfer sense signals. Function. The NMOS transistors MNa to MNc function as a clock control signal switching unit that switches a state indicated by a clock control signal (for example, the prior clock control signal CCSb) based on the data transfer detection signal. The NMOS transistors MNa to MNc constitute an open drain circuit having the resistor R as a load. When any of the NMOS transistors MNa to MNc is turned on, a current flows through the resistor R, and the pre-clock control signal CCSb becomes low level.

  Here, the operation of the semiconductor integrated circuit device 1 according to the first embodiment will be described. First, the operation in the normal operation mode in which the mode control signal SMC is disabled (for example, low level) will be described. In the normal operation mode, when a change occurs in any of the output data of the combinational circuits 30a to 30c, a logic level difference occurs between the data input terminal and the data output terminal of the scan flip-flop. Based on the difference in logic level, at least one ExOR circuit 41 of the monitoring units 33a to 33c sets the data transfer detection signal to a high level. The NMOS transistors MNa to MNc to which the high level data transfer detection signal is input are turned on. Thereby, the data transfer sensing circuit 32 sets the prior clock control signal CCSb to the low level. Since the mode control signal SMC is at the low level in the normal operation mode, the operation mode determination circuit 18 outputs the clock control signal CCSa having the same logic level as that of the prior clock control signal CCSb. That is, in the normal operation mode, the prior clock control signal CCSb is used as it is as the clock control signal CCSa.

  Here, the clock gating circuit 16 outputs the gating clock signal GCLK when the clock control signal CCSa is at a low level. Therefore, in the normal operation mode, the gating clock signal GCLK is supplied to the scan flip-flops SFFa to SFFc and the scan flip-flops SFFa to SFFc operate in a state where data transfer is performed through any of the scan flip-flops SFFa to SFFc. It becomes a state to do.

  Next, the operation of the semiconductor integrated circuit device 1 during the scan test will be described. In the scan test, first, scan data is set in the scan flip-flops SFFa to SFFc in the shift mode, and data output from the combinational circuits 30a to 30c is taken into the scan flip-flops SFFa to SFFc based on the scan data set in the scan mode. Then, the mode is switched again to the shift mode, and the test result data taken in the scan flip-flops SFFa to SFFc is read out.

  First, the operation of the semiconductor integrated circuit device 1 in the scan test shift mode will be described. In the shift mode, the mode control signal SMC is enabled (for example, high level). Therefore, the operation mode determination circuit 18 sets the clock control signal CCSa to the low level regardless of the value of the prior clock control signal CCSb. When the clock control signal CCSb is at the low level, the clock gating circuit 16 outputs the gating clock signal GCLK according to the clock signal CLK. That is, in the shift mode, the semiconductor integrated circuit device 1 generates the gating clock signal GCLK and operates the scan flip-flops SFFa to SFFc as shift registers to set scan data.

  Subsequently, an operation in a scan mode in which the mode control signal SMC is disabled (for example, at a low level) during a scan test will be described. The scan mode is an operation required for taking in the test result of the scan test, and the operation is equal to the operation in the normal operation mode. Since the scan test is intended to operate (toggle) the transistors constituting the combinational circuits 30a to 30c, the values of the data input terminals and the data output terminals of the scan flip-flops SFFa to SFFc are often different. Become a logical level. Therefore, in the scan mode, the gating clock signal GCLK is generated and the same operation as the normal operation is performed. Further, since the operation in the scan mode is completed in approximately one clock, the operation equivalent to the normal operation mode can be performed by the gating clock signal GCLK output in the shift mode performed before the scan mode.

  In any of the normal operation mode, the scan mode, and the shift mode, the clock control signal monitoring circuit 17 holds the value of the prior clock control signal CCSb according to the gating clock signal GCLK and outputs it as a clock monitoring signal. . By observing this clock monitoring signal, the state of the prior clock control signal CCSb of the semiconductor integrated circuit device 1 can be known.

  From the above description, in the semiconductor integrated circuit device 1 according to the first embodiment, the operation mode determination circuit 18 controls the value of the clock control signal CCSa in accordance with the mode control signal. Thereby, the semiconductor integrated circuit device 1 can obtain a power saving effect by controlling the clock signal by the clock gating circuit 16 in the normal operation mode. In addition, the semiconductor integrated circuit device 1 can substantially disable the clock signal control by the clock gating circuit 16 during the scan test and prevent malfunction due to the stop of the gating clock signal GCLK during the scan test.

  In the semiconductor integrated circuit device 1, the operation mode determination circuit 18 that controls the value of the clock control signal CCSa is realized by one logic gate (in this embodiment, the AND circuit 20 with an inverting input). Therefore, unlike the conventional semiconductor integrated circuit device, the semiconductor integrated circuit device 1 according to the first embodiment does not need to add many circuit elements in order to prevent malfunction during the scan test. That is, the semiconductor integrated circuit device 1 according to the first embodiment prevents malfunction during a scan test even in a semiconductor integrated circuit device that is limited in the addition of circuit elements such as an ASIC, and employs a clock gating technique. be able to. In other words, the semiconductor integrated circuit device 1 according to the first embodiment can achieve low power consumption and high reliability in a semiconductor integrated circuit device that is limited in the addition of circuit elements such as ASIC.

  In the semiconductor integrated circuit device 1 according to the first embodiment, the circuit operation can be monitored with higher accuracy by monitoring the state of the prior clock control signal CCSb by the clock control signal monitoring circuit 17. As a result, the semiconductor integrated circuit device 1 according to the first embodiment can ensure higher reliability.

Embodiment 2
FIG. 2 shows a block diagram of a semiconductor integrated circuit device 1a according to the second embodiment. In the description of the semiconductor integrated circuit device 1a according to the second embodiment, the same components as those in the semiconductor integrated circuit device 1 according to the first embodiment are denoted by the same reference numerals as those used in the description of the first embodiment. Therefore, the description is omitted.

  As shown in FIG. 2, the semiconductor integrated circuit device 1 a includes an operation mode determination circuit 18 a instead of the operation mode determination circuit 18. The operation mode determination circuit 18a is incorporated in one of the plurality of monitoring units of the data transfer sensing circuit 32. In the description of the second embodiment, the monitoring unit having the operation mode determination circuit 18a is referred to as a monitoring unit 34. In the example shown in FIG. 2, a monitoring unit 34 is provided instead of the monitoring unit 33a. Here, in the semiconductor integrated circuit device 1 a according to the second embodiment, only one of the plurality of monitoring units is set as the monitoring unit 34.

  As shown in FIG. 2, in the semiconductor integrated circuit device 1 a according to the second embodiment, the data transfer sensing circuit 32 directly outputs the clock control signal CCSa input to the clock gating circuit 16.

  The monitoring unit 34 includes an ExOR circuit 41a, an NMOS transistor MNa, and an operation mode determination circuit 18a. The operation mode determination circuit 18a includes an ExOR circuit 21a and a selector 22a. The ExOR circuit 21a monitors the values of the scan data input terminal and the data output terminal of the scan flip-flop SFFa, detects the scan data transfer state via the scan flip-flop SFFa, and outputs a scan data transfer detection signal. Functions as a transfer sensing unit. Here, in the description of the second embodiment, the ExOR circuit 41a is referred to as a first transfer sensing unit. The selector 22a receives the data transfer detection signal output from the ExOR circuit 41a and the scan data transfer detection signal output from the ExOR circuit 21a. The selector 22a selects either the data transfer sensing signal or the scan data transfer sensing signal according to the mode control signal SMC, and uses the selected signal as a switching signal to switch the clock control signal switching unit (for example, the NMOS transistor MNa). ).

  That is, when the mode control signal SMC indicates the normal operation mode or the scan mode (for example, when the mode control signal SMC is at the low level and indicates the disable state), the monitoring unit 34 transfers the input data in the scan flip-flop SFFa. This is detected to turn on the NMOS transistor MNa. In addition, when the mode control signal SMC indicates the shift mode (for example, when the mode control signal SMC is at a high level and indicates an enabled state), the monitoring unit 34 detects that scan data is being transferred in the scan flip-flop SFFa. Then, the NMOS transistor MNa is turned on.

  From the above description, in the semiconductor integrated circuit device 1a according to the second embodiment, one of the plurality of monitoring units is the monitoring unit 34 having the operation mode determination circuit 18a. Thereby, in the normal operation mode, the power consumption by the clock control signal CCSa and the clock gating circuit 16 can be reduced as in the first embodiment. Further, even during the scan test, the clock gating circuit 16 can be invalidated based on the transfer of the scan data via the scan flip-flop SFFa to prevent the malfunction in the scan test shift mode.

  Further, in the semiconductor integrated circuit device 1a according to the second embodiment, one of the plurality of monitoring units is used as the monitoring unit 34 having the operation mode determination circuit 18a, and is added to prevent malfunction during the scan test. The circuit is negligible. That is, also in the semiconductor integrated circuit device 1a according to the second embodiment, low power consumption and high reliability can be realized in a semiconductor integrated circuit device in which addition of circuit elements such as ASIC is limited. Note that at least one monitoring unit 34 may be provided, and a plurality of monitoring units 34 may be provided.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the scan flip-flop may be a flip-flop that can switch which of the two inputs is input / output according to the mode control signal SMC, and the circuit form is not limited. Further, the flip-flop FF used as the clock control signal monitoring circuit 17 may be a circuit that uses a scan flip-flop and constitutes a part of the scan chain.

DESCRIPTION OF SYMBOLS 1, 1a Semiconductor integrated circuit device 2-4, 8 Input terminal 5-7 Output terminal 10-15 Buffer circuit 16 Clock gating circuit 17 Clock control signal observation circuit 18, 18a Operation mode discrimination circuit 20 AND circuit 22a with an inverting input selector 30a-30c Combination circuit 32 Data transfer sensing circuit 33a-33c, 34 Monitoring unit 41a-41c, 21a ExOR circuit R Resistance MNa-MNc NMOS transistor SFFa-SFFc Scan flip-flop CLK Clock signal DIN Input data SIN Scan data SMC Mode control signal GCLK Gating clock signal

Claims (6)

A plurality of flip-flops that hold one of the values of the scan data and the input data according to the clock signal based on the mode control signal;
A value of a data input terminal and a data output terminal of the plurality of flip-flops is monitored to detect a data transfer state via any of the plurality of flip-flops, and a clock control signal is transmitted during the period in which the data transfer is performed A data transfer sensing circuit for enabling
A clock gating circuit for supplying the clock signal to the plurality of flip-flops during a period in which the clock control signal is enabled;
An operation mode determination circuit for enabling the clock control signal during a period in which the mode control signal is enabled;
A semiconductor integrated circuit device.   The semiconductor integrated circuit device according to claim 1, further comprising a clock control signal observation circuit that outputs a value of the clock control signal in accordance with the clock signal.   The operation mode determination circuit receives the clock control signal and the mode control signal output from the data transfer sensing circuit, and the mode control signal is in an enabled state regardless of the output of the data transfer sensing circuit. 3. The semiconductor integrated circuit device according to claim 1, wherein the clock control signal is enabled. The data transfer sensing circuit includes:
A first transfer sensing unit that monitors the data input terminal and the data output terminal of the flip-flop, senses the data transfer state, and outputs a data transfer sensing signal;
A clock control signal switching unit that switches a state indicated by the clock control signal based on the data transfer detection signal;
The operation mode determination circuit includes:
A second transfer sensing unit that monitors a scan data input terminal and the data output terminal of the flip-flop, detects a scan data transfer state via the flip-flop, and outputs a scan data transfer sensing signal;
The data transfer detection signal and the scan data transfer detection signal are input, and the data transfer detection signal or the scan data transfer detection signal is selected according to the mode control signal, and the selected signal is selected. A selector to be provided to the clock control signal switching unit as a switching signal,
The semiconductor integrated circuit device according to claim 1, wherein the clock control signal switching unit switches a state indicated by the clock control signal in accordance with the switching signal.   The semiconductor integrated circuit device according to claim 4, wherein the operation mode determination circuit is provided for at least one of the plurality of flip-flops.   6. The semiconductor integrated circuit device according to claim 1, wherein the plurality of flip-flops are flip-flops corresponding to a scan operation.

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