JP4768968B2 - Semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit having an I / O cell, and in particular at the time of a test, the I / O cell is operated according to a test mode set from the outside, so that the DC electric current of the semiconductor integrated circuit is obtained. The present invention relates to a semiconductor integrated circuit capable of easily measuring a physical characteristic.

  Conventionally, when testing a semiconductor integrated circuit such as an LSI device, the DC electrical characteristics of the integrated circuit can be easily measured by performing an operation for a test mode on an I / O cell provided in the semiconductor integrated circuit. I was doing. For example, in an LCD driving semiconductor integrated circuit device, a voltage level for testing can be output to the LCD driving terminal, and the driving capability and bias state can be easily tested only for the LCD driving terminal. (For example, refer to Patent Document 1). In addition, there has been an integrated semiconductor circuit in which transmission characteristics are tested only at the input terminal of the I / O cell with a control signal that passes through a multiplexer circuit (see, for example, Patent Document 2).

FIG. 3 is a diagram showing a conventional example of a semiconductor integrated circuit having I / O cells.
In the semiconductor integrated circuit 100 of FIG. 3, the control signal input terminals of the I / O cells CELA to CELZ are connected to the internal circuit 101, and input / output of the I / O cells CELA to CELZ is controlled by the control signal from the internal circuit 101. The state was determined. Therefore, in order to measure the DC electrical characteristics of the output high voltage level measurement, output low voltage level measurement, off-leakage current measurement, input leakage current measurement, pull-up current measurement, pull-down current measurement, and standby current measurement in the semiconductor integrated circuit 100. Therefore, it is necessary to perform measurement after fixing the operation states of the I / O cells CELA to CELZ by causing the internal circuit 101 to perform normal operation. In other words, the DC electrical characteristics have to be measured after the internal circuit 101 is operated to some extent according to a predetermined test pattern and each state of the I / O cells CELA to CELZ is fixed.
JP 2003-114654 A JP 2000-206193 A

  However, in a semiconductor integrated circuit having many terminals to be measured, in order to perform output high voltage level measurement, output low voltage level measurement, off-leak current measurement, input leak current measurement, pull-up current measurement, and pull-down current measurement, In many cases, a plurality of terminals cannot be in the same state at the same time. In such a case, the test pattern is operated by limiting the terminals to be measured, and measurement is performed after fixing the state of the I / O cells connected to the terminals that can be measured by the test pattern. For this reason, in order to measure all the terminals to be measured, it is not possible to perform measurement on the measurement item of the DC electrical characteristics unless the test pattern is operated a plurality of times. There is a problem that it takes a lot of time to measure all measurement items. In addition, the state of the I / O cell capable of measuring the DC electrical characteristics to be measured at all the measurement target terminals has been realized by executing a predetermined test pattern. There was a problem that development took a lot of time.

  The present invention has been made to solve the above-described problems. In the test mode, all the control signals for the I / O cells can be controlled so that the DC electric current of the semiconductor integrated circuit can be controlled. An object of the present invention is to obtain a semiconductor integrated circuit capable of easily measuring the physical characteristics.

According to another aspect of the present invention, there is provided a semiconductor integrated circuit having at least one I / O cell for inputting and outputting signals.
An internal circuit unit for controlling the operation of the I / O cell and inputting / outputting signals using the I / O cell;
When a signal indicating that a test operation for measuring a predetermined electrical characteristic is to be performed is input from the outside, the I / O cells of all control signals output from the internal circuit unit to all the I / O cells The input / output to the I / O cell is generated and output for all the I / O cells, and all the control signals for performing the set operation are generated and output instead of the internal circuit unit. An I / O cell control circuit unit for controlling the operation of
With
The I / O cell control circuit unit includes:
A predetermined test operation signal indicating that the test operation is performed and the operation control of the I / O cell are performed according to a signal input from the outside and indicating that the test operation for measuring the predetermined electrical characteristic is performed. A test circuit that generates and outputs all control signals for
When the predetermined test operation signal is output from the test circuit, all the control signals output from the internal circuit unit to all the I / O cells are blocked from being input to the I / O cell, A switching circuit that outputs each control signal output from the test circuit to all the I / O cells;
With
The test circuit includes:
A register in which one bit is assigned to each test mode representing each predetermined electrical characteristic, and a corresponding bit is set according to the test mode representing each predetermined electrical characteristic;
A test control unit for generating and outputting all control signals for controlling the operation of all the I / O cells according to the bits set in the register;
Separately from the test control unit , a logic circuit for generating a test operation signal that is branched and connected to the register and generates and outputs the predetermined test operation signal when one bit is set in the register; ,
Is provided.

Specifically, the test mode of each predetermined electrical characteristic includes output high voltage level measurement, output low voltage level measurement, off-leakage current measurement, input leakage current measurement, pull-up current measurement, pull-down in DC electrical characteristics. a current measurement and a standby current measurement.

  According to the semiconductor integrated circuit of the present invention, it is possible to easily select all DC electrical characteristic test modes that need to be measured by the semiconductor integrated circuit by the register set from the host, and to measure each terminal of the semiconductor integrated circuit. Since it can be performed simultaneously, the time required for the measurement can be greatly shortened.

Next, the present invention will be described in detail based on the embodiments shown in the drawings.
First embodiment.
FIG. 1 is a diagram showing a configuration example of a semiconductor integrated circuit according to the first embodiment of the present invention.
In FIG. 1, a semiconductor integrated circuit 1 includes I / O cells CEL1 to CELn (n is an integer of n> 0) having the same circuit configuration, and the I / O cells CEL1 to CELn according to the operating state during normal operation. And an internal circuit 2 having a predetermined function.

Furthermore, the semiconductor integrated circuit 1 generates and outputs each control signal for controlling the operation of the I / O cells CEL1 to CELn according to the signal from the outside during the test operation for measuring the DC electrical characteristics. And a switching circuit that outputs each control signal from either the internal circuit 2 or the test circuit 3 to the I / O cells CEL1 to CELn according to the control signal TESTEN input from the test circuit 3. 4 is provided. The internal circuit 2 forms an internal circuit unit, and the test circuit 3 and the switching circuit 4 form an I / O cell control circuit unit.
The switching circuit 4 includes multiplexers MA1 to MAn, MB1 to MBn, MC1 to MCn, MD1 to MDn, and ME1 to MEn. Here, since the I / O cells CEL1 to CELn are configured by the same circuit, an arbitrary I / O cell CELk (k = 1 to n) will be described as an example. Multiplexers MAk, MBk, MCk, MDk, and MEk are provided corresponding to the I / O cell CELk.

  The I / O cell CELk includes a PMOS transistor QPk, an NMOS transistor QNk, an AND circuit ANk, and a buffer BUk. The PMOS transistor QPk and the NMOS transistor QNk are connected in series between the power supply voltage Vdd and the ground voltage. A connection portion between the PMOS transistor QPk and the NMOS transistor QNk is connected to the pad Pk. The gate of the PMOS transistor QPk is connected to the output terminal of the multiplexer MAk, and the gate of the NMOS transistor QNk is connected to the output terminal of the multiplexer MEk.

In the buffer BUk, the input end is connected to the output end of the multiplexer MCk, the output end is connected to the pad Pk, and the control signal input end is connected to the output end of the multiplexer MBk.
Next, in the AND circuit ANk, the output signal is input to the internal circuit 2 as the input signal INk, one input terminal is connected to the pad Pk, and the other input terminal is connected to the output terminal of the multiplexer MDk.

On the other hand, in the multiplexer MAk, the control signal PUENk # from the internal circuit 2 is input to one input terminal, the control signal PUCNT # from the test circuit 3 is input to the other input terminal, and the control signal input terminal The control signal TESTEN from the test circuit 3 is input to the select terminal S that forms The control signal TESTEN is a test operation signal.
In the multiplexer MBk, the control signal OEk # from the internal circuit 2 is input to one input terminal, the control signal OECNT # from the test circuit 3 is input to the other input terminal, and the select terminal S has A control signal TESTEN from the test circuit 3 is input.

In the multiplexer MCk, the output signal OUTk from the internal circuit 2 is input to one input terminal, the signal ACNT from the test circuit 3 is input to the other input terminal, and the test circuit 3 is input to the select terminal S. The control signal TESTEN from is input.
In the multiplexer MDk, the control signal ENk from the internal circuit 2 is input to one input terminal, the control signal ENCNT from the test circuit 3 is input to the other input terminal, and the test circuit is connected to the select terminal S. The control signal TESTEN from 3 is input.
In the multiplexer MEk, the control signal PDENk from the internal circuit 2 is input to one input terminal, the control signal PDCNT from the test circuit 3 is input to the other input terminal, and the test circuit is connected to the select terminal S. The control signal TESTEN from 3 is input.

The operation of the I / O cell CELk in such a configuration will be described.
First, a signal input to the gate of the PMOS transistor QPk is a pull-up enable signal PUEN #, and a signal input to the gate of the NMOS transistor QNk is a pull-down enable signal PDEN. In addition, a signal input to the control signal input terminal of the buffer BUk is an output enable signal OE #, and a signal input to one input terminal of the AND circuit ANk is an enable signal EN. Further, a signal input to the input terminal of the buffer BUk is an A signal, and a signal output from the AND circuit ANk is a Y signal.

  When the pull-up enable signal PUEN # becomes a low level, the PMOS transistor QPk is turned on to form a pull-up resistor, and when the pull-up enable signal PUEN # becomes a high level, the PMOS transistor QPk is turned off. When the pull-down enable signal PDEN # becomes high level, the NMOS transistor QNk is turned on to form a pull-down resistor, and when the pull-down enable signal PDEN # becomes low level, the NMOS transistor QNk is turned off.

  On the other hand, when the output enable signal OE # becomes low level, the buffer BUk is turned on, the input A signal is converted into a binary signal and output to the pad Pk, and when the output enable signal OE # becomes high level. The buffer BUk is turned off and the output terminal is in a high impedance state. When the enable signal EN becomes high level, the AND circuit ANk converts the signal input to the pad Pk into a binary signal as a Y signal, forms the input signal INk of the internal circuit 2, and when the enable signal EN becomes low level. The Y signal is set to the low level regardless of the signal input to the pad Pk.

  Here, the test circuit 3 sets the control signal TESTEN to a low level during normal operation. Therefore, the multiplexers MAk, MBk, MCk, MDk, and MEk output the signals input from the internal circuit 2 to the I / O cell CELk, respectively. That is, in the I / O cell CELk, the control signal PUENk # is used as the pull-up enable signal PUEN # at the gate of the PMOS transistor QPk, and the control signal OEk # is used as the output enable signal OE # at the control signal input terminal of the buffer BUk. Each is entered. Further, in the I / O cell CELk, the output signal OUTk is the A signal at the input terminal of the buffer BUk, the control signal ENk is the enable signal EN at one input terminal of the AND circuit ANk, and the gate of the NMOS transistor QNk A control signal PDENk is input as a pull-down enable signal PDEN.

  Next, the test circuit 3 sets the control signal TESTEN to a high level during a test operation for measuring the DC electrical characteristics. Therefore, the multiplexers MAk, MBk, MCk, MDk, and MEk output the signals input from the test circuit 3 to the I / O cell CELk, respectively. That is, in the I / O cell CELk, the control signal PUCNT # is used as the pull-up enable signal PUEN # at the gate of the PMOS transistor QPk, and the control signal OECNT # is used as the output enable signal OE # at the control signal input terminal of the buffer BUk. Each is entered. Further, in the I / O cell CELk, the output signal ACNT is an A signal at the input terminal of the buffer BUk, the control signal ENCNT is an enable signal EN at one input terminal of the AND circuit ANk, and the gate of the NMOS transistor QNk is A control signal PDCNT is input as a pull-down enable signal PDEN.

Here, FIG. 2 is a diagram showing an example of the internal configuration of the test circuit 3, and the operation of the test circuit 3 will be described with reference to FIG.
In FIG. 2, a test circuit 3 generates and outputs control signals PUCNT #, OECNT #, ACNT, ENCNT, and PDCNT from a 7-bit register 11 and 7-bit data set in the register 11, respectively. The test control unit 12 executes the program and the 7-input OR circuit 13. The OR circuit 13 forms a test operation signal generation circuit unit. Here, bit data of TVOH, TVOL, TIOZ, TIIL, TPU, TPD, and TICCS is set in the register 11 by a data set from a host bus (not shown) or the like. Each bit data TVOH, TVOL, TIOZ, TIIL, TPU, TPD, and TICCS are input to corresponding input terminals of the test control unit 12 and the OR circuit 13, respectively.

  When bit data TVOH is set, output high voltage level measurement of DC electrical characteristics is performed, and when bit data TVOL is set, output Low voltage level measurement of DC electrical characteristics is performed. It shows that off leak current measurement of DC electrical characteristics is performed when set, and that input leak current measurement of DC electrical characteristics is performed when bit data TIIL is set. The bit data TICCS is set to perform pull-up current measurement of DC electrical characteristics when the bit data TPU is set, and to perform pull-down current measurement of DC electrical characteristics when the bit data TPD is set. When this is done, it is shown that standby current measurement of DC electrical characteristics is performed.

When normal operation is performed, each bit data TVOH, TVOL, TIOZ, TIIL, TPU, TPD, and TICCS are reset to “0”. Further, when performing a test operation, only one of each bit data TVOH, TVOL, TIZ, TIIL, TPU, TPD, TICCS is set.
The test control unit 12 executes, for example, the following program shown in Verilog language description, and from each bit data TVOH, TVOL, TIOZ, TIIL, TPU, TPD, TICCS inputted from the register 11, each control signal PUCNT #, OECNT #, ACNT, ENCNT, and PDCNT are generated and output, respectively.

Always @ (TVOH or TVOL or TIOZ or TIIL or TPU or TPD or TICCS) begin
Casex ({TVOH, TVOL, TIOZ, TIIL, TPU, TPD, TICCS})
7'b1000000: begin
ACNT = 1'b1;
ENCNT = 1'b0;
OECNT = 1'b0;
PUCNT = 1'b0;
PDCNT = 1'b1;
End
7'b0100000: begin
ACNT = 1'b0;
ENCNT = 1'b0;
OECNT = 1'b0;
PUCNT = 1'b0;
PDCNT = 1'b1;
End
7'b0010000: begin
ACNT = 1'b0;
ENCNT = 1'b1;
OECNT = 1'b1;
PUCNT = 1'b0;
PDCNT = 1'b1;
End
7'b0001000: begin
ACNT = 1'b0;
ENCNT = 1'b1;
OECNT = 1'b1;
PUCNT = 1'b0;
PDCNT = 1'b1;
End
7'b0000100: begin
ACNT = 1'b0;
ENCNT = 1'b1;
OECNT = 1'b1;
PUCNT = 1'b1;
PDCNT = 1'b1;
End
7'b0000010: begin
ACNT = 1'b0;
ENCNT = 1'b1;
OECNT = 1'b1;
PUCNT = 1'b0;
PDCNT = 1'b0;
End
Default: begin
ACNT = 1'b0;
ENCNT = 1'b1;
OECNT = 1'b1;
PUCNT = 1'b0;
PDCNT = 1'b1;
End
Endcase
End

  That is, when measuring the output high voltage level of the DC electrical characteristics, if only the bit TVOH of the register 11 is set, the control signal TESTEN becomes high level, and the control signals ACNT and PDCNT become high level, The control signals PUCNT #, OECNT #, and ENCNT become low level. Therefore, the PMOS transistors QP1 to QPn and the NMOS transistors QN1 to QNn are turned off and the buffers BU1 to BUn are enabled, and high level signals are output from the buffers BU1 to BUn to the corresponding pads P1 to Pn, respectively. . Therefore, the output high voltage level of all the I / O cells CEL1 to CELn can be measured simultaneously.

  When measuring the output low voltage level of the DC electrical characteristic, if only the bit TVOL of the register 11 is set, the control signal TESTEN becomes high level, the control signal PDCNT becomes high level, and the control signal PUCNT #, OECNT #, ACNT, and ENCNT are at low levels. Therefore, the PMOS transistors QP1 to QPn and the NMOS transistors QN1 to QNn are turned off and the buffers BU1 to BUn are enabled, and low level signals are output from the buffers BU1 to BUn to the corresponding pads P1 to Pn. . Therefore, the output low voltage level of all the I / O cells CEL1 to CELn can be measured simultaneously.

  Also, when measuring the off-leakage current of DC electrical characteristics, if only the bit TIOZ of the register 11 is set, the control signal TESTEN goes high and the control signals OECNT #, ENCNT, PDCNT go high. , The control signals PUCNT # and ACNT become low level. Accordingly, the PMOS transistors QP1 to QPn and the NMOS transistors QN1 to QNn are turned off and the buffers BU1 to BUn are disabled, and the output terminals of the buffers BU1 to BUn are set to a high impedance state. For this reason, the off-leakage currents of all the I / O cells CEL1 to CELn can be measured simultaneously.

  Further, when measuring the input leakage current of DC electrical characteristics, if only the bit TIIL of the register 11 is set, the control signal TESTEN becomes high level and the control signals OECNT #, ENCNT, PDCNT become high level, respectively. Thus, the control signals PUCNT # and ACNT are each set to a low level. Accordingly, the PMOS transistors QP1 to QPn and the NMOS transistors QN1 to QNn are turned on and the buffers BU1 to BUn are disabled, and the output terminals of the buffers BU1 to BUn are set to a high impedance state. For this reason, the input leakage current of all the I / O cells CEL1 to CELn can be measured simultaneously.

  When measuring the pull-up current of the DC electrical characteristics, if only the bit TPU of the register 11 is set, the control signal TESTEN becomes high level and the control signals PUCNT #, OECNT #, ENCNT, and PDCNT are respectively set. It becomes high level, and the control signal ACNT becomes low level. Accordingly, the PMOS transistors QP1 to QPn are turned on, the NMOS transistors QN1 to QNn are turned off, the buffers BU1 to BUn are respectively disabled, and the output terminals of the buffers BU1 to BUn are respectively in a high impedance state. . For this reason, the pull-up currents of all the I / O cells CEL1 to CELn can be measured simultaneously.

  Further, when measuring the pull-down current of the DC electrical characteristics, if only the bit TPD of the register 11 is set, the control signal TESTEN becomes high level and the control signals OECNT # and ENCNT become high level, respectively. The signals PUCNT #, ACNT, and PDCNT are each at a low level. Therefore, the PMOS transistors QP1 to QPn are turned off, the NMOS transistors QN1 to QNn are turned on, the buffers BU1 to BUn are disabled, and the output terminals of the buffers BU1 to BUn are set to a high impedance state. . For this reason, the pull-down currents of all the I / O cells CEL1 to CELn can be measured simultaneously.

When measuring the standby current of DC electrical characteristics, if only the bit TICCS of the register 11 is set, the control signal TESTEN becomes high level and the control signals OECNT #, ENCNT, PDCNT become high level, respectively. , The control signals PUCNT # and ACNT become low level. Therefore, the PMOS transistors QP1 to QPn and the NMOS transistors QN1 to QNn are turned off and the buffers BU1 to BUn are disabled, and the output terminals of the buffers BU1 to BUn are set to a high impedance state. Therefore, the standby currents of all the I / O cells CEL1 to CELn can be measured simultaneously. In this way, the DC electrical characteristics can be easily measured by setting one bit of the register 11.
In the above description, # added after the code indicating the signal name indicates low active.

  As described above, in the semiconductor integrated circuit according to the first embodiment, during the normal operation, the test circuit 3 sets the control signal TESTEN to the low level, so that the multiplexers MAk, MBk, MCk, MDk, MEk During the test operation in which each signal input from the circuit 2 is output to the I / O cell CELk and the DC electrical characteristic is measured, the test circuit 3 sets the control signal TESTEN to the high level so that the multiplexer MAk, MBk, MCk, MDk, and MEk output the control signals input from the test circuit 3 to the I / O cell CELk, respectively. Thus, in the test mode, all control signals for the I / O cell can be controlled, and the DC electrical characteristics of the semiconductor integrated circuit can be easily measured.

1 is a diagram illustrating a configuration example of a semiconductor integrated circuit according to a first embodiment of the present invention. FIG. 2 is a diagram illustrating an internal configuration example of a test circuit 3 in FIG. 1. It is the figure which showed the prior art example of the semiconductor integrated circuit which has an I / O cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit 2 Internal circuit 3 Test circuit 4 Switching circuit 11 Register 12 Test control part 13 OR circuit CEL1-CELn I / O cell MA1-MAn, MB1-MBn, MC1-MCn, MD1-MDn, ME1-MEn Multiplexer QP1 QPn PMOS transistor QN1 to QNn NMOS transistor BU1 to BUn buffer AN1 to ANn AND circuit P1 to Pn pad

Claims (2)

In a semiconductor integrated circuit having at least one I / O cell for inputting and outputting signals,
An internal circuit unit for controlling the operation of the I / O cell and inputting / outputting signals using the I / O cell;
When a signal indicating that a test operation for measuring a predetermined electrical characteristic is to be performed is input from the outside, the I / O cells of all control signals output from the internal circuit unit to all the I / O cells The input / output to the I / O cell is generated and output for all the I / O cells, and all the control signals for performing the set operation are generated and output instead of the internal circuit unit. An I / O cell control circuit unit for controlling the operation of
With
The I / O cell control circuit unit is
A predetermined test operation signal indicating that the test operation is performed and the operation control of the I / O cell are performed according to a signal input from the outside and indicating that the test operation for measuring the predetermined electrical characteristic is performed. A test circuit that generates and outputs all control signals for
When the predetermined test operation signal is output from the test circuit, all the control signals output from the internal circuit unit to all the I / O cells are blocked from being input to the I / O cell, A switching circuit that outputs each control signal output from the test circuit to all the I / O cells;
With
The test circuit includes:
A register in which one bit is assigned to each test mode representing each predetermined electrical characteristic, and a corresponding bit is set according to the test mode representing each predetermined electrical characteristic;
A test control unit for generating and outputting all control signals for controlling the operation of all the I / O cells according to the bits set in the register;
Separately from the test control unit , a logic circuit for generating a test operation signal that is branched and connected to the register and generates and outputs the predetermined test operation signal when one bit is set in the register; ,
A semiconductor integrated circuit comprising: The test modes of the respective predetermined electrical characteristics include output high voltage level measurement, output low voltage level measurement, off-leakage current measurement, input leakage current measurement, pull-up current measurement, pull-down current measurement, and standby current in DC electrical characteristics. 2. The semiconductor integrated circuit according to claim 1, wherein the measurement is measurement .

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