JP2010246949A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To ensure resetting of a CPU when a power source is turned on. <P>SOLUTION: A clock signal is divided by counter ICs 256, 257. An output signal of the counter IC 256 rises as an H active signal with a delay of a predetermined time (T1) from the change of a system reset signal, and the output signal to an NOR gate IC 261 changes to L. A flip-flop IC 267, when receiving the output signal of the counter IC 256, outputs H and L alternately to an Enable terminal of the counter IC 260 every clock from an oscillating section 210, and gives a pulse rising with a delay of a predetermined time (T2) and falling after a predetermined time (T3), and allows the NOR gate IC 261 to output the pulse. The NOR gate IC 261 takes the negation of OR of an output signal of a Schmitt trigger inverter IC 259 and an output signal from a Q2B terminal of the counter IC 260 and inputs it as a reset signal to the CPU. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a gaming machine whose game is controlled by a control circuit including a CPU.

In general, gaming machines such as pachinko machines adopt computer control, and signal generation and input / output control necessary for computer control are performed from when the gaming machine is turned on until normal gaming. For this reason, the selection of the CPU and the waveform of the generated signal depend on various factors such as the desired performance of the gaming machine for which the authorization system is adopted, game characteristics (game contents and preferences), and production / running costs. Decided by taking into account. Further, in the control of the gaming machine, reset control is performed in consideration of fairness between the player and the game hall and a severe operating environment (dust, electrical noise, etc.) of the game hall. This reset control mainly includes a reset control at the time of power-on of the gaming machine (hereinafter referred to as a power-on reset) and a reset control (user reset) that is regularly performed while the gaming machine is in operation. . The former power-on reset is a control that is performed in preparation for the start of business, such as before the daily opening of the amusement hall, and in preparation for steady control as the main power of the gaming machine is turned on before entering the normal game control. The control data for the entire gaming machine is initialized. On the other hand, the latter user reset is a control that is repeatedly performed in a short cycle (for example, every 2 ms) in the steady control, and the main control of the game is returned to the initial state every time leaving necessary data generated according to the progress of the game. Returned. By this user reset, even if the gaming machine runs away in a severe operating environment in the game hall, the initial state of the control is restored in a short period of time, and it is prevented that the game is adversely affected by the disturbance. In addition, it is necessary to design the input / output of signals to the CPU at an appropriate time in consideration of the internal operation of the CPU. That is, for example, even if a signal is input in a state where the CPU is not ready for signal reading, the CPU cannot appropriately use the input signal. As a CPU that prevents such a problem, there is a CPU that outputs a readable signal when it can be read, and outputs a writable signal when it can be written, so as to match the timing of signal input / output with a peripheral circuit.

By the way, a system reset (also referred to as a power-on reset) signal that initializes the CPU when the power is turned on, as shown in FIG. 14 (2), indicates the potential state of the power supply to the gaming machine ((1)). ) Is maintained at the L level (active) for a certain time T0 from when it rises until it becomes stable, and then becomes the H level (inactive). When this system reset signal is at the L level after power-on, the CPU is initialized. However, in practice, the relationship between the power signal (1) and the power-on reset signal (2) is not reflected in the operation state of the CPU as designed, and some control circuits are in the middle of rising of the power signal. In some cases, the potential showed unexpected behavior. Such defects are rarely seen in the development stage and do not occur in many of the millions of machines that are produced annually. In a gaming machine that is given, it is necessary to improve the fairness of the game and to stably exhibit the desired performance so as not to harm public order and morals. Therefore, occurrence of a phenomenon different from the idea of the gaming machine designer must be prevented as much as possible, and it is important to take some measures for operating the control circuit according to the design idea. As for the signal input / output of the CPU, simply outputting a writable signal when the signal is output from the CPU and outputting a readable signal at the signal input timing does not reflect the characteristics of the surrounding electronic components. Operation may become unstable.

An object of the present invention is to provide a gaming machine capable of further stabilizing a control operation.

In order to solve the above-described problems, in a gaming machine including a control device that performs control related to a game of the present invention, the control device includes an initialization signal generation unit that generates an initialization signal, and an initialization signal based on the initialization signal. The initialization signal generation unit gives a plurality of variations to the initialization signal.

When turning on a gaming machine, if an initialization signal having a waveform having a plurality of variations is given to the electronic component, the electronic component can be compared with a case where an initialization signal having a waveform having only a single variation is given. Initialization can be performed more reliably and stably, and as a result, the operation of the gaming machine can be stabilized.

A plurality of variations of the initialization signal are defined as first and second variations, and the first and second variations are different from the rising or falling of the signal. You can also. This makes it possible to initialize a portion of the electronic circuit that is initialized at the rising edge or falling edge of the initialization signal.

Further, with respect to the initialization signal, after the power is turned on, the electronic circuit unit is shown in a form that can be initialized (hereinafter also referred to as reset active) prior to showing the first change form, and then the electronic circuit part according to the first change form. It is also possible to use a waveform indicating an uninitialized form (hereinafter also referred to as reset non-active). In this way, the reset circuit becomes active at the same time as the power is turned on, so that the electronic circuit does not operate and malfunction at that time can be prevented.

If the initialization signal is generated based on a reference signal that is generated or changed as the power is turned on, the initialization signal can be input at an appropriate timing.

Further, if the initialization signal generation unit includes a power-on initialization signal generation unit and a steady-state initialization signal generation unit, the resetting of the gaming machine that is periodically required as well as when the power is turned on The circuit that performs the operation can also be used, and it is possible to realize circuit-saving parts of the circuit elements, space-saving of the circuit board, and the like. Similarly, the power-on initialization signal generator includes a general-purpose initialization signal generator that can initialize each circuit, and an electronic component initialization signal generator that initializes a specific electronic component. By doing so, it is possible to realize further parts saving and space saving. In addition, if a specific electronic component is a CPU, a periodic initialization operation required for stable operation of the gaming machine and prevention of fraud can be performed using an initialization circuit at power-on. .

On the other hand, the initialization signal generation unit makes the timings of applying the plurality of change forms different and eliminates the remaining defective elements remaining in the initialization related to the change form of the previous stage from the input of the change form of the subsequent stage, thereby initializing the electronic circuit unit. It can also be configured to compensate for the conversion. In other words, when the power is turned on again with the electric charge remaining in the internal circuit of the gaming machine, the malfunction caused by the residual electric charge that is the residual defective element is eliminated by the input of the subsequent change form. It is possible to do.

Regarding the reset input signal required for initialization of the CPU, which is determined for each CPU, the reset active level of the signal, the time during which the reset active level should be input, and the signal change form, that is, the slope of the waveform (edge) However, in the present invention, the conditions necessary for these various reset operations have already been taken into account, and a further stable operation is intended.

The front view of the game machine of one Example of this invention. The back view of a gaming machine. The block diagram of a main control board. Block diagram inside the CPU used for the main control board The circuit diagram which shows the connection state of a reset circuit part and CPU. The circuit diagram which shows the connection state of an I / O decoding circuit part and CPU. The circuit diagram which shows the connection state of a 1st input circuit part and CPU. The circuit diagram which shows a command output circuit part. The circuit diagram which shows a solenoid drive circuit part. The circuit diagram which shows a LED drive and information output circuit part. The circuit diagram which shows the 2nd external input circuit part. The circuit diagram which shows an output port part. The circuit diagram which shows a CPU reset circuit part. Timing chart showing main power supply signal (1), system reset signal (2), and CPU initialization reset signal (3) The timing chart which shows CPU initialization reset signal (5) and the various signals (1)-(4) used for the production | generation.

Hereinafter, embodiments of the present invention will be described with reference to examples shown in the drawings, taking a first-class gaming machine as an example.

Hereinafter, embodiments of the present invention will be described with reference to the examples shown in the drawings, taking a first-class gaming machine as an example. FIG. 1 is a front view of a gaming machine 1 according to the present invention. The front portion of the gaming machine 1 includes a main body frame 2, a middle frame 3, a front frame 4, an upper plate portion 5, a lower plate portion 6, and a locking device 7. The main body frame 2 is formed by assembling and fixing a wooden plate-like body into a substantially rectangular frame shape. The middle frame 3 is almost entirely made of plastic, and has a frame part (not shown) and a lower plate part (not shown) and is fitted and attached to the inner peripheral side of the main body frame 2. A locking device 7 is provided at the center of the right end. The locking device 7 has a substantially rectangular shape with a keyhole when viewed from the front, and is used for locking when the front frame 4 is closed.
The front frame 4 is entirely made of plastic, and in order to visually recognize the game board 10 from the front, the upper side has a substantially arc shape corresponding to the shape of the game area formed on the game board 10, and the whole is substantially a bullet shape. Has an opening 4a. And on the back surface, a substantially rectangular glass frame (not shown) fitted with a glass plate according to the opening 4a is mounted. The front frame 4 occupies 2/3 the size of the entire front surface of the gaming machine 1 and is pivotally attached to the left end of the middle frame 3 so as to be openable and closable.
The game board 10 is a substantially rectangular wooden plate-like body, and is held by the middle frame 3. The back mechanism board 102 (see FIG. 2), which will be described later, covers the back side thereof, and the outer rail and the inner rail provided on the surface. As a result, a substantially circular gaming area is formed, and gaming devices such as a special symbol display device and a variable winning device are arranged in the gaming region.

Here, the frame body portion is formed in a substantially rectangular frame shape from the upper end to the lower side to approximately 2/3 of the entire middle frame 3, and the upper end portion has a frame decoration along the arc portion of the upper end portion of the opening 4 a. Lamps 4b, 4c, 4e, and 4h are provided, and a frame decoration lamp substrate 4g is installed correspondingly. In the middle frame 3 above the left side, a prize ball display LED 4i and a prize ball display LED substrate 4d are provided, and in the upper right side, a stop display LED 4j and a stop display LED substrate 4f are provided.

Further, the lower plate portion occupies about 1/3 of the entire middle frame 3 from the lower end to the upper side, and on the left side, the effect corresponding to the gaming state to correspond to the speaker surface 5a formed on the upper plate portion 5. A speaker (not shown) for generating sound and other sound information is arranged, and on the substantially right side, a game ball stored in the upper plate part 5 with respect to a launcher unit 8 (see FIG. 2) that launches the game ball. A supply device or the like (not shown) is provided. Further, a lower plate part 6 is provided below.

The lower tray portion 6 includes an ashtray, a ball removal lever, and the like, and has a discharge port 6a for discharging game balls from the inside of the gaming machine 1, and operates the launcher unit 8 (see FIG. 2) at the right end. A firing handle 9 is provided. The launch handle 9 is equipped with a touch switch 9a for detecting that the player is touching, and in the vicinity thereof, a launch stop switch 9b for instructing the stop of the launch is arranged.

The upper plate part 5 is attached to the left end of the middle frame 3 below the front frame 4 and is formed to be openable and closable. On the outer edge 5b of the dish, a ball removal button, a game ball rental / return button, and the like are arranged. Further, a discharge port 5c for discharging game balls from the inside of the gaming machine 1 is opened. A speaker surface 5a having a plurality of long holes is formed at the left end, and a volume switch board (not shown) is provided on the back surface. A prepaid card unit 13 is mounted on the left end side of the gaming machine 1. The game board 10 is detachably attached to the surface side of the middle frame 3.

Next, the back surface structure of the gaming machine 1 of this embodiment will be described with reference to FIG. The front frame 4 is in the middle frame 3 and is supported by a pair of hinges 101 provided at the upper and lower ends of the front frame 4 so as to be opened and closed. The mechanism board 102 is supported by the pair of hinges 103 provided in the middle frame 3 at the upper and lower ends of the mechanism board 102 so as to be opened and closed. A prize ball tank 105 provided with a tank ball cut detection switch 104 at the bottom of the tank and a tank rail 106 connected to the prize ball tank 105 are attached to the left side as viewed from the position of the hinge 101 on the upper end side. ing. Further, a ball removal lever 107 is provided on the right side of the tank rail 106, a refill ball break detection switch 108 is provided on the downstream side, and a prize ball payout device 109 is provided on the downstream side. Yes.

Subsequently, a game ball distribution unit 110 is provided on the downstream side of the prize ball payout device 109. Below the tank rail 106 is a back case 111 with a lid that houses a display control unit (not shown), and below this back case 111 is a main control board case 112 that houses a main control board 100 to be described later. Are detachably provided. On the left side of the main control board case 112, a launcher control board case 113 storing a launcher control board (not shown), a touch sensitivity adjustment knob 114, a ball jump strength adjustment knob 115, and a launch control collective relay board 116 are provided. ing. In the lower left part of the mechanism panel 102, the above-mentioned launching device unit 8 is provided. Similarly, in the lower right part, the supply ball is clogged, the lower part is full, the main power supply voltage is abnormal, the firing is stopped, the main control board communication is abnormal, A frame control board case 118 that houses a frame control unit (not shown) having a frame status indicator 117 that displays a ball motor abnormality or the like with a 7-segment LED is provided.

On the other hand, on the upper right end portion of the mechanism panel 102, there is a fuse box 119, a power switch 120, a power terminal board 121 and a jackpot, launch device control, ball break, door open, prize ball, ball lending, etc. A terminal substrate 122 provided with connection terminals is provided. A power cable 123 for receiving external power supply is also provided below the terminal board 122. A connection cable 124 extends upward from the frame control board case 118 and is connected to a prepaid card unit 13 having a power cable 125. Further, a ball passage member 126 for a lower plate portion is provided at a substantially central lower end portion of the mechanism panel 102. As the power switch 120, a seesaw type switch is used. The power switch 120 is operated to turn on / off the main power supply of the gaming machine 1, and is operated by a game shop clerk or the like prior to the daily business start of the game hall. When the power switch 120 is turned on, the electric power obtained by transforming the commercial power source to a predetermined voltage (for example, AC 24V) is supplied from the island facility to each power source provided in the gaming machine 1.

Next, the main control board 100 will be described with reference to FIG. On the main control board 100, a main circuit unit 200 including a CPU 201 and an input / output circuit unit 300 are formed (see FIG. 3). Hereinafter, the main circuit unit 200 and the input / output circuit unit 300 will be described in order.

As shown in FIG. 3, the main circuit unit 200 includes a CPU 201, an oscillation unit 210, a reset circuit unit 250, a first external input circuit unit 230, an I / O decode circuit unit 220, and a data bus stabilization unit 211. ing. Among these, as shown in FIG. 4, the CPU 201 includes a CPU core 280, a built-in RAM 281, a built-in ROM 282, a memory control circuit 283, a clock generator 284, an address decoder 285, a watchdog timer 286, a counter / timer 287, a parallel input / output. A port 288, a reset / interrupt controller 289, an external bus interface 290, and an output control circuit 291 are provided.

As shown in FIG. 5, the oscillation unit 210 includes a crystal oscillation module 204. Similarly, as shown in FIG. 5, the reset circuit unit 250 includes an initialization reset signal generation unit 212 (power-on initialization signal generation unit) and a user reset signal generation unit 213 (steady control initialization signal generation). Part). The initialization reset signal generation unit 212 includes a general-purpose initialization reset signal generation unit 218 (general-purpose initialization signal generation unit) and a CPU initialization reset signal generation unit 214 (electronic component initialization signal generation unit). ing. Among these, the general-purpose initialization reset signal generation unit 218 of the initialization reset signal generation unit 212 includes a power input connector 245, a reset input protection resistor 251, a Schmitt trigger inverter IC 252, 254, a low-pass (LP) filter circuit 253, and a NAND gate. 255, a NOR gate IC 258, and counter ICs 256 and 257. The CPU initialization reset signal generation unit 214 includes a flip-flop IC267, a Schmitt trigger inverter IC259, a counter IC260, and a NOR gate IC261. Further, the user reset signal generation unit 213 includes a flip-flop circuit unit 262, a counter IC 263, a Schmitt trigger inverter ICs 264 and 266, and a counter IC 265.

As shown in FIG. 7, the first external input circuit unit 230 includes an input connector unit 240, a switch driver 232, a signal matching unit 233, a standardized signal stabilization unit 234, and a resistance array 231. The input connector section 240 includes a frame connector 241 and a first special symbol start switch connector 242 which is a game board connector, a second special symbol start switch connector 243 and a normal symbol start switch connector 244. The standardized signal stabilization unit 234 includes a plurality of resistors, and the signal matching unit 233 includes a plurality of resistors and a capacitor.

As illustrated in FIG. 6, the I / O decode circuit unit 220 includes a device selection signal generation unit 215 and a gate signal generation unit 216. The device selection signal generation unit 215 includes a NOR gate IC 222, decoder ICs 223 and 224, and resistance arrays 221 and 228. The gate signal generation unit 216 includes a NOR gate IC 225, a NAND gate IC 226, a flip-flop IC 227, a resistor array 229, and a Schmitt trigger inverter IC 205. Similarly, as shown in FIG. 6, the data bus stabilization unit 211 includes a resistance array 203 and a buffer IC 202.

Next, functions of the CPU 201 of the main circuit unit 200 and each circuit unit will be described. Each terminal of the CPU 201 shown in FIG. 5 and the like is classified as follows.
(1) Address portions A0 to A15: 16-bit address bus output terminals.
(2) Data portions D0 to D7: 8-bit bidirectional data bus terminals.
(3) System control unit XM1: A signal output terminal indicating the machine cycle 1.
XMREQ: An output terminal for request signals to the memory space.
XIORQ: An output terminal for an input / output request signal to the I / O space.
XWR: A signal output terminal indicating that the data bus is in a write cycle.
XRD: An output terminal for a signal indicating that the data bus is in a read cycle.
XRFSH: Refresh signal output terminal.
(4) CPU controller XHALT: Halt signal output terminal.
XINT: Maskable interrupt request signal input terminal.
XNMI: Non-maskable interrupt request signal input terminal.
XSRST: System reset signal input terminal.
XSRSTO: System reset signal output terminal.
XURST: User reset signal input terminal.
IEO / SCLKO: A daisy chain signal / divided clock output terminal.
PRG: An input terminal for setting the CPU to the PROM mode.
MODE: An output terminal indicating the state of the operation mode of the CPU.
(5) I / O section CLK / TRG2 · CLK / TRG3: External clock / timer trigger signal input terminal.
ZC / TO0 / ZC / TO1: Built-in CTC signal output terminal.
PA0 to PA7: 8-bit parallel I / O terminals.
PB0 / XCSIO0 to PB3 / XCSIO3: 4-bit parallel I / O port, shared terminal for external device chip select.
(6) Clock units EXTAL1 and EXTAL2: crystal resonator connection terminals.
CLKO: System clock signal output terminal. A square wave having a duty of 50% obtained by dividing the input signal frequency of the EXTAL1 / EXTAL2 terminal by 1/2 is output.
(7) Power supply units VDD1 and 2: Power supply (+ 5V) terminals.
VSS1 and 2: Power supply (GND) terminals.
VBB: Backup terminal for the internal RAM 281.
(8) Other NC: Non-connection terminal.

The CPU 201 uses the internal RAM 281 as a work area based on the program written in the internal ROM 282 shown in FIG. Further, the CPU 201 has a RAM backup function for holding the contents of the built-in RAM 281 by a voltage holding unit connected to the VBB terminal and a fraud prevention function such as a program authentication function and a program execution prohibition function outside the designated area when the power is shut off. ing. The program authentication function is to check whether the authentication code calculated based on the program is correct when an initialization signal for initializing the CPU 201 is input when the power is turned on, and the authentication code is incorrect Is a function to stop program execution. The out-of-designated-area program execution prohibition function is a function for prohibiting execution of a program outside a predetermined address range.

In the CPU 201, an interrupt reset is performed at a constant cycle to prevent runaway. The cause of the runaway is excessive noise intrusion. In the CPU 201 of this embodiment, I / O mapped I / O decoding is performed, the XIORQ terminal is used, and the XMREQ terminal is not used. However, it is also possible to employ the memory mapped I / O method for decoding and use the XMREQ terminal.

The crystal oscillation module 204 of the oscillator 210 shown in FIG. 5 outputs an operation clock signal for the CPU 201. This operation clock signal is input to the EXTAL1 terminal of the CPU 201. A crystal oscillator is used in place of the crystal oscillation module 204, and this crystal oscillator is connected between the EXTAL 1 and 2 terminals, and an oscillation clock can be generated by the clock generator 284 of the CPU 201 (see FIG. 4). . However, in this embodiment, since the crystal oscillation module 204 is used and connected to the EXTAL1 terminal of the CPU 201, it is not necessary to match the crystal oscillator and the clock generation circuit.

Similarly, in the reset circuit unit 250 shown in FIG. 5, a general-purpose initialization reset signal generation unit 218 generates a general-purpose initialization reset signal, and a user reset signal generation unit 213 generates a user reset signal. The general-purpose initialization reset signal generation unit 218 converts the general-purpose initialization reset signal into a CPU initialization reset signal based on a system reset signal (hereinafter also referred to as a power-on reset signal) input from the outside via the power input connector 245. The data is output to the generation unit 214 and the input / output circuit unit 300. The CPU initialization reset signal generation unit 214 outputs a CPU initialization reset signal to the XSRST terminal of the CPU 201 based on a system reset signal input from the outside via the external input connector 245. The CPU initialization reset signal is a pulse signal that maintains the H level for a certain period of time when the power supply of the CPU 201 is stabilized, and then once changes to the L level and then further changes to the H level. By generating this CPU initialization reset signal, the CPU 201 is surely initialized at the time of power-on without being affected by the power signal. Further detailed functions of the CPU initialization reset signal generator 214 will be described later. The user reset signal generation unit 213 outputs a user reset signal to the XURST terminal of the CPU 201 based on the output signal from the XM1 terminal of the CPU 201 and the system reset signal. That is, the user reset signal generation unit 213 performs a count operation with the output signal of the XM1 terminal of the CPU 201 becoming L level, and supplies the CPU 201 with a user reset signal that is a pulse signal having a constant cycle.

Next, the function of the CPU initialization reset signal generation unit 214 will be described in more detail with reference to FIGS. The generation of an input signal to the CPU initialization reset signal generation unit 214 will also be described. First, when the system reset signal (FIG. 15 (1)) falls and becomes active, the clock signal to the counter ICs 256 and 257 is divided, and a predetermined time (T1) from the change of the system reset signal (same (1)). The output signal (2) of the counter IC 256 rises as an H active signal with a delay. The output signal of the counter IC 257 is sent to the Schmitt trigger inverter IC 259, and the output signal ((3)) from the Schmitt trigger inverter IC 259 to the NOR gate IC 261 changes to L.

On the other hand, the output signal (2) of the timer IC 256 is input to the clear terminal (CLR) of the flip-flop IC267. The flip-flop IC 267 generates an Enable input signal for the counter IC 260 at the subsequent stage based on the clock input from the oscillation unit 210, and the counter IC 260 at the subsequent stage outputs the output signal of the counter IC 257 as the output signal ((4)). A pulse that rises after a predetermined time (T2) with respect to (2) and further falls after a predetermined time (T3) is given. The NOR gate IC 261 negates the logical sum of the output signal of the Schmitt trigger inverter IC 259 (same as (3)) and the output signal from the Q2B terminal of the counter IC 260 (same as (4)). That is, when the output signal (same (3)) of the Schmitt trigger inverter IC259 falls, the output signal (same (4)) of the counter IC 260 maintains the L level, so that the output signal (same as the same) of the NOR gate IC261. (5)) changes to the H level (shows the first change mode). Further, as the output signal of the counter IC 260 (same (4)) changes to the H level, the output signal of the NOR gate IC 261 (same (5)) changes to the L level (showing the second change mode). ). Further, as the output signal of the counter IC 260 (same (4)) changes to H level again, the output signal of the NOR gate IC 261 (same (5)) changes to H level again.

In this embodiment, the predetermined times T1 to T3 are set to T1 = 349.9 ms and T2 = T3 = 667 ns.

The first external input circuit unit 230 shown in FIG. 7 transmits the signal of the ball detection switches requested from the CPU 201 to the CPU 201. In other words, various switch groups are connected to the first external input circuit unit 230 via the input connector unit 240, and when the CPU 201 reads the switch state, the state of each switch is changed from O 1 to O 5 of the switch driver 232. The data is sent to the CPU 201 from the terminal and the VO terminal. In the present embodiment, six output terminals (O1 to O5 terminals, VO terminals) of the switch driver 232 are used in accordance with the number of associated ball detection switches. These six terminals individually correspond to the six ports (PA0 to PA5) assigned by the CPU 201. Further, in this embodiment, the resistor array 231 reduces the impedance of the PA0 to PA5 terminals and suppresses the influence of external noise and the like.

The signal from the input connector unit 240 is subjected to noise removal by a combination of the internal circuit of the switch driver 232, the standardized signal stabilization unit 234, and the signal matching unit 233. Furthermore, voltage adjustment is also performed in the signal matching unit. This is based on the fact that some of the switches connected to the input connector section 240 have branched transmission destinations, and the detection signal is sent to other than the main control board 100. That is, since the load of the circuit system related to the switch is larger than that of other switches, the characteristics of the signal are different from those of other signals. For this reason, the signal matching unit 233 is provided on the corresponding signal line to achieve matching with other signals. The output signal of the signal matching unit 233 is input to the V1 terminal of the switch driver 232.

6 decodes an address signal from the CPU 201 and outputs a device selection signal (CS0 to CS6) and a gate signal (G) to the input / output circuit unit 300 (described later). To do. The device selection signal (CS0 to CS6) is a signal for selecting an external device (described later), and the gate signal is a signal for enabling the device selection signal (CS6). The device selection signals (CS0 to CS6) are classified into output device selection signals (CS0 to CS5) and input device selection signals (CS6).

The output device selection signal (CS0 to CS5) is determined when the CPU 201 is in a state of writing data to the input / output circuit unit 300 and the range address of the PB0 / XCSIO0 terminal is specified, and is determined in advance from the A0 to A4 terminals. If there is an address output, the decoder IC 223 outputs the address. That is, when an output signal from the D0 to D7 terminals of the CPU 201 is output to the input / output circuit unit 300 via the data bus, an output device selection signal (CS0 to CS5) is transmitted to the output port 400 shown in FIG. The signals are input to the 1D to 8D terminals of the flip-flop ICs 311 to 361. On the other hand, the address signal is converted into an output device selection signal (CS0 to CS5) by the I / O decode circuit unit 220, which is also transmitted to the output port 400 and input to the clock terminal of the corresponding flip-flop IC.

The input device selection signal (CS6) is formed by the NOR gate IC 222 and the decoder IC 224 when there is a predetermined address output from the A0 to A4 terminals and when there is an output from the PB1 / XCSIO1 terminal. It is output to the IC 371 (see FIG. 11). The gate signal generation unit 216 generates a gate signal (G) based on the oscillation clock output from the crystal oscillation module 204 and the output signals of the XRD terminal and the XIORQ terminal of the CPU 201, and this is also output to the buffer IC 371. The Further, in this embodiment, the impedance on the input terminal side is reduced by the resistor arrays 221, 228, and 229, and the output selection signal, the input selection signal, and the gate generated by the gate signal generation unit 216, respectively, generated by the device selection signal generation unit. The influence of external noise etc. on the signal is suppressed. In this embodiment, the data bus (OD, D) is divided into two paths. This is due to the load capacity between the CPU 201 and the flip-flop ICs 311 to 361, and may be a circuit configuration that does not need to be divided into two paths.

The data bus stabilization unit 211 stabilizes the signal on the data bus connecting the CPU 201 and the input / output circuit unit 300. The resistor array 203 reduces the noise entering the bus by reducing the impedance, and the buffer 202 includes the command output circuit units (310 to 340) for the award ball, lamp, display, and voice among the data buses divided into two paths. ) Output signal (OD0 to OD7) of the bus (OD) to.

Next, the input / output circuit unit 300 will be described. As shown in FIG. 3, the input / output circuit unit 300 includes a prize ball command output circuit unit 310, a lamp command output circuit unit 320, a display command output circuit unit 330, a voice command output circuit unit 340, a solenoid drive circuit unit 350, An LED drive / information output circuit unit 360 and a second external input circuit unit 370 are provided.

Among the circuit units 310 to 370 described above, the prize ball command output circuit unit 310, the lamp command output circuit unit 320, the display command output circuit unit 330, and the voice command output circuit unit 340 all have the same circuit configuration. ing. Therefore, in this embodiment, in order to avoid redundant drawings, only the prize ball command output circuit unit 310 is shown (FIG. 8), and the other circuit units 320 to 340 are indicated in parentheses in FIG. For the sake of simplicity, these illustrations are omitted. That is, the output circuit units 310, 320, 330, and 340 are connected to the flip-flop ICs 311, 321, 331, and 341, the buffer ICs 312, 322, 332, and 342, and the strobe signal line buffer ICs 313, 323, 333, and 343, respectively. Connectors 314, 324, 334 and 344 are provided.

As shown in FIG. 9, the solenoid drive circuit unit 350 includes a flip-flop IC 351, three lamp / solenoid drivers 352 to 354, and a free wheel diode 355 connected in parallel to the drain terminals of the lamp / solenoid driver. And an output connector 356.

As shown in FIG. 10, the LED drive / information output circuit unit 360 includes a flip-flop IC 361, a transistor array 362, a lamp / solenoid driver 363, a relay unit 365, a power adjustment unit 364, an output connector 356, and an information output connector 366. The flip-flop IC 351 also has a part of its configuration. The relay unit 365 includes two relays 367 and 368, and the power adjustment unit 364 includes ten resistors R4 to R13.

As shown in FIG. 11, the second external input circuit unit 370 includes a buffer IC 371, a switch driver 372, a resistance array 373, a power adjustment unit 374, and an output connector 356. The power adjustment unit 374 includes six resistors R21 to R26.

Also, as shown in FIG. 12, a prize ball command output circuit unit 310, a lamp command output circuit unit 320, a display command output circuit unit 330, a voice command output circuit unit 340, a solenoid drive circuit unit 350, and an LED drive / information output circuit The flip-flop ICs 311, 321, 331, 341, 351, and 361 of the unit 360 constitute six output ports of the output port circuit unit 400.

Next, functions of the circuit units 310 to 370 of the input / output circuit unit 300 will be described. In the output port circuit unit 400 shown in FIG. 9, data (OD, D), device selection signals (CS0 to CS5), and a clear signal (CLR) from the main circuit unit 200 are input. An external device is assigned to each port of the output port circuit unit 400. Examples of the external device include a prize ball device, a lamp device, a display device, a sound device, a solenoid device, an LED device, and a hall computer. Data (OD) is input to the 1D to 8D terminals of the flip-flop ICs 311 to 361. The device selection signals (CS0 to CS5) are input to the clock terminals of the corresponding flip-flops IC311 to 361. In the flip-flop ICs 311 to 361 selected by the device selection signal (CS0 to CS5), the data (OD, D) from the main circuit unit 200 is input to the 1D to 8D terminals, and the device selection signal (CS0 to CS5) Data is output from the 1Q to 8Q terminals at the timing of the rising edge. In the output port circuit unit 400, when the gaming machine 1 is turned on, the flip-flop ICs 311, 321, 331, 341, 351, 361 are generated by the initialization reset signal from the general-purpose initialization reset signal unit 212 described above. Is initialized.

The various command output circuit units 310 to 340 shown in FIG. 8 transmit command data to a prize ball device, a lamp device, a display device, and a sound device, which are external devices at the subsequent stage. That is, one of the command output circuits 310 to 340 is selected by the device selection signal (CS0 to CS3). The command data output from the flip-flop ICs 311 to 341 is input to the terminals A1 to A8 of the buffer ICs 312, 322, 332, and 342 and output to the connectors 314 to 344. The output enable terminals G1 and G2 of the buffer ICs 312, 322, 332, and 342 are grounded, and the buffer ICs 312, 322, 332, and 342 output signals with enhanced drive capability. The control signals handled by the various command output circuit units 310 to 340 are 9 bits in total including 8 bits of data and 1 bit of strobe, but the number of data bits may be changed depending on the connected external device.

The solenoid drive circuit unit 350 shown in FIG. 9 is a circuit unit that is selected by a device selection signal (CS4) and drives a solenoid device that is an external device in accordance with the gaming state. In the solenoid drive circuit unit 350, lamp / solenoid drivers 352 to 354 are associated with solenoids. The flip-flop IC 351 outputs a signal from the 5Q to 7Q terminals to the corresponding lamp / solenoid drivers 352 to 354. Further, when the input signal from the flip-flop IC 351 to the IN terminals of the lamp / solenoid drivers 352 to 354 is at the H level, the lamp / solenoid drivers 352 to 354 drive the solenoid device. The flip-flop IC 351 also functions as a strobe signal generation unit that transmits a strobe signal to the command output circuit units 310 to 340. That is, as shown in FIG. 10, the flip-flop IC351 transmits the output signals from the 1Q to 4Q terminals to the strobe signal buffers IC313 to 343 of the corresponding command output circuit units 310 to 340 as strobe signals.

The freewheel diode 355 circulates the sustained current when the output signals of the lamp / solenoid drivers 352 to 354 are switched from the H level to the L level by the function of sustaining the load current during the high-speed switching operation. Instead of the lamp / solenoid drivers 352 to 354, for example, a transistor or FET can be used to drive the solenoid.

The LED drive / information output circuit unit 360 shown in FIG. 10 is used for driving a normal symbol LED and for outputting external information to a hall computer or the like. Data output from the flip-flop IC361 of the LED drive / information output circuit unit 360 is input to the I1 to I8 terminals of the transistor array 362. In the transistor array 362, 2 bits are normally assigned to the design LED and 6 bits are assigned to the external information output. The outputs of the O1-O7 terminals of the transistor array 362 are output to the output connector 356. The output of the O8 terminal of the transistor array 362 is sent to the information output connector 366 via the relay 368 of the relay unit 365. Note that the output signal of the transistor array 362 is current-controlled by the resistors R4 to R13 of the protective resistance unit 364.

The second external input circuit unit 370 shown in FIG. 11 is a circuit unit that inputs the state of various switches to the CPU 201, and the number of signal lines of the data bus (D0 to D5) to be used is equal to the number of connected switches. It corresponds. A detection signal from the output connector 356 is input to the I1 to I6 terminals of the switch driver 372 via the power adjustment unit 374. In the power adjustment unit 374, noise removal and voltage adjustment are performed by a combination of the resistors R21 to R26 and the internal circuit of the switch driver 372. Output signals from the O1 to O6 terminals of the switch driver 372 are input to the buffer IC 371. The switch driver 372 has a short-circuit detection function, and when a switch connected to the I1 and I2 terminals is in a short-circuit state, the output signal changes from H level to L level. Furthermore, the resistor array 373 reduces the impedance of the A1 to A8 terminals of the buffer IC 371 to suppress the influence of external noise and the like.

The gate signal (G) from the main circuit unit 200 is input to the G2 terminal of the buffer IC 371, and the buffer IC 371 amplifies the signal from the switch driver 372 and outputs it to the data bus (D).

In the gaming machine 1 of the present embodiment, as the gaming machine 1 is turned on, the power supplied to the gaming machine 1 from the outside (indicated by voltage (1) in FIG. 14) rises and a system reset signal (“power-on” (2)), also referred to as “reset signal”, is supplied to the main control board 100, and when the CPU initialization reset signal as described above is supplied to the CPU 201, the externally supplied power ((1)) is supplied. After the rise, the CPU 201 is initialized by an initialization reset signal for CPU at the L level ((3), FIG. 15 (5)). Thereafter, the CPU initialization reset signal ((3), FIG. 15 (5)) once rises, then falls, and returns to the L level. Therefore, the CPU 201 receives the initialization signal again. Then, the CPU initialization reset signal ((3), FIG. 15 (5)) again indicates the H level, and the control of the gaming machine 1 shifts to the steady state. That is, according to the gaming machine 1, since a plurality of change forms are given to the CPU initialization reset signal ((3), FIG. 15 (5)), only a single change form is given. Compared to the CPU 201, the CPU 201 can be initialized more reliably and stably, and the operation of the gaming machine can be stabilized. The reason why such a result was obtained is as follows. In other words, when the power of the gaming machine 1 is shut off, the charge stored in the capacitor constituting the noise filter or the like remains in the internal circuit of the CPU 201. For example, when the power is turned on the next game day business day, As a result, a signal that exceeds the threshold value is generated partly early, and the initialization signal to the CPU 201 shows the same level both when the power supply potential (FIG. 14 (2)) rises and when the CPU 201 is initialized. As a result, rising imbalance occurs, and control stability is impaired. However, as in the gaming machine 1 of the present embodiment, by adding a plurality of changes to the CPU initialization reset signal ((3), FIG. 15 (5)), a change of additional compensation is included. Thus, it becomes possible to eliminate the remaining defective elements that could not be solved only by giving a single change form.

In the technical field of gaming machines, the CPU 201 is mainly developed by designated organizations based on administrative guidance, and from the viewpoint of fraud prevention etc., all of the configuration of the internal circuit of the CPU 201 is even a gaming machine manufacturer. It will not be revealed. Therefore, the cause of the malfunction when the CPU 201 is reset is not limited to the above.

14 and 15 both explain the initialization reset signal for the CPU, and both figures include the system reset signal (FIG. 14 (2), FIG. 15 (1)). (2) shows a system reset signal input to the main control board 100, and FIG. 15 (1) shows a system reset signal (NAND gate 255 (FIG. 5) formed after input to the main board. Reference) output signal) is shown. In the present embodiment, both of these are described as “system reset signals”. However, for example, before molding can be distinguished as “system reset signal before molding” and “system reset signal after molding”. is there. This is the reason why the waveform of FIG. 14 (2) and the waveform of FIG. 15 (1) are highlighted.

The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the technical idea thereof. For example, the CPU initialization reset signal generation unit 214 may be provided in the CPU 201. In this way, the external circuit of the CPU 201 can be simplified, and the main control board 100 can be downsized. And it becomes possible to simplify the back structure of the gaming machine 1 and to increase the degree of freedom in the design of the arrangement of the baskets through which the game balls flow down. Furthermore, in this embodiment, the first change form of the CPU initialization reset signal is a rising form, and the second change form is a falling form of the same signal. These may be considered as a constant waveform pattern including rising and falling, and may be combined. In this case, the number of rising and falling edges is not limited to one, and one or a plurality of selections can be made as appropriate. For example, the fall after the power is turned on and the subsequent rise of the CPU initialization signal in the present embodiment can be regarded as the second variation.

Also, a time T1 from the fall of the system reset signal (FIG. 15 (1), etc.) to the preceding rise of the CPU initialization signal (FIG. 15 (5)), from there, the CPU initialization signal (FIG. 15 ( The time T2 until the falling of 5)) and the time T3 until the subsequent rising of the CPU initialization signal (FIG. 15 (5)) can be appropriately changed.

In this embodiment, T1 is set to about 500 times T2 (and T3), and T2 and T3 are set equal. In order to initialize the CPU 201 more stably, it is desirable to set T1 sufficiently large. T2 and T3 do not necessarily need to be set equal. When both are set to be equal, a waveform can be generated with the same circuit configuration, so that the circuit design and configuration are simplified. As a modification, for example, it is conceivable that T2 and T3 are set based on a common clock signal as in the present embodiment, and T2 is set larger than T3. The reason why T2 is increased is to give the CPU 201 a sufficient initialization time, and the reason why T3 is decreased is to stabilize the control of the CPU 201 earlier. As a definition method of T2 and T3, it is conceivable that the minimum value is defined by the number of clocks (for example, 4) and the maximum value of T2 is 100 ms.

1 gaming machine 100 main control board 120 power switch 201 CPU
210 Oscillator 212 Initialization Reset Signal Generation Unit 213 User Reset Signal Generation Unit 214 CPU Initialization Reset Signal Generation Unit 218 General Purpose Initialization Reset Signal Generation Unit 250 Reset Circuit Units 256 and 257 Counter IC
259 Schmitt trigger inverter IC
260 Counter IC
261 NOR gate IC
267 Flip-flop IC

Claims (8)

In a gaming machine equipped with a control device for performing control related to a game,
The control device includes an initialization signal generation unit that generates an initialization signal, and an electronic circuit unit that is initialized based on the initialization signal, and the initialization signal generation unit includes a plurality of changes in the initialization signal. A gaming machine characterized by giving form.   The initialization signal indicates an initializable form of the electronic circuit unit prior to showing the first change form, and then indicates an uninitialized form of the electronic circuit part according to the first change form. The gaming machine according to claim 1.   The plurality of change forms are first and second change forms, and the first and second change forms are different forms of signal rising or falling forms. Item 3. The gaming machine according to Item 2.   The gaming machine according to any one of claims 1 to 3, wherein the initialization signal generation unit generates the initialization signal based on a reference signal that is generated or changed when power is turned on.   5. The gaming machine according to claim 1, wherein the initialization signal generation unit includes a power-on initialization signal generation unit and a steady control initialization signal generation unit.   6. The gaming machine according to claim 5, wherein the power-on initialization signal generator includes a general-purpose initialization signal generator and an electronic circuit initialization signal generator.   The gaming machine according to claim 1, wherein the electronic circuit unit is a CPU.   The initialization signal generation unit is configured to change the application timings of the plurality of change forms, eliminate residual defect elements remaining in the initialization related to the change form of the previous stage from the input of the change form of the subsequent stage, and The gaming machine according to claim 1, wherein the initialization is compensated.

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