JP2002066094A - Game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure input to a CPU performed from external equipment through a data bus. SOLUTION: This game machine is provided with a reception side CPU 201 connectable with one or plural external equipment to be a data transmission origin and for receiving data from the external equipment through the data bus, a buffer IC 371 for switching connection/non-connection between the CPU 201 and the external equipment based on changeover command signals from the CPU 201 and a gate signal generation part 216 provided separately from the CPU 201 and interposed between the CPU 201 and the buffer IC 371 for adjusting the timing of the transmission to the buffer 371 of the changeover command signals from the CPU 201. Thus, the collision of the data in the data bus is prevented matched with the characteristics of the various kinds of electronic components.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a gaming machine whose game is controlled by a control circuit including a CPU.

[0002]

2. Description of the Related Art Generally, gaming machines such as pachinko machines employ computer control. From the time the game machine is turned on to the time of a normal game, the generation of signals and input / output control required for computer control are performed. Is being done.
For this reason, the selection of the CPU and the waveform of the generated signal depend on various factors such as the desired performance of the gaming machine for which permission is granted, game characteristics (game content and interest), and production and running costs. It is decided in consideration of it. In the control of a gaming machine, reset control is performed in consideration of fairness between a player and a game arcade and a severe operating environment (dust, electric noise, etc.) of the game arcade. The reset control mainly includes a reset control when the power of the gaming machine is turned on (hereinafter referred to as a power-on reset) and a reset control (user reset) that is constantly performed while the gaming machine is operating.
There is. The former power-on reset is a control that is performed in preparation for the start of business, for example, before opening a game hall every day,
Before starting the normal game control, the control data of the entire game machine is initialized in preparation for the steady control when the main power of the game machine is turned on. On the other hand, the latter user reset is a control that is repeatedly performed in a short cycle (for example, every 2 ms) in the steady control, and the main control of the game is reset to the initial state every time, leaving necessary data generated according to the progress of the game. Will be returned. By this user reset, even if a runaway of the gaming machine occurs in a severe operating environment in the game arcade, the initial state of the control is restored in a short period of time, thereby preventing the disturbance from adversely affecting the game. Further, it is necessary to design the input and output of signals to and from the CPU at an appropriate time in consideration of the operation inside the CPU. That is, for example, even if a signal is input while the CPU is not ready for signal reading, the CPU cannot use the input signal appropriately. As a CPU that has prevented such a problem, there is a CPU that outputs a readable signal when readable and outputs a writable signal when writable to match the timing of signal input / output with peripheral circuits.

[0003]

However, when the power is turned on,
System reset (power only)
The signal is also shown with reference to FIG.
Power supply to the gaming machine ((1) shows its potential state
) For a certain period of time T ₀of
L level (active) for a while, then H level
(Inactive). This system reset signal
Is initialized at L level after power-on
Is done. However, actually, the power signal (1) and the power
-The relationship with the on-reset signal (2) is CP as designed.
Not reflected in the operating state of U, some control circuits
Behaves unexpectedly at an intermediate potential during the rise
was there. Such defects are extremely difficult during the development stage.
This is a rare phenomenon and millions of games are produced annually.
Although it does not occur on many machines,
In gaming machines where value media is given to players according to
Increases the fairness of the game and does not harm public order and morals
It is necessary to stably exhibit desired performance. did
Therefore, occurrence of phenomena that differ from the gaming machine designer's
Control as much as possible, and
It is important to take some measures to ensure proper operation.
You. Also, regarding the signal input / output of the CPU,
Outputs a writable signal when the signal is output from the
If a readable signal was output at the appropriate time,
CPU operation is unstable because the characteristics of electronic components are not reflected
There is a fear that.

An object of the present invention is to provide a gaming machine capable of further stabilizing a control operation.

[0005]

SUMMARY OF THE INVENTION In a gaming machine provided with a control device for performing control relating to a game, a gaming device includes one or a plurality of transmission source devices serving as data transmission sources and a data bus from the transmission source device. And a switching unit provided on the data bus for switching connection / disconnection between the CPU and the transmission source device based on a switching command signal from the receiving CPU. And a switching command signal transmission timing that is provided separately from the receiving CPU and that is interposed between the receiving CPU and the switching unit to adjust the transmission timing of the switching command signal from the receiving CPU to the switching unit. Adjusting means.

With this configuration, when the CPU switches the input / output of the bus interface, the timing at which the read / write switching signal is input to the input port is determined.
The switching command signal transmission timing adjusting means can adjust. As a result, the read / write switching signal can be prevented from preceding the input / output switching of the bus interface of the CPU in accordance with the characteristics of various electronic components, and the signal existing at the interface before data input from the input port can be prevented. It is possible to prevent the CPU from reading incorrect data due to the potential. Further, data collision (so-called conflict) on the data bus can be prevented.

The CPU outputs a switching command signal substantially at the same time as the input / output switching timing. The switching command signal transmission timing adjusting means delays the switching command signal by a predetermined time and relays the switching command signal to the switching unit. Can be That is, since the CPU outputs the switching command signal at a substantially constant timing, a predetermined time delay corresponding to the switching command signal is applied to the signal output, so that the data input from the input port to the CPU can be read stably without variation. Can be realized. If the clock pulse of the CPU is used to create the timing of the delay, the operation of the delay circuit is also synchronized with the CPU, so that a more reliable reading operation can be performed. For example, a D-type flip-flop IC is used as a circuit element operated by such a clock pulse.

The switching command signal transmission timing adjusting means is C
By forming it outside the PU, a stable operation can be obtained without changing the CPU. In other words, in a gaming machine, from the viewpoint of fairness and public order and morals, the CPU used
Is limited, and a gaming machine manufacturer cannot arbitrarily select a CPU or commercialize a developed product. For this reason, by forming the switching command signal transmission timing adjusting means outside the CPU, it is possible to use a CPU of a standard purchase product.

It is also conceivable to provide such a delay circuit or delay means inside the CPU. For example, a program that delays the output timing of the read / write signal by a predetermined time based on the system clock or the like in response to the switching of the input / output mode of the bus interface is RO.
M may be stored.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to an embodiment shown in the drawings, taking a first-type gaming machine as an example. FIG. 1 is a front view of a gaming machine 1 of the present invention. The front part of the gaming machine 1 includes a main body frame 2, a middle frame 3, a front frame 4, and an upper plate 5
, A lower plate 6 and a locking device 7. The main body frame 2 is formed by assembling and fixing a wooden plate-like body into a substantially rectangular frame shape. The middle frame 3 is almost entirely made of plastic, has a frame portion (not shown) and a lower plate portion (not shown), and is fitted and attached to the inner peripheral side of the main body frame 2. A locking device 7 is provided at the center of the right end. The locking device 7 has a substantially rectangular shape with a keyhole when viewed from the front, and locks when the front frame 4 is closed.

The front frame 4 is entirely made of plastic, and has a substantially arcuate upper side corresponding to the shape of the game area formed on the game board 10 so that the game board 10 can be visually recognized from the front. It has an opening 4a formed in a substantially bullet shape. A substantially rectangular glass frame (not shown) in which a glass plate is fitted according to the opening 4a is mounted on the back surface. The front frame 4 occupies 2/3 of the entire front surface of the gaming machine 1 and is pivotally mounted on the left end of the middle frame 3 so as to be openable and closable.

The game board 10 is a substantially rectangular wooden plate-like body, held by the middle frame 3, and has a back mechanism board 102 (FIG.
), The back side of which is covered, and a substantially circular game area is formed by the outer rail and the inner rail provided on the surface,
In the game area, game devices related to the game, such as a special symbol display device and a variable winning device, are provided.

Here, the frame portion is formed in a substantially rectangular frame shape from the upper end to about 2/3 of the entire middle frame 3, and the upper end portion is formed along the arc portion of the upper end portion of the opening 4a. Frame decoration lamps 4b, 4c, 4e, and 4h are provided, and a frame decoration lamp substrate 4g is installed correspondingly. The award ball display LED 4i and the award ball display LED board 4d are provided in the upper middle frame 3 on the left side, and the stop display L is provided on the upper right side.
An ED 4j and a stop display LED board 4f are provided.

The lower plate portion occupies approximately 1/3 of the entire inner frame 3 from the lower end to the upper side. On the left side, a game state is set to correspond to the speaker surface 5a formed on the upper plate portion 5. A speaker (not shown) for generating a corresponding sound effect or other audio information is provided. On the substantially right side, a speaker unit 8 (see FIG. 2) for firing a game ball is stored in the upper plate portion 5. A supply device or the like (not shown) for supplying game balls is provided. Further, a lower plate 6 is provided below.

The lower tray 6 is provided with an ashtray, a ball-drawing lever, and the like, and has an outlet 6a for discharging game balls from the inside of the gaming machine 1, and a firing unit 8 at the right end (see FIG. 2). A firing handle 9 for operating the vehicle is provided. A touch switch 9a for detecting that the player is touching is mounted on the firing handle 9, and a fire stop switch 9b for temporarily instructing a stop of the fire is arranged near the touch switch 9a.

The upper plate 5 is pivotally attached to the left end of the middle frame 3 below the front frame 4 so as to be openable and closable. Dish outer edge 5
In b, a ball removal button, a game ball lending / returning button, and the like are provided. A discharge port 5c for discharging game balls from the inside of the gaming machine 1 is provided. A speaker surface 5a having a plurality of long holes is formed on the left end, and a volume switch board (not shown) is provided on the back surface.
At the left end of the gaming machine 1, a prepaid card unit 13 is provided.
Is installed. The game board 10 is detachably attached to the front side of the middle frame 3.

Next, the back surface structure of the gaming machine 1 of the embodiment will be described with reference to FIG. The front frame 4 is in the middle frame 3 and is supported by a pair of hinges 101 provided at the upper and lower ends of the front frame 4 so as to be openable and closable. Mechanism panel 10
Reference numeral 2 denotes a middle frame 3 which is supported by a pair of hinges 103 provided at the upper and lower ends of a mechanism panel 102 so as to be openable and closable. On the left side when viewed from the position of the hinge 101 at the upper end, a prize ball tank 105 provided with a tank ball out detection switch 104 at the bottom of the tank, and a prize ball tank 105
And a tank rail 106 connected thereto. A ball release lever 107 is provided on the right side of the tank rail 106, a supply ball out detection switch 108 is provided downstream thereof, and a prize ball payout device 109 is provided downstream thereof. I have.

Subsequently, a game ball distribution unit 110 is provided downstream of the prize ball payout device 109. A lower case 111 with a lid containing a display control unit (not shown) is provided below the tank rail 106, and a main control board case 112 containing a main control board 100 described below is provided below the lower case 111. Are detachably provided.
On the left side of the main control board case 112, a launcher control board case 113 storing a launcher control board (not shown),
Touch sensitivity adjustment knob 114, ball fly strength adjustment knob 1
15 and a launch control collective relay board 116 are provided. In the lower left portion of the mechanical panel 102, the above-described firing device unit 8 is also provided. In the lower right portion, the supply ball is clogged, the lower plate portion is full, the main power supply voltage is abnormal, the firing is stopped, the main control board communication is abnormal, and the prize. A frame control board case 118 containing a frame control unit (not shown) including a frame status indicator 117 for displaying a ball motor abnormality or the like with a 7-segment LED is provided.

On the other hand, at the upper right end of the mechanical panel 102, there are a fuse box 119, a power switch 120, a power terminal board 121 and a jackpot, a launch machine control, a ball out, a door open, a prize ball, a ball lending machine and the like. A terminal board 122 provided with a frame external connection terminal is provided. A power cable 123 for receiving power supply from outside is also provided below the terminal board 122. A connection cable 124 extends upward from the frame control board case 118, and a prepaid card unit 13 having a power cable 125.
It is connected to the. A ball passage member 126 for a lower plate portion is provided substantially at the lower end of the center of the mechanism panel 102.

Next, the main control board 100 will be described with reference to FIG. The main control board 100 includes a CPU 2
The main circuit section 200 including the first and the second input / output circuits 01 and the input / output circuit section 300 are formed (see FIG. 3). Hereinafter, the main circuit unit 200
And the input / output circuit unit 300 will be described in order.

As shown in FIG. 3, the main circuit 200
PU 201, oscillator 210, reset circuit 250, first external input circuit 230, I / O decode circuit 22
0 and a data bus stabilizing unit 211. As shown in FIG. 4, the CPU 201 includes a CPU core 280, a built-in RAM 281, a built-in ROM 282, a memory control circuit 283, a clock generator 284, an address decoder 285, a watch dog timer 286, a counter / timer 287, and a parallel input / output. A port 288, a reset / interrupt controller 289, an external bus interface 290, and an output control circuit 291 are provided.

As shown in FIG. 5, the oscillating unit 210 includes a crystal oscillation module 204. Also, as shown in FIG. 5, the reset circuit unit 250 includes an initialization reset signal generation unit 212 (an initialization signal generation unit for power-on).
And a user reset signal generation unit 213 (initialization signal generation unit for steady control). The initialization reset signal generation unit 212 includes a general-purpose initialization reset signal generation unit 218.
(General-purpose initialization signal generation unit) and a CPU initialization reset signal generation unit 214 (electronic component initialization signal generation unit). Among these, the general-purpose initialization reset signal generation unit 218 of the initialization reset signal generation unit 212
Power input connector 245, reset input protection resistor 25
1, Schmitt trigger inverter ICs 252, 254,
Low-pass (LP) filter circuit 253, NAND gate 255, NOR gate IC 258, and counter IC
256, 257. The CPU initialization reset signal generation unit 214 is a flip-flop IC
267, a Schmitt trigger inverter IC 259, a counter IC 260, and a NOR gate IC 261. Further, the user reset signal generation unit 213 includes a flip-flop circuit unit 262, a counter IC 263,
It is composed of Schmitt trigger inverters 264 and 266 and a counter IC 265.

As shown in FIG. 7, the first external input circuit 2
30 is an input connector section 240, a switch driver 23
2, a signal matching unit 233, a standardized signal stabilizing unit 234, and a resistor array 231. Input connector section 240
Are the frame connector 241 and the first game board connector.
It has a special symbol start switch connector 242, a second special symbol start switch connector 243, and a normal symbol start switch connector 244. The standardized signal stabilizing unit 234 includes a plurality of resistors, and the signal matching unit 233
Is composed of a plurality of resistors and capacitors.

As shown in FIG. 6, the I / O decode circuit section 220 has a device selection signal generation section 215 and a gate signal generation section 216. Device selection signal generator 2
15 is a NOR gate IC 222, a decoder IC 22
3, 224 and resistance arrays 221 and 228.
The gate signal generator 216 constituting the switching command signal transmission timing adjusting means includes a NOR gate IC 225,
NAND gate IC 226, flip-flop IC 22
7, a resistor array 229 and a Schmitt trigger inverter 205. As also shown in FIG. 6, the data bus stabilizing unit 211 includes a resistor array 203 and a buffer I
C202.

Next, the functions of the CPU 201 of the main circuit section 200 and each circuit section will be described. CPU 201 shown in FIG.
Are classified as follows. (1) Address section A0 to A15: 16-bit address bus output terminals. (2) Data section D0 to D7: 8-bit bidirectional data bus terminals. (3) System control unit XM1: An output terminal for a signal indicating machine cycle 1. XMREQ: output terminal of a request signal to the memory space. XIORQ: an output terminal for an input / output request signal to the I / O space. XWR: an output terminal for a signal indicating that the data bus is in a write cycle. XRD: an output terminal for a signal indicating that the data bus is in a read cycle. XRFSH: refresh signal output terminal. (4) CPU control unit XHALT: Halt signal output terminal. XINT: Input terminal of a maskable interrupt request signal. XNMI: an input terminal for a non-maskable interrupt request signal. XSRST: Input terminal for system reset signal. XSRTO: output terminal for system reset signal. XURST: User reset signal input terminal. IEO / SCLKO: A shared output terminal for daisy chain signals and frequency-divided clocks. PRG: Input terminal for setting the CPU to PROM mode. MODE: an output terminal indicating the state of the operation mode of the CPU. (5) I / O section CLK / TRG2 / CLK / TRG3: external clock /
Input terminal for timer trigger signal. ZC / TO0 / ZC / TO1: Output terminal for built-in CTC signal. PA0 to PA7: 8-bit parallel I / O terminals. PB0 / XCSIO0 to PB3 / XCSIO3: 4-bit parallel I / O port, dual-purpose terminal for chip select of an external device. (6) Clock section EXTAL1 and EXTAL2: crystal oscillator connection terminals. CLKO: Output terminal of the system clock signal. EXTA
A 50% duty square wave obtained by dividing the input signal frequency of the L1 / EXTAL2 terminal by 1/2 is output. (7) Power supply section VDD1 / 2: Power supply (+ 5V) terminal. VSS1,2: Power supply (GND) terminals. VBB: Backup terminal of built-in RAM. (8) Others NC: Non-connection terminal.

The CPU 201 has a built-in RO shown in FIG.
Based on the program written in M282, the built-in RA
M281 is used as a work area. CPU2
01 is an R which holds the contents of the built-in RAM 281 by the voltage holding unit connected to the VBB terminal when the power is turned off.
It has an AM backup function and a fraud prevention function such as a program authentication function and a program execution prohibition function outside the designated area. When the power is turned on, the program authentication function
When an initialization signal for initializing the PU 201 is input, a check is performed to determine whether or not the authentication code calculated based on the program is correct. If the authentication code is incorrect, the program execution is stopped. is there. The program execution prohibition function outside the designated area is a function for prohibiting execution of a program outside a predetermined address range.

In the CPU 201, an interruption reset is performed at a constant cycle to prevent runaway. Causes of runaway include excessive noise penetration and the like. Also,
In the CPU 201 of the present embodiment, the I / O mapped I
The decoding of the / O method is performed, the XIORQ terminal is used, and the XMREQ terminal is not used. However, the memory mapped I / O method is used for decoding, and XMRE
It is also possible to use the Q terminal.

The crystal oscillation module 204 of the oscillation section 210 shown in FIG. This operation clock signal is output from the E
It is input to the XTAL1 terminal. Note that a crystal oscillator is used instead of the crystal oscillation module 204, and this crystal oscillator is connected between the EXTAL1 and EXTAL2 terminals, and an oscillation clock can be generated by the clock generator 284 (see FIG. 4) of the CPU 201. . However, in this embodiment, the crystal oscillation module 204 is used, and the
Since it is connected to the AL1 terminal, it is not necessary to match the crystal oscillator with the clock generation circuit.

In the reset circuit section 250 also shown in FIG. 5, a general-purpose initialization reset signal generation section 218 generates a general-purpose initialization reset signal, and a user reset signal generation section 213 generates a user reset signal. The general-purpose initialization reset signal generation unit 218 converts a general-purpose initialization reset signal into a CPU initialization reset signal generation unit based on a system reset signal (also referred to as a power-on reset signal) input from outside via the power input connector 245. 214 and an output port 400 described later (FIG. 1
2) of the flip-flop ICs 311 to 361
Output to the ear terminal and initialize it.

CPU initialization reset signal generator 214
XS of the CPU 201 is based on a system reset signal input from the outside via the external input connector 245.
An initialization reset signal for CPU is output to the RT terminal. C
The PU initialization reset signal is a pulse signal that maintains the H level for a certain period of time at the time when the power supply of the CPU 201 is stabilized, and then temporarily changes to the L level and then further changes to the H level. By generating the CPU initialization reset signal, the CPU 201 reliably performs initialization at power-on without being affected by the power signal.
Note that further detailed functions of the CPU initialization reset signal generation unit 214 will be described later.

The user reset signal generation unit 213 outputs C
A user reset signal is output to the XURST terminal of the CPU 201 based on the output signal of the XM1 terminal of the PU 201 and the system reset signal. That is, the user reset signal generation unit 213 performs a counting operation when the output signal of the XM1 terminal of the CPU 201 becomes L level, and supplies the CPU 201 with a user reset signal which is a pulse signal of a constant cycle.

Next, the function of the CPU reset signal generator 214 will be described in more detail with reference to FIGS. The CPU initialization reset signal generation unit 2
The generation of the input signal to 14 will also be described. First, when the system reset signal (FIG. 15 (1)) falls and becomes active, the clock signal to the counter ICs 256 and 257 is frequency-divided, and a predetermined time (T ₁ ) from the change of the system reset signal ((1)). With a delay, the output signal of the counter IC 256 ((2)) rises as an H active signal. The output signal of the counter IC 257 is sent to the Schmitt trigger inverter IC 259, and the Schmitt trigger IC 259 outputs the NOR gate IC.
The output signal ((3)) to H.261 changes to L.

On the other hand, the output signal of the timer IC 256
((2)) clears the flip-flop IC 267
Input to the terminal (CLR). Flip-flop IC2
67 is based on a clock input from the oscillation unit 210,
Generates the Enable input signal of the counter IC 260 at the subsequent stage.
The counter IC 260 at the subsequent stage outputs the output signal (the same
(4)) shows the output signal of the counter IC 257 (
(2)) for a predetermined time (T ₂) Stand up late and update
A predetermined time (T₃) Give a falling pulse later. N
OR gate IC 261 is a Schmitt trigger inverter
The output signal of IC 259 ((3)) and the counter IC 2
Logic with the output signal ((4)) from the Q2B terminal of No. 60
Take the negation of the sum. In other words, Schmitt trigger inverter
When the output signal (3) of the IC 259 falls,
Output signal of counter IC 260 ((4)) is at L level
Is maintained, the output signal of the NOR gate IC 261 is maintained.
Signal (5) changes to the H level (first change mode)
Is shown). Further, the output signal of the counter IC 260 (the
As (4)) changes to the H level, the NOR gate
Output signal of IC 261 ((5)) changes to L level
(Showing a second variation). Also, the counter IC2
60 output signal ((4)) changes to the H level again.
Accordingly, the output signal of the NOR gate IC 261 (the
(5)) changes to the H level again.

In the present embodiment, the predetermined times T _{1 to} T ₃ are T ₁ = 349.9 ms and T ₂ = T ₃ = 6.
It is set to 67 ns.

The first external input circuit section 230 shown in FIG.
The signal of the ball detection switches requested from the CPU 201 is transmitted to the CPU 201. That is, various switch groups are connected to the first external input circuit unit 230 via the input connector unit 240. When the CPU 201 reads the switch state, the state of each switch is set to the switch driver 2
It is sent to the CPU 201 from 32 O1 to O5 terminals and the VO terminal. In the present embodiment, six output terminals (O1 to O5 terminals, VO terminals) of the switch driver 232 are used in accordance with the number of ball detection switches associated with each other. These six terminals correspond to the six ports (PA0 to PA5) assigned by the CPU 201, respectively. In this embodiment, the impedance of the terminals PA0 to PA5 is reduced by the resistor array 231.
The influence of external noise and the like is suppressed.

The signal from the input connector section 240 is subjected to noise removal by a combination of the internal circuit of the switch driver 232, the standardized signal stabilizing section 234, and the signal matching section 233. Further, voltage adjustment is also performed in the signal matching unit. This is based on the fact that some of the switches connected to the input connector unit 240 have a branch destination, and a detection signal is sent to other than the main control board 100. That is, since the load of the circuit system related to the switch is larger than that of the other switches, the characteristics of the signal are different from those of the other signals. For this reason, the signal matching unit 233 is provided on the corresponding signal line to achieve matching with other signals. The output signal of the signal matching unit 233 is input to the V1 terminal of the switch driver 232.

The I / O decode circuit 220 shown in FIG.
Decodes the address signal from the CPU 201 and outputs a device selection signal (CS0 to CS6) and a gate signal (G) to the input / output circuit unit 300 (described later). The device selection signals (CS0 to CS6) are signals for selecting an external device (described later), and the gate signal is a signal for validating the device selection signal (CS6). The device selection signals (CS0 to CS6) include an output device selection signal (CS0 to CS5) and an input device selection signal (CS
6). When a range address (upper) of the PB0 / XCSIO0 terminal is designated, a signal is output from the PB0 / XCSIO0 terminal, and an address signal (lower) is output from the A0 to A4 terminals. The address signal is decoded by the NOR gate IC 222 and the decoder IC 223 into output device selection signals (CS0 to CS5). CP
When the output signals of the D0 to D7 terminals of U201 are output to the input / output circuit unit 300 via the data bus, the output device selection signals (CS0 to CS5) are transmitted to the output port 400 shown in FIG. Flip-flop IC311
361 is input to the 1D to 8D terminals. On the other hand, the address signal is converted into an output device selection signal (CS0-CS5) by the I / O decode circuit,
00 and the corresponding flip-flop IC cl
Input to the ock terminal.

In this embodiment, the resistance arrays 221, 2
28 and 229, the impedance on the input terminal side is reduced, and the effects of external noise and the like on the output selection signal, the input selection signal generated by the device selection signal generation unit, and the gate signal generated by the gate signal generation unit 216 are suppressed. Have been. Further, in this embodiment, the data bus (OD,
D) is divided into two routes. This is due to the load capacitance between the CPU 201 and the flip-flop ICs 311 to 361, and may be a circuit configuration that does not need to be divided into two paths.

When CPU 201 writes data to input / output circuit section 300, a range address of PB0 / XCSIO0 terminal is designated, and an address signal is output from A0 to A4 terminals. The address signal is decoded by the NOR gate IC 222 and the decoder IC 223 into output device selection signals (CS0 to CS5) and output from the decoder IC 223. D0 of CPU 201
When the output signal of the D7 terminal is output to the input / output circuit unit 300 via the data bus, the output device selection signals (CS0 to CS5) are transmitted to the output port 400 shown in FIG. 361 1D
~ 8D terminal. On the other hand, the address signal is I / O
Output device selection signals (CS0 to CS0)
CS5), which is also transmitted to the output port 400 and input to the clock terminal of the corresponding flip-flop IC.

The input device selection signal (CS6) formed as a switching command signal is output to the NOR gate IC 222 when there is a predetermined address output from the A0 to A4 terminals and an output from the PB1 / XCSIO1 terminal. The decoder IC 224 is formed by the decoder IC 224.
4 to the buffer IC 371 (see FIG. 16). Also, in the gate signal generation unit 216, the oscillation clock output from the crystal oscillation module 204 and C
A gate signal (G) is generated based on the output signals of the XRD terminal and the XIORQ terminal of the PU 201, and this is also output to the buffer IC 371.

Next, the gate signal generator 216 of the I / O decode circuit 220 will be described. As shown in FIG. 16, when the CPU 201 as the receiving CPU reads data from an external device as a transmission source device connected to the input / output circuit unit 300 via the data bus, the data is output from the PB1 / XCSIO1 terminal as shown in FIG. And A0
A predetermined address signal is output from terminals A4.
The address signal is decoded by the NOR gate IC 222 and the decoder IC 224 into an input device selection signal (CS6), and is output from the decoder IC 224 to the buffer IC 371 as a switching unit. On the other hand, the CPU 201 sends a read signal from the XRD terminal and a read designation signal from the XIORQ terminal almost simultaneously with the output of the address signal, together with the input / output mode conversion of the data bus interface. The read signal and the read designation signal are NOR gate I
The signal is input to the NAND gate IC 226 and the flip-flop IC 227 from C225. NAND gate IC2
26 is a NOR gate IC 225 and a flip-flop IC
When the output of 227 becomes H, an active signal (L) is output to the buffer IC 371.

FIG. 17A shows the CPU shown in FIG.
A signal (0) obtained by inverting the clock pulse (CLKO) from the inverter 201 by the Schmitt trigger inverter IC 205, an output signal (1) from the NOR gate IC 225, an output signal (2) from the 2Q terminal of the flip-flop IC 226, and a signal from the NAND gate IC 226 6 is a timing chart showing the output signal (3) of FIG. In the initial state, since the 2D terminal of the flip-flop IC 227 is L, the signal output from the 2Q terminal is L even if the system clock is output from the CLKO terminal of the CPU 201. Therefore, the gate signal from the NAND gate IC 226 Is H. Therefore, the buffer IC 3
71 does not become active. When the CPU 201 executes the input mode, the outputs of the XRD terminal and the XIORQ terminal become active, the output signal (1) of the NOR gate IC 225 becomes H, and the 2D terminal of the flip-flop IC 227 becomes H. Here, when the rising of the output signal (0) of the Schmitt trigger inverter 205 is detected,
The H level is output from the 2Q terminal of the flip-flop IC 227 (2). As a result, as compared with the case where the XRD signal is directly input to the buffer IC 371, after the H level signal is input to the 2D terminal of the flip-flop IC 227, the flip-flop IC
227 signal input to only buffer IC371 difference t ₁ of time until the H-level signal is output delayed 2Q terminal, which is configured to at least more than a predetermined delay time (for example, 8 ns). The output signal (1) of the NOR gate IC 225 is supplied to the XRD terminal and the XI terminal.
Since the output from the ORQ terminal is kept at L while it is at L, the NAND gate IC 226 is connected to the XRD terminal and XIO
As long as the RQ terminal is active, the buffer IC 371
Becomes the input mode. In this embodiment, the output from the XRD terminal and the XIORQ terminal is the Schmitt trigger I
It outputs 2.5 pulses of the pulse output from C205, in other words, 2.5 clocks of the system clock continuously. When the CPU 201 switches to the output mode again, the XWR terminal or PB0 / X
The CSIO0 terminal is activated, the data bus is set to the output mode, and at the same time, the XRD and XIORQ terminals are deactivated. Thereby, the NAND gate IC2
Since the output from 26 becomes L, the buffer IC 371 is opened and no input is made. At this time, C of each flip-flop IC 311 to 361 of the output port 400 is
Since the PU side terminal has high impedance, the potential remaining in the bus interface of the CPU 201 in the transition state drops.

As shown in FIG. 17B, when a signal propagates through a circuit, a delay caused by a physical factor such as a propagation speed or a transient time until a signal recognition threshold is exceeded is caused. Since the time (t ₂ , t ₃ , t ₄ ) exists, the delay time t 1 is longer than that shown in FIG. In addition, due to the influence of the delay times (t ₂ , t ₃ , t ₄ ) caused by these physical elements, there is a possibility of operating without malfunction even without incorporating the delay circuit of the present invention. It depends on factors such as the situation and the environment. However, by providing the delay circuit as described above, it is possible to ensure a signal transmission delay time for avoiding malfunctions. Also, the gate signal generation unit 216
Is not provided with a delay circuit.
4 is provided on a signal line of a chip select signal (CS6) output from the buffer IC 371 to the buffer IC 371 by providing a D-type flip-flop IC or the like which operates in response to a system clock input.
The output of one CPU may be delayed.

The data bus stabilizing section 211 has a CPU 201
And the input / output circuit unit 300 to stabilize the signal on the data bus. The resistance array 203 reduces the noise entering the bus by reducing the impedance,
Is a command bus for each of the prize ball, lamp, display, and voice among the data buses divided into two paths (310 to 340).
Amplify the output signals (OD0 to OD7) of the bus (OD).

Next, the input / output circuit section 300 will be described. As shown in FIG. 3, the input / output circuit unit 300 includes a prize ball command output circuit unit 310, a lamp command output circuit unit 320, a display command output circuit unit 330, a voice command output circuit unit 340, a solenoid drive circuit unit 350, L
ED drive / information output circuit section 360 and second
An input circuit unit 370 is provided.

Of the above-described circuit sections 310 to 370, the prize ball command output circuit section 310, the lamp command output circuit section 320, the display command output circuit section 330, and the voice command output circuit section 340 all have the same circuit configuration. have. Therefore, in this embodiment, in order to avoid the drawing from being redundant, only the prize ball command output circuit unit 310 is shown (FIG. 10), and the other circuit units 320 to 340 are shown in parentheses in FIG. Only these are not shown. That is, each of the output circuit units 310 and 32
0, 330, and 340 are flip-flop ICs 31 respectively.
1, 321, 331, 341 and the buffer IC 312,
322, 332, 342, strobe signal line buffer ICs 313, 323, 333, 343 and connector 3
14, 324, 334, 344.

As shown in FIG. 9, the solenoid drive circuit unit 350 includes a flip-flop IC 351, three lamp solenoid drivers 352 to 354, and free terminals connected in parallel to the drain terminals of the lamp solenoid drivers. A wheel diode 355,
An input / output connector 356 is provided.

As shown in FIG. 10, the LED drive / information output circuit section 360 includes a flip-flop IC 361, a transistor array 362, and a lamp / solenoid driver 3.
63, a relay section 365, a power adjusting section 364, an input / output connector 356, and an information output connector 366, and the flip-flop IC 351 also plays a part of the configuration.
The relay 365 has two relays 367, 368, and the power adjuster 364 has ten resistors R4 to R13.

As shown in FIG. 11, the second external input circuit unit 370 includes a buffer IC 371 and a switch driver 37.
2, a resistor array 373, a power adjusting unit 374, and an input / output connector 356. The power adjustment unit 374 includes six resistors R21 to R26.

As shown in FIG. 12, the prize ball command output circuit section 310, the ramp command output circuit section 320,
Flip-flop IC 31 of display command output circuit 330, voice command output circuit 340, solenoid drive circuit 350, and LED drive / information output circuit 360
1, 321, 331, 341, 351, 361 constitute the output port circuit section 400. The output port circuit section 400 has six output ports.

Next, each circuit section 31 of the input / output circuit section 300
For 0 to 370, the function will be described. In the output port circuit section 400 shown in FIG. 9, the data (OD, D) from the main circuit section 200 and the device selection signals (CS0 to CS0)
CS5) and a clear signal (CLR). An external device is assigned to each port of the output port circuit unit 400. External devices include a prize ball device, a lamp device, a display device, a sound device, a solenoid device, and an LE device.
D apparatus, a hall computer, and the like. The data (OD) is input to the 1D to 8D terminals of the flip-flop ICs 311 to 361. Device selection signal (CS
0 to CS5) correspond to the corresponding flip-flop IC311.
Are input to the clock terminals 〜361. In the flip-flop ICs 311 to 361 selected by the device selection signals (CS0 to CS5), data (OD, D) from the main circuit unit 200 is input to the 1D to 8D terminals,
Data is output from the 1Q to 8Q terminals at the timing of the rising edge of the device selection signals (CS0 to CS5). In this output port circuit section 400,
When the power of the gaming machine 1 is turned on, the flip-flop ICs 311, 321, 331, 341 and 35 are supplied by the initialization reset signal from the general-purpose initialization reset signal unit 212 described above.
1, 361 are initialized.

Various command output circuit units 31 shown in FIG.
Reference numerals 0 to 340 denote circuit units for transmitting command data to the subsequent external devices such as the prize ball device, the lamp device, the display device, and the audio device. When the device selection signal is CS0 to CS3, the corresponding command is transmitted. Output circuit section 310
Command data output from the flip-flop ICs 311 to 341 are buffer ICs 312 and 32
2, 332, 342 are input to the A1 to A8 terminals, the drive capacity is enhanced, and the connectors 314 to 34 of each circuit are increased.
4 together with a strobe signal transmitted from a flip-flop IC 351 to be described later. In addition, each buffer IC
In addition, the output enable terminals G1 and G2 of the strobe signal line buffer are grounded, and their driving capabilities are enhanced. In addition, various command output circuit units 310 to 3
The control signal handled by 40 is a total of 9 bits of 8 bits of data and 1 bit of strobe, but the number of data bits may be changed depending on the connected prize ball device.

The solenoid drive circuit section 350 shown in FIG.
Is a circuit unit which is selected by the device selection signal (CS4) and drives a solenoid device which is an external device in accordance with a game state. In the solenoid drive circuit section 350, lamp / solenoid drivers 352 to 354 are associated with the solenoids. The flip-flop IC 351 is connected to the corresponding lamp from the 5Q to 7Q terminals.
The H level is input to the solenoid drivers 352 to 354. Further, when the input signal from the flip-flop IC 351 to the IN terminals of the lamp solenoid drivers 352 to 354 is at H level, the lamp solenoid drivers 352 to 354 drive the solenoid devices. Also,
The flip-flop IC 351 is connected to the command output circuit unit 3
It also functions as a strobe signal generator for transmitting a strobe signal to 10 to 340. That is, as shown in FIG. 10, the flip-flop IC 351 converts the output signals from the 1Q to 4Q terminals into the corresponding command output circuit sections 310 to 310.
340 strobe signal buffer ICs 313 to 343
Then, it is transmitted as a strobe signal.

The freewheel diode 355 circulates the sustained current when the output signals of the lamp solenoid drivers 352 to 354 switch from the H level to the L level by maintaining the load current during the high-speed switching operation. The lamp / solenoid driver 3
Instead of 52 to 354, for example, a transistor, FE
It is also possible to use T to drive the solenoid.

The LED drive / information output circuit section 360 shown in FIG. 10 is used for driving a design LED and outputting external information to a hall computer or the like. Normally, 2 bits are assigned to the symbol LED, and 6 bits are assigned to the external information output. When the device selection signal is CS5, data output from the flip-flop IC 361 of the LED drive / information output circuit unit 360 is input to the I1 to I8 terminals of the transistor array 362. If these inputs are I1 and I2, they are drive signals for the ordinary symbol LED based on the determination of the correctness of the CPU 201, and the transistor array 362 performs a switching operation and outputs (O1, O2) via the input / output connector 356. The connected LED is driven. Input I
Reference numerals 3 to I7 denote external information output signals such as symbol determination frequency information. The transistor array 362 performs a switching operation in the same manner and outputs from the input / output connector 356. The input I8 is also an external information output, which is switched by the transistor array 362 and output from the connection connector 366 via the relay of the relay section 365. The driving current to the LED and the signal current of the external output are supplied to the resistors R4 to R13 provided for each signal line of the protection resistor 364.
And an overcurrent is prevented from flowing.

In the ordinary symbol LED driving section, data (D0, D1) for informing the result of the ordinary symbol success / failure determination is provided by:
The signal is input to the I1 and I2 terminals of the transistor array 362. As a result, the transistor array 362 performs a switching operation and is output from the connector 356 to a normal symbol LED. The drive current to the ordinary design LED is limited by R4 and R5 of the protection resistor 374.

In the external information output unit, the CPU 201
When the external information data is input to the flip-flop IC 361 from the transistor array 362, the transistor array 362 performs a switching operation, and the symbol determination frequency information,
Gate information, starting port information, probability fluctuation (fluctuation reduction) information,
A plurality of types of information such as jackpot information and prize ball information are output. 8 of the flip-flop IC 351 from the CPU 201
When there is an input to the D terminal and the 8D terminal of the flip-flop IC 361, the transistor array 362 and the lamp / solenoid driver 363 perform a switching operation. Further, two types of signal forms are generated: an output signal at a voltage level using the transistor array 362 and the lamp / solenoid driver 363, and a contact output signal based on ON / OFF of a contact using the relay 365. Note that R6 to R13 of the protection resistor 374 limit the current to prevent occurrence of overcurrent.

The second input circuit section 370 shown in FIG.
D5), and the number of signal lines of the data buses (D0 to D5) to be used corresponds to the number of connected switches. When the detection signal is received by the connection connector 356, noise removal and voltage adjustment are performed by resistors R21 to R26 provided for each signal line of the power adjustment unit 374, and are input to the switch driver 372 (I1 to I2).
6). These signals are input to the buffer IC 371 from the output terminals O1 to O6 of the switch driver 372.

Here, when the reading of the switch state by the CPU 201 is instructed, the device selection signal generation unit 215
Is input to the G1 terminal to select the buffer IC 371, and the gate signal (G) instructing the inversion of the input / output direction of the data bus from the gate signal generation unit 216 is input to the G2 terminal. Is entered. The buffer IC 371 that has received the device selection signal (CS6) and the gate signal (G) amplifies the signal input from the switch driver 372 and inputs the amplified signal to the data bus (D). The output signal of the switch driver 372 is read into the buffer IC 371, amplified, and input to the CPU 201 via the data bus (D). The switch driver 372 has a short-circuit detecting function. When the switches connected to the I1 and I2 terminals are short-circuited, the output signal changes from the H level to the L level. Sent to
Upon receiving this, the CPU 201 executes error processing and stops game control. The power adjustment unit 374 performs noise removal and voltage adjustment on the input signal to the switch driver 372. Also, the resistance array 373
Reduces the impedance of the A1 to A8 terminals of the buffer IC 371 to suppress the influence of external noise and the like.

As described above, the receiving CPU 2 is connectable to one or a plurality of external devices as data transmission sources and receives data from the external devices via the data bus.
01, a buffer IC 371 for switching connection / disconnection between the CPU 201 and the external device based on a switching command signal from the CPU 201, and a buffer IC 371 provided separately from the CPU 201 and interposed between the CPU 201 and the buffer IC 371. The provision of the gate signal generation unit 216 that adjusts the transmission timing of the switching command signal from the CPU 201 to the buffer 371 can prevent data collision on the data bus in accordance with the characteristics of various electronic components. The data collision is caused by a difference between the transmission timing of the read or write signal from the CPU 201 and the transition completion timing of the read or writable state in the CPU 201, and the transmission timing of the switching command signal to the buffer 371 is caused. Is preferably simultaneous or subsequent to the transition completion timing of the read or write enabled state in the CPU 201. However, the transition completion timing of the read or write enable state in the CPU 201 is as follows.
Since it may be different depending on the type of the CPU 201 or the game state, the transmission timing may be before the transition completion timing. Therefore, as in the present embodiment, the buffer 371 of the switching command signal from the CPU 201
Signal generator 216 for adjusting the transmission timing to
Is provided, the transmission timing and the transition completion timing are positively and as close as possible, so that the CPU 201 can perform stable data reading or writing regardless of, for example, a difference in a game state or the like.

[Brief description of the drawings]

FIG. 1 is a front view of a gaming machine according to one embodiment of the present invention.

FIG. 2 is a rear view of the gaming machine.

FIG. 3 is a block diagram of a main control board.

FIG. 4 is a block diagram of the inside of a CPU used for a main control board.

FIG. 5 is a circuit diagram showing a connection state between a reset circuit unit and a CPU.

FIG. 6 is a circuit diagram showing a connection state between an I / O decode circuit unit and a CPU.

FIG. 7 is a circuit diagram showing a connection state between a first input circuit unit and a CPU.

FIG. 8 is a circuit diagram showing a command output circuit unit.

FIG. 9 is a circuit diagram showing a solenoid drive circuit unit.

FIG. 10 is a circuit diagram showing an LED drive / information output circuit unit.

FIG. 11 is a circuit diagram showing a second input circuit unit.

FIG. 12 is a circuit diagram showing an output port unit.

FIG. 13 is a circuit diagram showing a CPU reset circuit unit.

FIG. 14 is a timing chart showing a main power supply signal (1), a system reset signal (2), and a CPU initialization reset signal (3).

FIG. 15 is a timing chart showing a CPU initialization reset signal (5) and various signals (1) to (4) used for generation thereof.

FIG. 16 is a circuit diagram of an I / O decode circuit, its peripheral portion, and N main parts.

FIG. 17 is a timing chart showing an output signal of each unit of the gate signal generation unit.

[Explanation of symbols]

 1 gaming machine 100 main control board 201 CPU 216 gate signal generator 224 decoder IC 225 NOR gate IC 226 NAND gate IC 227 flip-flop IC 371 buffer IC

Claims (3)

[Claims] 1. A gaming machine comprising a control device for performing control related to a game, wherein the control device is connectable to one or a plurality of transmission source devices serving as data transmission sources, and a data bus is transmitted from the transmission source device. A receiving CPU that receives data via the data bus, and a connection / connection between the CPU and the transmission source device via the data bus.
A switching unit that switches disconnection based on a switching command signal from the receiving CPU, and a switching unit that is provided separately from the receiving CPU, and that is interposed between the receiving CPU and the switching unit, A gaming machine comprising: a switching command signal transmission timing adjusting means for adjusting a transmission timing of the switching command signal from the CPU to the switching unit. 2. The data bus is connected to a data input / output port of a receiving CPU, and the receiving CPU transmits and outputs a data signal to a data transmission destination via the data bus by switching to a data output mode. The switching command signal transmission timing adjusting means transmits the switching command signal to the switching unit with a predetermined delay from the input / output switching timing at which the receiving CPU switches from the data output mode to the data input mode. 2. The gaming machine according to claim 1, wherein 3. The receiving-side CPU outputs the switching command signal to the switching command signal transmission timing adjusting means substantially simultaneously with the input / output switching timing. 3. The gaming machine according to claim 2, wherein after receiving the switching command signal, the switching command signal is relayed to the switching unit with a predetermined delay.