JP2010246251A - Drive circuit of power conversion circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem that when an excessive current is applied to a power switching element Sw, a time lag occurs before taking countermeasures against the current. <P>SOLUTION: A serial connection body of a Zener diode 78 and a switching element 76 as a clamp circuit for clamping a gate voltage of the power switching element Sw is connected between a gate and an emitter of the power switching element Sw. The switching element 76 is operated to be turned on over a prescribed period from a switching start time point from an off-state to an on-state of the power switching element Sw. In this way, a gate voltage of the power switching element Sw is limited by the Zener diode 78 over the predetermined period from the switching start time point of the power switching element Sw to the on-state. The prescribed period is set so as to finish before the completion time of a mirror period. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a drive circuit for a power conversion circuit that drives on / off a voltage-controlled switching element included in the power conversion circuit.

  As this type of driving circuit, for example, as seen in Patent Document 1 below, a Zener diode and a transistor for clamping the gate voltage to a predetermined voltage are provided between the emitter and gate of an insulated gate bipolar transistor (IGBT). It is also proposed that the transistor is turned on when the collector current of the IGBT exceeds a specified value. Thereby, when the collector current of the IGBT becomes a value that may cause a decrease in the reliability thereof, the gate voltage can be lowered, and thus the collector current can be limited.

Japanese Patent No. 3558324

  By the way, there is a time lag after the collector current of the IGBT becomes equal to or higher than the specified value until the gate voltage is clamped by the Zener diode by actually turning on the transistor. Here, in order to shorten the time until the clamping process is performed, the transistor is turned on on the assumption that a current exceeding the specified value has flowed due to noise even though the current exceeding the specified value does not actually flow. Malfunction is likely to occur. On the other hand, when an element is selected as an IGBT whose reliability does not decrease even if an excessive current flows during the period until the clamping process is performed, there is a problem that the element size of the IGBT increases.

  The present invention has been made in order to solve the above-described problems, and an object of the present invention is to more appropriately suppress the occurrence of an excessive current flowing through a voltage-controlled switching element included in a power conversion circuit. It is to provide a drive circuit for a power conversion circuit.

  Hereinafter, means for solving the above-described problems and the operation and effects thereof will be described.

  According to the first aspect of the present invention, the detected value of the current flowing between the input terminal and the output terminal of the voltage-controlled switching element provided in the power conversion circuit is input, and the switching element is controlled when the current exceeds a specified value. In the drive circuit of the power conversion circuit, including the limiting unit that limits the voltage applied to the conduction control terminal of the switching element to the reference voltage while maintaining the on state, the limiting unit is turned on from the off state of the switching element. It has a function of limiting a voltage applied to the conduction control terminal to a reference voltage over a specified period in which a length from the start of switching to a state is determined.

  In the above invention, since the voltage applied to the conduction control terminal over the specified period is limited to the reference voltage, it is preferable that the current flowing through the switching element becomes excessive when the switching element is switched to the on state. Can be suppressed. When the current exceeding the specified value actually flows through the switching element, the voltage at the conduction control terminal is limited to the reference voltage based on the input of the detected current value even after the specified period has elapsed. be able to.

  The invention according to claim 2 is characterized in that, in the invention according to claim 1, the prescribed period is a period from the start time of switching to the ON state to a time point before the completion of the mirror period.

  When switching the switching element from the off state to the on state, the voltage of the conduction control terminal normally rises once and then rises again after a mirror period that hardly changes at a constant value. And the voltage of the conduction control terminal in the mirror period does not take a very high value unless an excessive current flows through the switching element. For this reason, by setting the specified period to end before the end of the mirror period, it is possible to suitably avoid a situation where the voltage of the conduction control terminal exceeds the reference voltage in a situation where excessive current does not flow through the switching element. it can.

  The invention according to claim 3 is the invention according to claim 1 or 2, wherein the specified period is equal to or longer than a time required for the limiting means to start limiting to the reference voltage in response to the detected value of the current. It has the length of.

  In the above invention, when the current flowing through the switching element is equal to or greater than the specified value, the voltage limitation of the conduction control terminal based on the input of the detected value of the current flowing through the switching element is started within the specified period. For this reason, it is possible to continuously limit the voltage of the conduction control terminal from the start of switching to the ON state of the switching element until the end of the specified period. For this reason, the current flowing through the switching element can be limited to the maximum current determined by the reference voltage.

  The invention according to claim 4 is the invention according to any one of claims 1 to 3, wherein the limiting means includes a Zener diode provided between the conduction control terminal and the output terminal, the conduction control terminal, and A means for opening and closing an electrical path provided between the output terminals and including the Zener diode, and a means for opening and closing the electrical path with an ON operation command of the switching element as an input over the specified period. And a means for closing.

  According to a fifth aspect of the present invention, in the invention according to any one of the first to fourth aspects, the limiting means receives a detection value of a current flowing through the switching element and compares the detection value with a threshold value. And a detection means for determining whether or not the current is greater than or equal to the specified value, and a detected value of the voltage of the conduction control terminal of the switching element as an input, and the detected value of the current becomes the voltage of the conduction control terminal. And a removing means for removing an influence exerted on the comparison by the judging means.

  When the means for detecting the current flowing through the switching element is constituted by means for detecting the current actually flowing through the switching element or a part thereof directly instead of directly detecting the current, a detected value of the current Tends to depend on the voltage of the conduction control terminal. In this case, the comparison result between the detected current value and the threshold value may vary depending on the voltage applied to the conduction control terminal of the switching element. In this regard, in the above invention, whether or not the current flowing through the switching element becomes equal to or higher than the specified value by removing the fluctuation of the comparison result due to the fluctuation of the detected value depending on the voltage applied to the conduction control terminal. Can be determined with high accuracy.

  The invention according to claim 6 is the invention according to any one of claims 1 to 5, wherein the power conversion circuit includes a series connection body of a high potential side switching element and a low potential side switching element, and the conduction The switching element to which the limiting means is connected to the control terminal is at least one of the high potential side switching element and the low potential side switching element.

  In the above invention, since the high-potential side switching element and the low-potential side switching element are connected in series, the current flowing between the input terminal and the output terminal of the switching element may be limited in the event of an abnormal current flowing through them. desired. For this reason, the merit of providing the regulation means is particularly great.

  The invention according to claim 7 is the invention according to claim 6, wherein free wheel diodes are respectively connected between the input terminal and the output terminal of the high potential side switching element and the low potential side switching element, The high-potential-side switching element and the low-potential-side switching element are instructed to be turned on / off by complementary signals that are alternately commanded to be turned on, and are freewheels corresponding to the switching elements to which the limiting means is connected. When it is determined that a current flows through the diode, it further comprises invalidating means for invalidating the restriction by the restriction means.

  When on / off is instructed by a complementary signal as described above, wasteful power consumption tends to be particularly large due to restriction processing to the reference voltage by the restriction means when current flows through the freewheeling diode. This is because when the current flows through the freewheeling diode, the voltage at the conduction control terminal is considered to quickly exceed the reference voltage. In the above invention, in view of this point, it is possible to suitably suppress the waste of power by the limiting unit by including the invalidating unit.

  The invention according to claim 8 is the invention according to claim 7, wherein the switching element and the free wheel diode are provided on the same semiconductor substrate, and it is determined that a current flows through the free wheel diode. In the case, it further comprises a stopping means for stopping voltage application to the conduction control terminal of the switching element, and the invalidating means is constituted by the stopping means.

  When the switching element and the free wheel diode are provided on the same semiconductor substrate, the free wheel is used when the power switching element connected in reverse parallel to the free wheel diode when the current is flowing is turned on. The power loss of the diode increases. In the above invention, in view of this point, the conduction loss can be reduced by providing the stopping means.

  Furthermore, the increase in the number of parts can be suppressed by configuring the invalidating means by a stopping means.

1 is a system configuration diagram according to a first embodiment. FIG. Sectional drawing and side view which show the structure of IGBT and free wheel diode concerning the embodiment. The circuit diagram which shows the circuit structure of the drive unit concerning the embodiment. The time chart which illustrates the protection aspect from the overcurrent concerning the embodiment. The figure which shows the relationship between the voltage drop amount of shunt resistance by the output current of a sense terminal, and collector current. The circuit diagram which shows the circuit structure of the drive unit concerning 2nd Embodiment.

(First embodiment)
Hereinafter, a first embodiment in which a drive circuit of a power conversion circuit according to the present invention is applied to a hybrid vehicle will be described with reference to the drawings.

  FIG. 1 shows the system configuration of this embodiment. As shown in the figure, a motor generator 10 as an in-vehicle main machine is connected to a high voltage battery 12 via an inverter IV and a converter CV. The inverter IV is configured by connecting three series-connected bodies of a high-potential side power switching element Swp and a low-potential side power switching element Swn in parallel. Connection points of these power switching elements Swp and Swn are connected to respective phases of the motor generator 10. Further, converter CV connects capacitor C, a series connection body of power switching element Swp on the high potential side and power switching element Swn on the low potential side, and a connection point between these power switching elements Swp and Swn and high voltage battery 12. And a reactor L.

  Between the input / output terminals (between the collector and the emitter) of the high potential side power switching element Swp and the low potential side power switching element Swn, there is a high potential side freewheel diode FDp and a low potential side freewheel diode. The cathode and anode of FDn are connected.

  The drive unit DU is connected to the conduction control terminals (gates) of the power switching elements Swp and Swn constituting the inverter IV. Thereby, the power switching elements Swp and Swn are driven by the control device 16 using the low voltage battery 14 as a power source via the drive unit DU. The control device 16 controls operation signals gup, gvp, and gwp for operating the power switching elements Swp for the U phase, V phase, and W phase of the inverter IV based on detection values of various sensors (not shown), and power switching. Operation signals gn, gvn, and gwn for operating the element Swn are generated and output. Further, operation signals gcp and gcn for operating the power switching elements Swp and Swn of the converter CV are generated and output. Thereby, the power switching elements Swp and Swn are operated by the control device 16 via the drive unit DU. The high-potential side operation signals gup, gvp, gwp, and gcp and the low-potential side operation signals gun, gvn, gwn, and gcn are respectively divided into a high-potential side switching element Swp and a low-potential side switching element. Swn is driven complementary to each other. That is, during the period when one of the operation signals is a signal for turning on, the other operation signal is a signal for turning off.

  The high voltage system including the inverter IV and the converter CV and the low pressure system including the control device 16 are insulated by an insulating means such as a photocoupler (not shown), and the operation signal is transmitted to the high pressure system via the insulating means. Is output.

  Each of the power switching elements Swp and Swn is a switching element that has an input terminal and an output terminal that are uniquely defined and prevents a current from flowing from the output terminal to the input terminal. Specifically, these are constituted by insulated gate bipolar transistors (IGBT). The power switching elements Swp and Swn include a sense terminal ST that outputs a minute current having a correlation with a current flowing between the input terminal and the output terminal and a current flowing through the freewheel diodes FDp and FDn. This function of the sense terminal ST is realized because an IGBT with a built-in diode is used. That is, in this embodiment, the high-potential side power switching element Swp and the high-potential side freewheel diode FDp are formed adjacent to each other on the same semiconductor substrate. The free wheel diodes FDn on the side are formed adjacent to the same semiconductor substrate.

  FIG. 2A shows a cross-sectional configuration of the power switching element Swp (Swn) and the free wheel diode FDp (FDn) according to the present embodiment. In the following description, the power switching elements Swp and Swn are collectively referred to as the power switching element Sw, and the free wheel diodes FDp and FDn are collectively referred to as the free wheel diode FD.

  As illustrated, the semiconductor substrate 20 is formed with an IGBT region and a diode region. A region extending from the main surface side to the back surface side of the semiconductor substrate 20 is an N-type region 22 whose conductivity type is N-type. A P-type region 24 having a P-type conductivity is formed in the surface layer portion on the main surface side of the semiconductor substrate 20, and the N-type having a concentration higher than that of the N-type region 22 in the P-type region 24. An N-type region 26 having the conductivity type is formed. The P-type region 24 and the N-type region 26 are connected to an IGBT emitter terminal E and a diode anode terminal. A gate electrode 30 is formed on the P-type region 24 and the N-type region 26 via a gate oxide film 28.

  On the other hand, an N-type region 36 and a P-type region 34 having a concentration higher than that of the N-type region 22 are provided side by side on the back surface side of the semiconductor substrate 20. Here, the P-type region 34 constitutes a collector region of the IGBT, and the N-type region 36 constitutes a cathode region of the diode. An N-type region 32 having a concentration lower than that of the N-type region 22 is formed between the P-type region 34 and the N-type region 36 and the N-type region 22.

  FIG. 2B is a plan view schematically showing the main surface side of the semiconductor substrate 20. As shown in the drawing, most of the main surface side is an emitter region, and a gate region and a sense electrode 38 are formed as a region smaller than this. Here, the actual area of the sense electrode 38 is about one thousandth of the area of the emitter region, so that a very small current is correlated with the current flowing through the IGBT and the free wheel diode. Can be output.

  FIG. 3 shows a circuit configuration of the drive unit DU.

  As shown in the figure, the power supply 40 is connected to the gate of the power switching element Sw via a P-channel MOS transistor (charging switching element 42) and a charging resistor 44 for adjusting the charging speed of the gate. Has been. The gate of the power switching element Sw is connected to the emitter E of the power switching element Sw via a discharging resistor 46 for adjusting the discharge rate of the gate and an N-channel MOS transistor (discharging switching element 48). Yes.

  The drive control circuit 50 receives the operation signal g (general notation of the operation signals gup, gun, gvp, gvn, gwp, gwn, gcp, gcn) input to the drive unit DU via an insulating means such as a photocoupler (not shown). Based on the above, the power switching element Sw is driven by complementarily turning on and off the charging switching element 42 and the discharging switching element 48. That is, when the operation signal g becomes logic “H” to indicate that the power switching element Sw is to be turned on, the charging switching element 42 is turned on and the discharging switching element 48 is turned off. Thus, a positive charge is charged to the gate of the power switching element Sw. Further, when the operation signal g becomes logic “L” to instruct the power switching element Sw to be turned off, the charging switching element 42 is turned off and the discharging switching element 48 is turned on. Thus, positive charges are discharged from the gate of the power switching element Sw.

  A shunt resistor 52 is connected between the emitter E and the sense terminal ST of the power switching element Sw. The voltage drop amount of the shunt resistor 52 due to the minute current output from the sense terminal ST is converted into a voltage by the inverting amplifier circuit 54 and then applied to the inverting input terminal of the comparator 56. Here, the inverting amplification circuit 54 fixes the polarity of the voltage applied to the inverting input terminal of the comparator 56 regardless of whether a current flows through the power switching element Sw or a free wheel diode FD. Is. Here, as the inverting amplifier circuit 54, a circuit in which a positive voltage is applied to the non-inverting input terminal of the operational amplifier based on the emitter potential of the power switching element Sw is illustrated. The output voltage of the inverting amplifier circuit 54 becomes larger as the input voltage is smaller (negative and the absolute value is larger).

  The voltage VthL of the reference power supply 58 is applied to the non-inverting input terminal of the comparator 56. Here, the reference power supply 58 is for applying a voltage having a higher potential than the emitter potential of the power switching element Sw to the non-inverting input terminal. As a result, when the current flowing through the freewheel diode FD exceeds a specified value, a stop signal SD for forcibly stopping voltage application from the comparator 56 to the drive control circuit 50 to the gate of the power switching element Sw is generated. Is output. In the drive control circuit 50, when the stop signal SD is input, the power switching element Sw is turned off regardless of the value of the operation signal g. This is in view of the fact that the power loss of the freewheel diode FD is increased by applying a voltage to the gate of the power switching element Sw when a current flows through the freewheel diode FD. That is, the power loss of the free wheel diode FD can be reduced by forcibly turning off the power switching element Sw when a current flows through the free wheel diode FD.

  Further, the output signal of the inverting amplifier circuit 54 becomes an input signal of the inverting input terminal of the comparator 60. The reference voltage VthH of the reference power supply 62 is applied to the non-inverting input terminal of the comparator 60. As a result, the current flowing through the power switching element Sw becomes equal to or greater than the threshold value, so that the output of the comparator 60 is inverted from logic “L” to logic “H”. The logic “H” signal from the comparator 60 is taken into the delay 64. The delay 64 outputs a logic “H” signal to the gate of the soft shut-off switching element 66 so that the power switching element Sw is forcibly turned off when the input signal becomes logic “H” for a predetermined time. And a stop signal AE to the drive control circuit 50. Here, the stop signal AE is a signal for stopping driving of the charging switching element 42 and the discharging switching element 48 by the drive control circuit 50.

  The soft cutoff switching element 66 has one terminal connected to the emitter E of the power switching element Sw, and the other terminal connected to the power switching via the soft cutoff resistor 68 and the discharge resistor 46. Connected to the gate of the element Sw. As a result, the state in which the current flowing through the power switching element Sw is equal to or greater than the threshold value continues for a predetermined time or longer, so that the soft cutoff switching element 66 is turned on, and the soft cutoff resistor 68 and the discharge resistor 46 are connected. Thus, the charge of the gate of the power switching element Sw is discharged. Here, the soft blocking resistor 68 is used to increase the resistance value of the discharge path. This is because, under a situation where the collector current is excessive, if the speed at which the power switching element Sw is switched from the on state to the off state, in other words, the cutoff speed between the collector and the emitter is increased, the surge becomes excessive. This is in view of the fear. For this reason, in a situation where the collector current is determined to be equal to or greater than the threshold, the gate of the power switching element Sw is connected by a path having a resistance value larger than that of the discharge path including the discharge resistor 46 and the discharge switching element 48. Discharge.

  As the drive limiting means for such power switching element Sw, the present embodiment includes means for limiting the gate voltage of the power switching element Sw to a reference voltage larger than zero in addition to the means for performing the soft shut-off process. This is configured by providing a series connection body of an N-channel MOS transistor (switching element 76) and a Zener diode 78 between the collector and emitter of the power switching element Sw. As a result, when the switching element 76 is turned on, the gate voltage of the power switching element Sw can be limited to the breakdown voltage (clamp voltage) of the Zener diode 78.

  The switching element 76 is basically turned on based on the output of the comparator 60 when the current flowing through the power switching element Sw exceeds a threshold value. However, in the present embodiment, the gate voltage is increased by turning on the switching element 76 over a specified period in which the length from the start point of switching of the power switching element Sw from the off state to the on state is determined. It is also used for processing that restricts. This is realized by the following circuit configuration.

  The drive signal for the switching element 42 output from the drive control circuit 50 is input to the filter 70. The filter 70 has a delay time corresponding to the time specified by the specified period. This time is shorter than the time determined by the delay 64. In particular, in the present embodiment, the time determined by the specified period is a time within the time from the start of switching of the power switching element Sw from the off state to the on state until the mirror period ends. The filter 70 is constituted by, for example, a first-order lag filter.

  An OR circuit 72 generates a logical sum signal of the output of the filter 70 and the output of the comparator 60. The AND circuit 74 generates a logical product signal of the logically inverted signal of the drive signal by the inverter 69 and the output signal of the OR circuit 72. The output signal of the AND circuit 74 is applied to the conduction control terminal (gate) of the switching element 76.

  FIG. 4 shows an aspect of the gate voltage limiting process by the above circuit. Specifically, FIG. 4A shows the transition of the operation signal g, FIG. 4B shows the transition of the gate voltage Vge, and FIG. 4C shows the current (collector current) flowing through the power switching element Sw. Ic) is shown, and FIG. 4D shows the change of the operation mode of the clamp circuit including the Zener diode 78.

  Here, Case A shows a normal time when no excessive current flows through the power switching element Sw. In this case, when a command to turn on the power switching element Sw is issued, the gate voltage increases, and the clamp circuit is switched to the off state before the completion of the mirror period (time t1). Here, since the gate voltage in the mirror period is equal to or lower than the clamp voltage Vcr (breakdown voltage of the Zener diode 78) by the clamp circuit, the presence or absence of the operation of the clamp circuit affects the rise of the gate voltage of the power switching element Sw. Does not reach. Further, no current flows through the Zener diode 78, and there is no power consumption.

  On the other hand, Case B shows an abnormal time when an excessive current flows through the power switching element Sw, for example, a through current flows through the pair of power switching elements Swp and Swn. In this case, since the gate voltage increases as the current flowing through the power switching element Sw increases, the voltage in the mirror period is also clamped by the clamp voltage Vcr. As a result, the current flowing through the power switching element Sw is limited by the clamp voltage Vcr. Since the current flowing through the power switching element Sw is not less than the threshold value Ith determined by the reference voltage VthH, the gate voltage is limited to the clamp voltage Vcr even after the period determined by the filter 70 has elapsed.

  On the other hand, Case C shows a conventional example in which the clamp circuit is driven only by the output signal of the comparator 60. In this case, when an excessive current flows through the power switching element Sw, the gate voltage of the power switching element Sw once rises above the clamp voltage Vcr. Thereafter, the comparator 60 detects that the current flowing through the power switching element Sw becomes equal to or greater than the threshold value Ith, and the clamp circuit is driven based on this, whereby the gate voltage is limited to the clamp voltage Vcr, and the power switching element Sw is The flowing current is also limited.

  As described above, in the present embodiment, by driving the clamp circuit for a specified period from the time when the power switching element Sw is switched from the off state to the on state, the power switching element Sw is switched to the on state. An excessive current can be suitably avoided. On the other hand, in the case C that does not have such a configuration, an excessive current flows through the power switching element Sw. Therefore, it is necessary to use a rated one that can withstand this, and as a result, the power switching element Sw is increased in size. Invite. In particular, there is a demand for increasing the gate voltage from the viewpoint of reducing the power loss when the power switching element Sw is in the on state. When this demand is followed, the power switching element during the period until the clamp circuit operates in response to an overcurrent. The current flowing through Sw tends to be very large. For this reason, the larger the power switching element Sw is, the more the power switching element Sw is complied with.

  Although it may be possible to shorten the time required for the clamp circuit to operate in response to an overcurrent, in this case, it is necessary to make the circuit very fast.

  According to the embodiment described in detail above, the following effects can be obtained.

  (1) The voltage applied to the gate is limited to the clamp voltage Vcr over a specified period in which the length from the start of switching from the off state to the on state of the power switching element Sw is determined. Thereby, it can suppress suitably that the electric current which flows into power switching element Sw by switching power switching element Sw to an ON state becomes excessive.

  (2) The specified period is a period from the start time of switching to the ON state to a time point before the completion of the mirror period. As a result, a situation in which the gate voltage exceeds the clamp voltage Vcr can be suitably avoided in a situation where no excessive current flows through the power switching element Sw.

  (3) The time required to start limiting the clamp voltage Vcr to the clamp voltage Vcr in response to the detected value of the current flowing through the power switching element Sw (the switching element 76 is operated based on the output signal of the comparator 60). The time until it became possible). As a result, the gate voltage can be continuously limited from the start time of switching the power switching element Sw to the ON state to the time point exceeding the end time of the specified period.

  (4) The power switching element Swp and the power switching element Swn are connected in series. In this case, since the current flowing through the power switching element Sw tends to be particularly large at the time of an abnormality in which the current passing through them flows, the merit of starting the clamp circuit is particularly great when the power switching element is turned on.

  (5) When it is determined that a current flows through the freewheeling diode FD, voltage application to the gate of the power switching element Sw is stopped. Thereby, the power loss of the free wheel diode FD can be reduced. Further, when a current flows through the free wheel diode FD, the gate voltage of the power switching element Sw quickly exceeds the clamp voltage Vcr. For this reason, when the voltage application to the gate of the power switching element Sw is not stopped, it is considered that power is wasted by the clamp circuit. In this respect, in the present embodiment, when it is determined that a current flows through the free wheel diode FD, such a situation can be avoided by stopping the voltage application to the gate of the power switching element Sw.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to the drawings with a focus on differences from the first embodiment.

  In the present embodiment, the reference voltage VthH that is compared with the amount of voltage drop by the shunt resistor 52 to determine whether or not a current equal to or greater than the threshold flows through the power switching element Sw is variable according to the gate voltage of the power switching element Sw. Set. This is because the minute current output from the sense terminal ST depends on the gate voltage Vge of the power switching element Sw as shown in FIG. That is, due to the gate voltage dependency of the minute current, a determination error may occur when it is determined whether or not a current exceeding the threshold value flows through the power switching element Sw based on a comparison between the voltage drop amount and a fixed value. In order to avoid such a situation, the reference voltage VthH to be compared with the amount of voltage drop is variably set to compensate for the gate voltage dependence of the minute current in the above determination.

  FIG. 6 shows a circuit configuration of the drive unit DU according to the present embodiment. In FIG. 6, members corresponding to those shown in FIG. 3 are given the same reference numerals for convenience.

  As shown in the figure, the reference power source 62 variably sets the reference voltage VrefH with the gate voltage of the power switching element Sw as an input. Specifically, the reference voltage VrefH is increased as the gate voltage is higher.

  According to the present embodiment described above, the following effects can be obtained in addition to the above-described effects of the first embodiment.

  (6) The reference voltage VthH to be compared with the voltage drop amount corresponding to the minute current output from the sense terminal ST is variably set according to the gate voltage. Thereby, it can be avoided that the comparison result between the current flowing through the power switching element Sw and the threshold value fluctuates due to the minute current fluctuating depending on the gate voltage.

(Other embodiments)
Each of the above embodiments may be modified as follows.

  -When determining whether or not the current flowing through the power switching element Sw is equal to or higher than a specified value based on the comparison between the detected value of the current flowing through the power switching element Sw and the threshold value, the dependence of the detected value on the gate voltage is removed. The method is not limited to the method of variably setting the threshold according to the gate voltage, as exemplified in the second embodiment. For example, the detection value may be corrected such that the resistance value of the shunt resistor (shunt resistor 52) is variably set according to the gate voltage.

  In each of the above embodiments, the switching element 76 is connected to the anode side of the Zener diode 78, but may be connected to the cathode side.

  A limiting means for limiting the voltage applied to the conduction control terminal of the power switching element Sw to the reference voltage while maintaining the power switching element Sw in an on state is configured to include a Zener diode 78 and a switching element 76. Not limited to things. For example, instead of the Zener diode 78, a series connection body of a plurality of diodes having the gate side of the power switching element Sw as an anode may be used.

  In each of the above embodiments, the drive signal of the switching element 42 for opening and closing the electrical path between the gate of the power switching element Sw and the power supply 40 is input to the filter 70, but the present invention is not limited to this. For example, the operation signal g input to the drive control circuit 50 may be used.

  In each of the above embodiments, the high-potential side power switching element Swp and the low-potential side power switching element Swn are driven complementarily, but the present invention is not limited to this. When a current flows through the freewheeling diode FD, if the operation signal of the power switching element Sw connected in reverse parallel to this corresponds to the OFF command, not only power consumption by the Zener diode 78 but also power switching Power consumption due to charging of the gate of the element Sw can also be avoided.

  In each of the above embodiments, the output of the inverting amplifier circuit 54 is applied to the inverting input terminal of the comparator 60. However, the present invention is not limited to this. For example, the voltage at the connection point between the shunt resistor 52 and the sense terminal ST may be applied to the non-inverting input terminal of the comparator 60 and the reference voltage may be applied to the inverting input terminal.

  The invalidating means for invalidating the clamping process of the gate voltage of the power switching element Sw by the Zener diode 78 when a current flows through the freewheel diode FD is not limited to the one exemplified in the above embodiments. For example, when the power switching element Sw and the freewheeling diode FD are configured in separate chips and it is determined that a current flows through the freewheeling diode FD, the voltage application to the gate of the power switching element Sw is stopped. Even when the means is not provided, providing the invalidating means is effective in avoiding unnecessary power consumption by the Zener diode 78. However, even in this case, configuring the invalidating means as a stopping means for stopping the voltage application to the gate of the power switching element Sw avoids unnecessary power consumption due to charging of the gate of the power switching element Sw. It is effective in doing.

  The means for detecting the current flowing through the power switching element Sw is not limited to detecting the voltage drop amount at the shunt resistor due to the minute current output from the sense terminal ST. For example, the voltage between the input terminal and the output terminal of the power switching element Sw may be detected. In this case, the detected voltage is a parameter having a correlation with the current flowing between the input terminal and the output terminal of the power switching element Sw. However, even in this case, the detected voltage changes depending on the voltage applied to the gate of the power switching element Sw. Therefore, as in the second embodiment, the power switching element It is effective to remove this voltage dependency when determining whether or not a current exceeding the specified value flows through Sw.

  The configuration of the drive unit DU is not limited to that exemplified in the above embodiments. For example, the charging resistor 44 and the discharging resistor 46 may be the same. Further, the electrical path for the soft cutoff process may be a path that bypasses the discharging resistor 46.

  The power conversion circuit is not limited to the inverter IV and the converter CV as a boost converter. For example, a step-down converter that steps down the voltage of the high voltage battery 12 and applies it to the low voltage battery 14 may be used.

  -As a power converter circuit, not only what is mounted in a hybrid vehicle, For example, you may mount in an electric vehicle.

  60 ... Comparator (constituent element of one embodiment of limiting means), 76 ... Switching element (constituent element of one embodiment of limiting means), 78 ... Zener diode (constituent element of one embodiment of limiting means), Sw ... Power Switching element.

Claims (8)

The detected value of the current flowing between the input terminal and the output terminal of the voltage control type switching element provided in the power conversion circuit is used as an input, and while the switching element is maintained in the ON state when the current is equal to or higher than a specified value, In the drive circuit of the power conversion circuit comprising limiting means for limiting the voltage applied to the conduction control terminal of the switching element to the reference voltage,
The limiting unit is configured to limit the voltage applied to the conduction control terminal to a reference voltage over a specified period in which the length from the start of switching from the OFF state to the ON state of the switching element is determined. A drive circuit for a power conversion circuit, comprising:   2. The drive circuit for a power conversion circuit according to claim 1, wherein the specified period is a period from a start time of switching to the ON state to a time before completion of the mirror period.   3. The electric power according to claim 1, wherein the specified period has a length longer than a time required for the limiting unit to start limiting to the reference voltage in response to the detected value of the current. Drive circuit for conversion circuit.   The restricting means includes a Zener diode provided between the conduction control terminal and the output terminal, and a means for opening and closing an electric path provided between the conduction control terminal and the output terminal and including the Zener diode. 4. The apparatus according to claim 1, further comprising: means for inputting an on-operation command for the switching element, and closing the means for opening and closing the electrical path over the specified period. 5. A drive circuit of the power conversion circuit described.   The limiting means receives as input a detection value of the current flowing through the switching element, and determines whether or not the current exceeds the specified value based on a comparison between the detection value and a threshold value; and the switching element And a removal means for removing an influence exerted on the comparison by the determination means when the detected value of the current depends on the voltage of the conduction control terminal. The drive circuit for a power conversion circuit according to claim 1, wherein the drive circuit is a power conversion circuit. The power conversion circuit includes a series connection body of a high potential side switching element and a low potential side switching element,
The switching element to which the restriction means is connected to the conduction control terminal is at least one of the high-potential side switching element and the low-potential side switching element. A drive circuit of the power conversion circuit described. Free wheel diodes are connected between the input terminal and the output terminal of the high potential side switching element and the low potential side switching element,
The high-potential side switching element and the low-potential side switching element are instructed to be turned on and off by complementary signals that are alternately commanded to be turned on.
7. The method according to claim 6, further comprising: a disabling unit for disabling the limitation by the limiting unit when it is determined that a current flows through a freewheeling diode corresponding to the switching element to which the limiting unit is connected. Drive circuit for power conversion circuit. The switching element and the free wheel diode are provided on the same semiconductor substrate,
When it is determined that a current flows through the freewheeling diode, it further comprises stop means for stopping voltage application to the conduction control terminal of the switching element,
8. The drive circuit for a power conversion circuit according to claim 7, wherein the invalidating means is constituted by the stopping means.

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