JP2010245438A - Thin film transistor, display device, and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor having highly reliable, high-performance transistor characteristics, a display device, and a manufacturing method for the transistor and display device. <P>SOLUTION: The thin film transistor includes a gate electrode 2 formed on a substrate 1, a gate insulating film 3 which includes a first gate insulating film 31 made of an SiN film and a second gate insulating film 33 made of an SiN oxide layer formed on the first gate insulating film 31 and covers the gate electrode 2, a semiconductor layer 4 which is disposed facing to the gate electrode 2 via the gate insulating film 3 and at least has a microcrystal semiconductor film (first semiconductor layer 41) formed on an interface in contact with the second gate insulating film 33, and a source electrode 7 and a drain electrode 8 formed on the semiconductor layer 4 via an Ohmic contact film 6. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a thin film transistor, a display device, and a manufacturing method thereof, and particularly relates to a thin film transistor including a microcrystalline semiconductor film crystallized by laser annealing, a display device, and a manufacturing method thereof.

  Liquid crystal display (LCD), one of the thin panels, is widely used for monitors for personal computers, personal digital assistants, and in-car monitors such as car navigation systems, taking advantage of low power consumption and small size and light weight. It is used. In recent years, LCDs have been widely used for TV applications instead of CRTs. Also, organic EL (Electro-Luminescence) display devices have been used as next-generation thin panel devices. Organic EL display devices are self-luminous, have a wide viewing angle, high contrast, and high-speed response, and take advantage of features that LCD does not have. The problem of being difficult has been cleared.

  A thin film transistor (hereinafter referred to as TFT: Thin Film Transistor) used in such a display device often employs a MOS structure using a semiconductor film. The structure of the TFT is generally known as an inverted staggered type (bottom gate type) or top gate type, and the semiconductor film used for the TFT is mainly amorphous silicon, which is an amorphous semiconductor film.

  A TFT using amorphous silicon as a semiconductor layer has a disadvantage that a threshold voltage changes with time. This is due to the injection and trapping of electrons from the amorphous silicon into the gate insulating film and the increase in the density of localized states in the amorphous silicon film. Therefore, in order to compensate for this drawback, circuit design is performed in which the amount of change in the threshold voltage with time is estimated in advance. A TFT using amorphous silicon can be used only for switching a pixel portion and cannot be used for a peripheral circuit such as a gate driver circuit. Therefore, a gate driver IC is externally attached to the gate driver circuit. Therefore, there is a problem that the frame of the display device inevitably increases.

  In order to solve such a problem, a gate driver circuit has been formed by a TFT using a crystalline semiconductor film such as a microcrystalline semiconductor film or a polycrystalline semiconductor film as a semiconductor layer. Since the crystalline semiconductor film has a smaller density of defect states than the amorphous semiconductor film, the threshold voltage does not change with time. Or even if it occurs, the change with time is small.

For example, Patent Document 1 discloses a technique for selectively using TFTs for each application by forming TFTs using an amorphous semiconductor film in a pixel region and forming TFTs using a polycrystalline semiconductor film in a peripheral circuit region. ing. In Patent Document 1, after a SiN film is formed as a gate insulating film, a SiO ₂ film or a SiON film is selectively formed only on the TFT of the peripheral circuit by laser irradiation.

However, in the structure of Patent Document 1, a change in the threshold voltage over time occurs in the TFT in the pixel region using the amorphous semiconductor film. In addition, since the SiO ₂ film or the SiON film is selectively formed by laser irradiation, the operation of aligning the TFT portion in the peripheral circuit region in the substrate surface with the laser irradiation position must be repeated, and the processing time is reduced. Cost. Therefore, there is a risk that productivity may be reduced.

  Therefore, if the TFT using the crystalline semiconductor film is formed in both the pixel region and the peripheral circuit region, the above problem can be avoided. Recently, in particular, a microcrystalline silicon TFT having a stacked structure in which a microcrystalline semiconductor film is formed on a semiconductor film in contact with a gate insulating film and an amorphous semiconductor film is formed thereon has been used. Hereinafter, a conventional method for producing a microcrystalline silicon TFT will be described with reference to the cross-sectional structures shown in FIGS. 7 and 8 are cross-sectional views showing the structure of a conventional microcrystalline silicon TFT.

7 and 8, after the gate electrode 2 is formed on the substrate 1 made of glass or the like, the gate insulating film 3 is formed. As the gate insulating film 3, a single layer of SiN film is often applied as shown in FIG. Further, as shown in FIG. 8, the gate insulating film 3 may have a laminated structure in which a SiN film is formed as the first gate insulating film 31 and then a SiO ₂ film is formed as the second gate insulating film 34. However, when a stacked structure of SiN film and the SiO ₂ film, typically, SiO ₂ film of the second gate insulating film 34 is deposited a thick film thickness of at least 100 nm.

  An amorphous silicon (a-Si) film, which is an amorphous semiconductor film, is formed on the gate insulating film 3 thus formed, and the a-Si film is crystallized by a laser annealing method to form a microcrystalline silicon film. Convert. Thereby, the first semiconductor layer 41 which is a microcrystalline semiconductor film is formed. Next, the second semiconductor layer 42 and the ohmic contact film 6 are formed in this order. As the second semiconductor layer 42, an a-Si film that is an amorphous semiconductor film is formed. As the ohmic contact film 6, an n-type amorphous silicon (na-Si) film that is an n-type amorphous semiconductor film is formed. Thereafter, the ohmic contact film 6, the second semiconductor layer 42, and the first semiconductor layer 41 are patterned into a desired shape.

  Then, the source electrode 7 and the drain electrode 8 are formed on the ohmic contact film 6, and using these as a mask, the entire ohmic contact film 6 and a part of the second semiconductor layer 42 thereunder are removed by etching. As a result, the second semiconductor layer 42 between the source electrode 7 and the drain electrode 8 is exposed, and the channel region 9 is formed on the semiconductor layer 4 having a stacked structure in which the second semiconductor layer 42 is stacked on the first semiconductor layer 41. Is formed.

  Subsequently, after forming a protective film 10 covering the source electrode 7 and the drain electrode 8, a contact hole 11 reaching the drain electrode 8 is opened in the protective film 10. Then, the pixel electrode 12 connected to the drain electrode 8 through the contact hole 11 is formed on the protective film 10. By the above manufacturing method, an inverted staggered microcrystalline semiconductor silicon TFT having a stacked structure in which an amorphous semiconductor film is stacked on a microcrystalline semiconductor film is completed.

JP-A-5-107560

  As described above, in the conventional microcrystalline silicon TFT, a single layer of SiN film is often applied to the gate insulating film 3. In this case, when the amorphous semiconductor film is crystallized by laser annealing to form a microcrystalline semiconductor film, the amorphous and microscopic films are interposed between the gate insulating film 3 and the first semiconductor layer 41 as shown in FIG. A mixed layer 14 which is a semiconductor layer in which crystals are mixed is formed.

  FIG. 9 is a graph showing an IV curve which is one of TFT characteristics. A conventional microcrystalline silicon TFT in which a single layer of a SiN film is applied to the gate insulating film 3 has a curve in which the IV curve has moved to the negative side as indicated by the dotted line in FIG. Become. When the IV curve moves to the minus side, a considerable current flows even when the voltage is 0 V, and there is a problem that the display of the pixel portion cannot be normally operated.

In the conventional microcrystalline silicon TFT, when a laminated film of a SiN film and a SiO ₂ film is applied to the gate insulating film 3, an upper SiO ₂ film is usually formed with a thickness of 100 nm or more. In this case, even when the amorphous semiconductor film is crystallized by laser annealing to form the microcrystalline semiconductor film, the mixed layer 14 is not formed between the gate insulating film 3 and the first semiconductor layer 41. Therefore, in the conventional microcrystalline silicon TFT in which the laminated film of the SiN film and the SiO ₂ film is applied to the gate insulating film 3, the IV curve does not move to the minus side as shown by the solid line in FIG.

However, since the upper SiO ₂ film is once melted and solidified by the heat of laser annealing, the uneven portion 15 is formed on the surface of the SiO ₂ film as shown in FIG. Therefore, the surface roughness (surface irregularities) at the interface between the SiO ₂ film and the first semiconductor layer 41 is increased. In particular, when the thickness of the SiO ₂ film is as thick as 100 nm or more, the surface roughness becomes as large as 20 nm or more. As described above, when the surface roughness of the interface between the SiO ₂ film and the first semiconductor layer 41 is large, there is a problem that electric field concentration occurs and the gate dielectric breakdown voltage is lowered, and the TFT characteristics are lowered.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a thin film transistor, a display device, and a manufacturing method thereof having high reliability and high performance transistor characteristics. To do.

  A thin film transistor according to a first aspect of the present invention includes a gate electrode formed on a substrate, a SiN film and a SiN oxide layer formed on the SiN film, the gate insulating film covering the gate electrode, A semiconductor layer disposed on the opposite side of the gate electrode through a gate insulating film and having a microcrystalline semiconductor film formed at least at an interface portion in contact with the SiN oxide layer, and formed on the semiconductor layer through an ohmic contact film A source electrode and a drain electrode.

A thin film transistor according to a second aspect of the present invention includes a gate electrode formed on a substrate, a SiN film, and a SiO ₂ film having a thickness of 20 nm or less formed on the SiN film, and covering the gate electrode An insulating film, a semiconductor layer disposed opposite to the gate electrode through the gate insulating film, and having a microcrystalline semiconductor film formed at least at an interface portion in contact with the SiN film; and an ohmic contact film on the semiconductor layer And a source electrode and a drain electrode formed through the electrode.

  According to a third aspect of the present invention, there is provided a method for manufacturing a thin film transistor, comprising: a semiconductor having a microcrystalline semiconductor film at least at an interface portion in contact with the gate insulating film on a gate insulating film covering a gate electrode formed on a substrate; A method of manufacturing a thin film transistor provided with a layer, comprising: forming a SiN film on the gate electrode; forming a SiN oxide layer on a surface of the SiN film; and including the SiN film and the SiN oxide layer. Forming a gate insulating film; forming an amorphous semiconductor film directly on the surface of the SiN oxide layer; and crystallizing the amorphous semiconductor film by laser annealing, thereby forming the microcrystalline semiconductor film Forming the step.

According to a fourth aspect of the present invention, there is provided a method for manufacturing a thin film transistor, comprising: a semiconductor having a microcrystalline semiconductor film at least at an interface portion in contact with the gate insulating film on a gate insulating film covering a gate electrode formed on a substrate; a method of manufacturing a thin film transistor layer is provided, wherein the SiN film is formed on the gate electrode, the on SiN film is formed below the SiO ₂ film thickness 20 nm, the SiN film and the SiO ₂ film Forming a gate insulating film including: an amorphous semiconductor film directly on the surface of the SiO ₂ film, and crystallizing the amorphous semiconductor film by laser annealing, Forming a microcrystalline semiconductor film.

  According to the present invention, it is possible to provide a thin film transistor, a display device, and a manufacturing method thereof having high reliability and high performance transistor characteristics.

2 is a front view showing a configuration of a TFT array substrate used in the liquid crystal display device according to Embodiment 1. FIG. 3 is a plan view showing a pixel configuration of a TFT array substrate according to Embodiment 1. FIG. 2 is a cross-sectional view illustrating a configuration of a TFT according to Embodiment 1. FIG. 5 is a cross-sectional view showing one manufacturing process of the TFT array substrate used in the display device according to Embodiment 1. FIG. 5 is a cross-sectional view showing one manufacturing process of the TFT array substrate used in the display device according to Embodiment 1. FIG. FIG. 6 is a cross-sectional view illustrating a configuration of a TFT according to a second embodiment. It is sectional drawing which shows the structure of the conventional microcrystal silicon TFT. It is sectional drawing which shows the structure of the conventional microcrystal silicon TFT. It is a graph which shows the IV curve which is one of the TFT characteristics.

  Embodiments of the present invention will be described below with reference to the drawings. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. For the sake of clarification, duplicate explanation is omitted as necessary. In addition, what attached | subjected the same code | symbol in each figure has shown the same element, and description is abbreviate | omitted suitably.

Embodiment 1 FIG.
First, the liquid crystal display device according to the first embodiment will be described with reference to FIG. FIG. 1 is a front view showing a configuration of a TFT array substrate used in the liquid crystal display device according to the first embodiment. The display device according to the first embodiment will be described using a liquid crystal display device as an example. However, the display device is merely an example, and a flat display device (flat panel display) such as an organic EL display device can also be used. is there. The overall configuration of this liquid crystal display device is common to the first and second embodiments described below.

  The liquid crystal display device according to the first embodiment has a substrate 1. The substrate 1 is, for example, an array substrate such as a TFT array substrate. The substrate 1 is provided with a display area 101 and a frame area 102 provided so as to surround the display area 101. In the display area 101, a plurality of gate lines (scanning signal lines) 103 and a plurality of source lines (display signal lines) 104 are formed. The plurality of gate wirings 103 are provided in parallel. Similarly, the plurality of source lines 104 are provided in parallel. The gate wiring 103 and the source wiring 104 are formed so as to cross each other. A region surrounded by the adjacent gate wiring 103 and source wiring 104 is a pixel 107. Accordingly, in the display area 101, the pixels 107 are arranged in a matrix.

  A scanning signal driving circuit 105 and a display signal driving circuit 106 are provided in the frame region 102 of the substrate 1. The gate wiring 103 extends from the display area 101 to the frame area 102 and is connected to the scanning signal driving circuit 105 at the end of the substrate 1. Similarly, the source wiring 104 extends from the display area 101 to the frame area 102 and is connected to the display signal driving circuit 106 at the end of the substrate 1. An external wiring 108 is connected in the vicinity of the scanning signal driving circuit 105. Further, an external wiring 109 is connected in the vicinity of the display signal driving circuit 106. The external wirings 108 and 109 are wiring boards such as an FPC (Flexible Printed Circuit).

  Various external signals are supplied to the scanning signal driving circuit 105 and the display signal driving circuit 106 via the external wirings 108 and 109. The scanning signal driving circuit 105 supplies a gate signal (scanning signal) to the gate wiring 103 based on an external control signal. The gate wiring 103 is sequentially selected by this gate signal. The display signal driving circuit 106 supplies a display signal to the source wiring 104 based on an external control signal or display data. As a result, a display voltage corresponding to the display data can be supplied to each pixel 107.

  In the pixel 107, at least one TFT 50 is formed. Here, a plan view showing a pixel configuration of the TFT array substrate according to the first embodiment is shown in FIG. FIG. 2 shows one of the pixels 107 on the TFT array substrate. As shown in FIG. 2, the TFT 50 is disposed in the vicinity of the intersection of the source wiring 104 and the gate wiring 103. Although a detailed configuration of the TFT 50 will be described later, for example, the TFT 50 supplies a display voltage to the pixel electrode 12. That is, the TFT 50 which is a switching element is turned on by a gate signal supplied from the gate wiring 103 to the gate electrode 2. Thereby, a display voltage is applied from the source electrode 7 connected to the source wiring 104 to the pixel electrode 12 connected to the drain electrode 8 via the semiconductor layer 4 of the TFT 50. An electric field corresponding to the display voltage is generated between the pixel electrode 12 and the counter electrode.

  In addition, at least one storage capacitor is formed in the pixel 107. With this storage capacitor, even when no display voltage is applied to the pixel electrode 12, the charge of the pixel electrode 12 can be continuously held. For example, the storage capacitor is configured by the pixel electrode 12, the storage capacitor wiring 103a disposed between the adjacent gate wirings 103, and an insulating film sandwiched between them. An alignment film (not shown) is formed on the surface of the substrate 1.

  Furthermore, a counter substrate is disposed opposite to the substrate 1. The counter substrate is, for example, a color filter substrate, and is disposed on the viewing side. A color filter, a black matrix (BM), an alignment film, and the like are formed on the counter substrate. The counter electrode may be disposed on the substrate 1 side. Then, a liquid crystal layer is sandwiched between the substrate 1 and the counter substrate. That is, liquid crystal is introduced between the substrate 1 and the counter substrate. Furthermore, a polarizing plate, a phase difference plate, and the like are provided on the outer surfaces of the substrate 1 and the counter substrate. A backlight unit or the like is disposed on the non-viewing side of the liquid crystal display panel.

  The liquid crystal is driven by the electric field between the pixel electrode 12 and the counter electrode. That is, the alignment direction of the liquid crystal between the substrates changes. As a result, the polarization state of the light passing through the liquid crystal layer changes. That is, the polarization state of light that has been linearly polarized after passing through the polarizing plate is changed by the liquid crystal layer. Specifically, light from the backlight unit becomes linearly polarized light by the polarizing plate on the array substrate side. As the linearly polarized light passes through the liquid crystal layer, the polarization state changes.

  The amount of light passing through the polarizing plate on the counter substrate side varies depending on the polarization state. That is, the amount of light that passes through the polarizing plate on the viewing side among the transmitted light that passes through the liquid crystal display panel from the backlight unit changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel.

  Next, the configuration of the TFT 50 according to the first embodiment will be described with reference to FIG. FIG. 3 is a cross-sectional view showing a configuration of the TFT 50 according to the first embodiment. FIG. 3 shows a III-III cross section of FIG. Here, the configuration of the TFT 50 of the first embodiment will be described by taking the pixel switching element TFT 50 provided on the TFT array substrate as an example.

  In FIG. 3, a gate electrode 2 is provided on a transparent insulating substrate 1 such as glass or quartz. For example, as shown in FIG. 2, the gate electrode 2 is formed integrally with the gate wiring 103 so that a partial region of the gate wiring 103 functions as the gate electrode 2. The gate electrode 2 is formed of a metal material or an alloy material such as Al, Cr, Mo, Ti, and W, for example. Here, the gate electrode 2 having a thickness of about 200 nm is formed of Cr.

  A gate insulating film 3 is provided so as to cover the gate electrode 2. The gate insulating film 3 has a laminated structure in which a second gate insulating film 32 made of a SiN oxide layer is laminated on a first gate insulating film 31 made of a SiN film. Here, an oxide layer of the first gate insulating film 31 is formed on the first gate insulating film 31 having a thickness of about 400 nm. As described above, the gate insulating film 3 according to the first embodiment includes the SiN film as the first gate insulating film 31 and the SiN oxide layer as the second gate insulating film 32 provided on the first gate insulating film 31. It is the composition which includes. By configuring the gate insulating film 3 in such a configuration, the mixed layer 14 of amorphous and microcrystal shown in FIG. 7 and the uneven portion 15 shown in FIG. 8 are formed at the interface with the semiconductor layer 4 described later. The formation can be prevented.

  A semiconductor layer 4 is formed on the gate insulating film 3. The semiconductor layer 4 is provided on the opposite side of the gate electrode 2 with the gate insulating film 3 interposed therebetween. In the semiconductor layer 4, a microcrystalline semiconductor film is formed at the interface portion in contact with the second gate insulating film 32. Specifically, the semiconductor layer 4 has a stacked structure in which a second semiconductor layer 42 made of an amorphous semiconductor film is stacked on a first semiconductor layer 41 made of a microcrystalline semiconductor film. The first semiconductor layer 41 is disposed on the gate insulating film 3 side of the semiconductor layer 4. That is, the first semiconductor layer 41 is disposed between the second semiconductor layer 42 and the second gate insulating film 32. Here, for example, microcrystalline silicon having a thickness of about 60 nm is formed as the first semiconductor layer 41, and amorphous silicon (a-Si) having a thickness of about 100 nm is formed as the second semiconductor layer 42. As described above, in the first embodiment, the semiconductor layer 4 in which the microcrystalline semiconductor film is formed is provided at least at the interface portion in contact with the SiN oxide layer that is the second gate insulating film 32.

  An ohmic contact film 6 is provided on the semiconductor layer 4. The ohmic contact film 6 is disposed on substantially the entire surface of the semiconductor layer 4 except for the channel region 9 of the TFT 50. The ohmic contact film 6 is formed of an amorphous semiconductor layer into which conductive impurities are introduced. Here, the ohmic contact film 6 is formed with a film thickness of about 50 nm from amorphous silicon (na-Si) doped with an n-type impurity such as phosphorus (P) at a high concentration. .

  Of the semiconductor layer 4, the region of the semiconductor layer 4 corresponding to the ohmic contact film 6 becomes a source / drain region. Specifically, the region of the semiconductor layer 4 corresponding to the left ohmic contact film 6 in FIG. 3 becomes the source region. Then, a region of the semiconductor layer 4 corresponding to the right ohmic contact film 6 in FIG. 3 becomes a drain region. Thus, source / drain regions are formed at both ends of the semiconductor layer 4 constituting the TFT 50. A region sandwiched between the source / drain regions of the semiconductor layer 4 becomes a channel region 9. The ohmic contact film 6 is not formed on the channel region 9 of the semiconductor layer 4.

  A source electrode 7 and a drain electrode 8 are formed on the ohmic contact film 6. Specifically, the source electrode 7 is formed on the ohmic contact film 6 on the source region side of the semiconductor layer 4. A drain electrode 8 is formed on the ohmic contact film 6 on the drain region side. Thus, the inverted stagger type TFT 50 is configured. The source electrode 7 and the drain electrode 8 are formed so as to extend outside the channel region of the semiconductor layer 4. That is, the source electrode 7 and the drain electrode 8 are not formed on the channel region of the semiconductor layer 4 like the ohmic contact film 6. The source electrode 7 and the drain electrode 8 are made of, for example, a metal material or an alloy material such as Al, Cr, Mo, Ti, and W. Here, the gate electrode 2 having a thickness of about 200 nm is formed of Cr. Note that the source electrode 7 may be formed integrally with the source wiring 104 so that a region branched from the source wiring 104 functions as the source electrode 7 as shown in FIG.

  A protective film 10 is provided so as to cover the source electrode 7, the drain electrode 8, and the semiconductor layer 4. A contact hole 11 reaching the drain electrode 8 is opened in the protective film 10. Here, the protective film 10 is formed of, for example, a SiN film having a thickness of about 200 nm.

  A pixel electrode 12 connected to the drain electrode 8 through the contact hole 11 is provided on the protective film 10. The pixel electrode 12 is formed of a transparent conductive film such as ITO. Here, the pixel electrode 12 is formed of, for example, ITO having a film thickness of about 100 nm.

  As described above, the TFT 50 according to the first embodiment includes the gate electrode 2 formed on the substrate 1, the first gate insulating film 31 made of the SiN film, and the SiN oxide layer formed on the first gate insulating film 31. A gate insulating film 3 including a second gate insulating film 33, a semiconductor layer 4 in which a microcrystalline semiconductor film (first semiconductor layer 41) is formed at least at an interface portion in contact with the second gate insulating film 33, and a semiconductor layer 4, a source electrode 7 and a drain electrode 8 formed via an ohmic contact film 6 are provided.

  Subsequently, a manufacturing method of the TFT 50 according to the first embodiment will be described with reference to FIGS. 4 and 5 are cross-sectional views showing one manufacturing process of the TFT array substrate used in the display device according to the first embodiment.

  First, a conductive film to be the gate electrode 2 is formed on a transparent insulating substrate 1 such as glass or quartz. A metal material or an alloy material such as Al, Cr, Mo, Ti, or W can be used for the conductive film to be the gate electrode 2. Here, Cr is deposited over the entire surface of the substrate 1 with a thickness of about 200 nm as a conductive film to be the gate electrode 2 by sputtering or the like. Next, a resist pattern is formed on the formed conductive film by a known photolithography method. Then, etching is performed using this resist pattern as a mask, and the conductive film to be the gate electrode 2 is patterned into a desired shape. Thereafter, the resist pattern is removed. Thereby, the gate electrode 2 is formed.

Next, a gate insulating film 3 is formed so as to cover the gate electrode 2. In the first embodiment, the gate insulating film 3 having a stacked structure in which the second gate insulating film 32 is stacked is formed on the first gate insulating film 31. Specifically, a SiN film having a thickness of about 400 nm is formed on the gate electrode 2 as the first gate insulating film 31 by a plasma CVD method using a mixed gas of SiH ₄ , NH ₃ , and N ₂ gas. A film is formed on the entire surface. Thereafter, plasma treatment using a gas containing at least O ₂ or N ₂ O is performed on the surface of the first gate insulating film 31 to form an SiN oxide layer on the surface of the first gate insulating film 31. That is, an SiN oxide layer is formed as the second gate insulating film 32 on the surface of the SiN film that is the first gate insulating film 31. Here, O ₂ plasma treatment is performed using O ₂ gas. In this way, a laminated film in which the second gate insulating film 32 made of the SiN oxide layer is laminated on the first gate insulating film 31 made of the SiN film is formed as the gate insulating film 3.

  Subsequently, a first semiconductor layer 41 is formed on the gate insulating film 3. In the first embodiment, first, an amorphous semiconductor film 41a for forming the first semiconductor layer 41 is formed. For example, an amorphous silicon film is formed over the entire surface of the substrate 1 with a film thickness of 30 to 100 nm, preferably 50 to 70 nm, using the plasma CVD method as the amorphous semiconductor film 41a. Here, an amorphous silicon film having a thickness of about 60 nm is formed. The first gate insulating film 31, the second gate insulating film 32, and the amorphous semiconductor film 41a are preferably formed continuously in the same apparatus or the same chamber. Thereby, contaminants such as boron existing in the air atmosphere can be prevented from being taken into the interface of each film. As a result, the configuration shown in FIG.

  Note that annealing is preferably performed at a high temperature after the amorphous semiconductor film 41a is formed. This is performed in order to reduce the amount of hydrogen since the amorphous semiconductor film 41a formed by the plasma CVD method contains a large amount of hydrogen in the film. Here, the inside of the chamber held in a low vacuum state in a nitrogen atmosphere is heated to about 480 ° C., and the substrate 1 on which the amorphous semiconductor film 41a is formed is held for 45 minutes. If such a process is performed, in the step of crystallizing the amorphous semiconductor film 41a, which will be described later, hydrogen is not rapidly desorbed as the temperature rises, and surface roughness of the amorphous semiconductor film 41a occurs. Can be suppressed.

  Next, after the natural oxide film formed on the surface of the amorphous semiconductor film 41a is removed by etching with hydrofluoric acid, the amorphous semiconductor film 41a is crystallized. Specifically, laser light is irradiated from above the amorphous semiconductor film 41a while blowing a gas such as nitrogen. As the laser light applied to the amorphous semiconductor film 41a, a laser beam converted into a linear beam through a predetermined optical system is used. Here, the second harmonic (oscillation wavelength: 532 nm) of the YAG laser is used as the laser light, but an excimer laser may be used as the laser light instead of the second harmonic of the YAG laser. When irradiated with laser light, the amorphous semiconductor film 41a is once melted and crystallized to be converted into a microcrystalline semiconductor film. For example, amorphous silicon formed as the amorphous semiconductor film 41a is crystallized and converted into microcrystalline silicon when irradiated with laser light. As described above, when the amorphous semiconductor film 41a is irradiated with laser light while nitrogen is blown, the height of the protrusion generated in the crystal grain boundary portion of the microcrystalline semiconductor film can be suppressed. Therefore, the surface roughness of the first semiconductor layer 41 can be reduced to about 3 nm or less. As a result, as shown in FIG. 4B, the amorphous semiconductor film 41a is crystallized to form the first semiconductor layer 41 made of a microcrystalline semiconductor film.

At this time, in the first embodiment, since the amorphous semiconductor film 41a irradiated with the laser light is directly formed on the surface of the second gate insulating film 32 made of the SiN oxide layer, the gate insulating film 3 It is possible to prevent the mixed layer 14 of amorphous and microcrystals from being formed at the interface. In other words, laser irradiation can be performed with a sufficient energy density to crystallize the amorphous semiconductor film 41a without causing N incorporation into the amorphous semiconductor film 41a. Therefore, the amorphous semiconductor film 41a can be crystallized up to the interface with the gate insulating film 3, and the mixed layer 14 can be prevented from being formed. Further, in the first embodiment, the gate insulating film 3 has a stacked structure in which a second gate insulating film 32 made of an oxide layer of the first gate insulating film 31 is stacked on the first gate insulating film 31. Since the surface of the gate insulating film 3 does not have the SiO ₂ film that melts by the heat of laser annealing to form the uneven portion 15, the uneven portion 15 is formed at the interface between the gate insulating film 3 and the first semiconductor layer 41. Can be prevented. That is, the surface roughness of the interface between the gate insulating film 3 and the first semiconductor layer 41 can be reduced as compared with the conventional microcrystalline semiconductor TFT shown in FIG. 8, and the interface state can be improved. As described above, the second gate insulating film 32 is formed on the interface between the gate insulating film 3 and the semiconductor layer 4 at the mixed layer 14 of amorphous and microcrystal shown in FIG. 7 or the uneven portion 15 shown in FIG. It functions as a deterrent film that deters formation.

  Next, the substrate 1 is etched with hydrofluoric acid to remove the natural oxide film formed on the surface of the crystallized first semiconductor layer 41 and the first semiconductor layer 41 contaminated with boron or the like present in the air atmosphere. Clean the surface. Thereafter, a second semiconductor layer 42 made of an amorphous semiconductor film and an ohmic contact film 6 made of an amorphous semiconductor film containing an n-type impurity are formed in this order on the first semiconductor layer 41. Here, for example, plasma CVD is used to form amorphous silicon (a-Si) having a thickness of about 100 nm as the second semiconductor layer 42 and n-type amorphous silicon (na) having a thickness of about 50 nm as the ohmic contact film 6. Si) are sequentially formed on the entire surface of the substrate 1.

Next, a resist pattern having a desired shape is formed on the ohmic contact film 6 using a known photolithography method. Then, the ohmic contact film 6, the second semiconductor layer 42, and the first semiconductor layer 41 are patterned using this resist pattern as a mask. Here, patterning is performed by, for example, a dry etching method using CF ₄ gas. Thereafter, the resist pattern is removed. As a result, as shown in FIG. 4C, the laminated film including the ohmic contact film 6, the second semiconductor layer 42, and the first semiconductor layer 41 is patterned into an island shape.

  Then, a conductive film to be the source electrode 7 and the drain electrode 8 is formed so as to cover the pattern of the laminated film including the ohmic contact film 6, the second semiconductor layer 42, and the first semiconductor layer 41. For the conductive film to be the source electrode 7 and the drain electrode 8, a metal material or an alloy material such as Al, Cr, Mo, Ti, or W can be used. Here, Cr is formed over the entire surface of the substrate 1 with a thickness of about 200 nm as a conductive film to be the source electrode 7 and the drain electrode 8 by sputtering or the like. Next, a resist pattern is formed on the formed conductive film by a known photolithography method. Then, etching is performed using this resist pattern as a mask, and this conductive film is patterned into a desired shape. Thereafter, the resist pattern is removed. As a result, as shown in FIG. 4D, the source electrode 7 and the drain electrode 8 are formed.

Next, etching is performed using the formed source electrode 7 and drain electrode 8 as a mask, and the ohmic contact film 6 is removed. For example, the ohmic contact film 6 is entirely removed in the depth direction by dry etching using CF ₄ gas, and the second semiconductor layer 42 is partially removed in the depth direction. That is, the stacked film composed of the ohmic contact film 6, the second semiconductor layer 42, and the first semiconductor layer 41 is etched by a predetermined etching amount using the source electrode 7 and the drain electrode 8 as a mask. As a result, as shown in FIG. 5E, the second semiconductor layer 42 between the source electrode 7 and the drain electrode 8 is exposed, and the ohmic contact film 6 is formed between the source region and the channel region 9 of the semiconductor layer 4. The drain region is separated. In this way, the TFT 50 of the first embodiment is completed.

Thereafter, a protective film 10 is formed on these. For example, a SiN film of about 200 nm is formed on the entire surface of the substrate 1 as the protective film 10 by using plasma CVD. As a result, the source electrode 7, the drain electrode 8, and the channel region 9 of the TFT 50 are covered with the protective film 10. Next, a resist pattern is formed on the protective film 10 using a known photolithography method. Then, the protective film 10 is etched using this resist pattern as a mask to form a contact hole 11 reaching the drain electrode 8. For example, the contact hole 11 is opened in the protective film 10 by a dry etching method using CF ₄ gas. Thereafter, when the resist pattern is removed, the structure shown in FIG.

  Next, when this TFT 50 is used as a pixel switching element, a transparent conductive film to be the pixel electrode 12 is formed on the protective film 10. For the transparent conductive film to be the pixel electrode 12, for example, ITO can be used. For example, an ITO film having a thickness of 100 nm is formed on the entire surface of the substrate 1 by sputtering. Then, a resist pattern is formed on the formed transparent conductive film by a known photolithography method. Then, etching is performed using the resist pattern as a mask, and the transparent conductive film is patterned into a desired shape. Thereafter, the resist pattern is removed. Thereby, as shown in FIG. 5G, the pixel electrode 12 connected to the drain electrode 8 through the contact hole 11 is formed. Through the above steps, the TFT array substrate used in the display device according to the present embodiment is completed.

  As described above, in the first embodiment, the second gate insulating film 32 made of the SiN oxide layer is formed on the side of the gate insulating film 3 in contact with the semiconductor layer 4, and the amorphous semiconductor formed directly on the second gate insulating film 32 is formed. The film 41a is crystallized by being irradiated with laser light, and converted into a microcrystalline semiconductor film. When crystallization is performed by such a method, the first semiconductor layer 41 is brought to the interface with the gate insulating film 3 without forming the mixed layer 14 of amorphous and microcrystals at the interface with the gate insulating film 3. A completely crystallized microcrystalline semiconductor film can be obtained. Therefore, the IV curve of the TFT characteristics is a curve that does not move to the minus side as shown by the solid line in FIG. Therefore, a high performance TFT 50 can be obtained. Further, the surface roughness of the first semiconductor layer 41 at the interface between the gate insulating film 3 made of the SiN film and the SiN oxide layer formed on the SiN film and the first semiconductor layer 41 is reduced, and the interface state is improved. be able to. Accordingly, it is possible to suppress a decrease in the gate withstand voltage and improve the reliability of the TFT 50. Therefore, a thin film transistor, a display device, and a manufacturing method thereof having high reliability and high performance transistor characteristics can be provided.

  In the first embodiment, the pixel switching element TFT 50 provided in the pixel region of the TFT array substrate has been described as an example. However, the TFT 50 is a peripheral circuit such as the scanning signal driving circuit 105 or the display signal driving circuit 106. It may be formed in the region. Since the TFT 50 of this embodiment is a microcrystalline semiconductor TFT having a stacked structure in which an amorphous semiconductor film is stacked on a microcrystalline semiconductor film, a driving circuit that requires element driving capability and reliability is provided on the same substrate. Can be configured. That is, the TFT 50 of the first embodiment may be formed in both the pixel switching element and the peripheral circuit. This eliminates the need for externally attaching a driver IC, thereby realizing a display device with a narrow frame.

Embodiment 2. FIG.
The structure of the TFT according to the second embodiment will be described with reference to FIG. FIG. 6 is a cross-sectional view showing a configuration of the TFT 50 according to the second embodiment. FIG. 6 shows a cross section corresponding to the III-III cross section of FIG. In the second embodiment, only the configuration of the gate insulating film 3 is different from that of the first embodiment, and the other configuration is the same as that of the first embodiment, and thus the description thereof is omitted.

In FIG. 6, in the second embodiment, the second gate insulating film 33 made of a SiO ₂ film having a thickness of 20 nm or less is laminated on the first gate insulating film 31 made of the SiN film. Have a laminated structure. That is, the second gate insulating film 32 made of the SiN oxide layer is provided on the first gate insulating film 31 in the first embodiment. Instead, the second gate insulating film 32 having a thickness of 20 nm or less is provided in the second embodiment. A second gate insulating film 33 made of a SiO ₂ film is provided. The film thickness of the second gate insulating film 33 is preferably 10 nm or less in order to reduce the surface roughness. Here, a second gate insulating film 33 having a thickness of about 10 nm is formed on the first gate insulating film 31 having a thickness of about 350 nm.

As described above, the gate insulating film 3 of the second embodiment includes the SiN film as the first gate insulating film 31 and the film thickness of 20 nm as the second gate insulating film 33 provided on the first gate insulating film 31. The structure includes the following SiO ₂ film. In the first embodiment, the SiO ₂ film that is melted by the heat of laser annealing to form the uneven portion 15 is not included. However, in the gate insulating film 3 of the second embodiment, the SiO ₂ film that is melted by the heat of laser annealing is used. _{since 2} film is relatively thin and the film thickness 20nm or less, uneven portions 15 formed on the surface of the SiO ₂ film becomes to be finely formed only on the further electrode surface of the thin SiO ₂ film. By setting the thickness of the SiO ₂ film to 20 nm or less, it is possible to miniaturize the concavo-convex portion 15 to a level that does not cause a decrease in gate dielectric breakdown voltage and TFT characteristics due to electric field concentration. As described above, the gate insulating film 3 has a configuration in which the second gate insulating film 33 made of a SiO ₂ film having a thickness of 20 nm or less is provided on the first gate insulating film 31, and thus the first embodiment and the first embodiment. Similarly, it is possible to prevent the formation of the mixed layer 14 of amorphous and microcrystal shown in FIG. 7 and the large uneven portion 15 as shown in FIG. 8 at the interface with the semiconductor layer 4. A thin film transistor having high and high performance transistor characteristics can be obtained. That is, in the second gate insulating film 33, the mixed layer 14 and the large uneven portion 15 are formed at the interface between the gate insulating film 3 and the semiconductor layer 4 as in the second gate insulating film 32 of the first embodiment. Functions as a deterrent film.

The manufacturing method of the TFT 50 having such a configuration is different from the first embodiment only in the step of forming the gate insulating film 3, and the other steps are the same as those in the first embodiment, and thus the description thereof is omitted. In the step of forming the gate insulating film 3, a SiN film that is the first gate insulating film 31 is formed, and then a SiO ₂ film having a thickness of 20 nm or less is formed as a second gate insulating film 33 on the SiN film. In this way, the gate insulating film 3 including the SiN film and the SiO ₂ film is formed. Here, a SiN film is formed as a first gate insulating film 31 with a thickness of about 350 nm on the entire surface of the substrate 1 by a plasma CVD method using a mixed gas of SiH ₄ , NH ₃ , and N ₂ gas. Thereafter, a SiO ₂ film having a thickness of about 10 nm is formed on the entire surface of the substrate 1 as a second gate insulating film 31 by plasma CVD using a mixed gas of SiH ₄ , N ₂ O, and Ar gas. Thus, a laminated film in which the second gate insulating film 33 made of a SiO ₂ film having a thickness of 20 nm or less is laminated on the first gate insulating film 31 made of the SiN film is formed as the gate insulating film 3.

Thereafter, the first semiconductor layer 41 is formed on the gate insulating film 3 in the same manner as in the first embodiment. At this time, in the second embodiment, the amorphous semiconductor film 41a irradiated with the laser light is formed on the second gate insulating film 33 made of a SiO ₂ film having a thickness of 20 nm or less. As in Embodiment 1, it is possible to prevent the mixed layer 14 of amorphous and microcrystals from being formed at the interface with the gate insulating film 3. Therefore, the amorphous semiconductor film 41a can be crystallized up to the interface with the gate insulating film 3, and the mixed layer 14 can be prevented from being formed. Further, similarly to the first embodiment, it is possible to prevent the large uneven portion 15 from being formed at the interface between the gate insulating film 3 and the first semiconductor layer 41. That is, the surface roughness of the interface between the gate insulating film 3 and the first semiconductor layer 41 can be reduced as compared with the conventional microcrystalline TFT shown in FIG. 8, and the interface state can be improved. As described above, the second gate insulating film 33 is formed on the interface between the gate insulating film 3 and the semiconductor layer 4 at the mixed layer 14 of amorphous and microcrystal shown in FIG. 7 or the uneven portion 15 shown in FIG. It functions as a deterrent film that deters formation. The subsequent steps are the same as those in the first embodiment.

As described above, in the second embodiment, the second gate insulating film 33 made of a SiO ₂ film having a thickness of 20 nm or less is formed on the side of the gate insulating film 3 in contact with the semiconductor layer 4 and directly formed thereon. The amorphous semiconductor film 41a is crystallized by irradiating it with a laser beam and converted into a microcrystalline semiconductor film. When crystallization is performed by such a method, the first semiconductor layer 41 is brought to the interface with the gate insulating film 3 without forming the mixed layer 14 of amorphous and microcrystals at the interface with the gate insulating film 3. A completely crystallized microcrystalline semiconductor film can be obtained. For this reason, the IV curve of the TFT characteristics is a curve that does not move to the minus side, as shown by the solid line in FIG. 9, as in the first embodiment. Therefore, a high performance TFT 50 can be obtained. In addition, the surface roughness of the first semiconductor layer 41 at the interface between the gate insulating film 3 formed on the SiN film and the SiO ₂ film having a thickness of 20 nm or less formed on the SiN film and the first semiconductor layer 41 is sufficiently reduced. Thus, the interface state can be improved. Accordingly, it is possible to suppress a decrease in the gate withstand voltage and improve the reliability of the TFT 50. Therefore, a thin film transistor, a display device, and a manufacturing method thereof having high reliability and high performance transistor characteristics can be provided.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, in the above embodiment, an example in which the TFT 50 according to the present invention is applied to a liquid crystal display device has been described. However, the present invention is not limited to this. For example, a display device using a display material other than liquid crystal, such as organic EL or electronic paper, may be used. Furthermore, the TFT 50 according to the present invention can be suitably applied not only to a display device but also to other devices such as a semiconductor device.

1 substrate, 2 gate electrode, 3 gate insulating film,
4 semiconductor layer, 6 ohmic contact film,
7 source electrode, 8 drain electrode,
9 channel region, 10 protective film,
11 contact holes, 12 pixel electrodes,
14 mixed layers, 15 uneven parts,
31 1st gate insulating film,
32, 33, 34 second gate insulating film,
41 first semiconductor layer, 41a amorphous semiconductor film 42 second semiconductor layer, 50 TFT,
101 display area, 102 frame area,
103 gate wiring, 103a storage capacitor wiring,
104 source wiring, 105 scanning signal drive circuit,
106 display signal drive circuit, 107 pixels,
108, 109 External wiring

Claims (10)

A gate electrode formed on the substrate;
A gate insulating film including a SiN film and a SiN oxide layer formed on the SiN film and covering the gate electrode;
A semiconductor layer disposed on the opposite side of the gate electrode through the gate insulating film and having a microcrystalline semiconductor film formed at least in an interface portion in contact with the SiN oxide layer;
A thin film transistor comprising a source electrode and a drain electrode formed on the semiconductor layer via an ohmic contact film. A gate electrode formed on the substrate;
A gate insulating film including a SiN film and a SiO ₂ film having a thickness of 20 nm or less formed on the SiN film, and covering the gate electrode;
A semiconductor layer disposed on the opposite side of the gate electrode through the gate insulating film and having a microcrystalline semiconductor film formed at least in an interface portion in contact with the SiN film;
A thin film transistor comprising a source electrode and a drain electrode formed on the semiconductor layer via an ohmic contact film. The thin film transistor according to claim 2, wherein the thickness of the SiO ₂ film is 10 nm or less.   A display device using the thin film transistor according to claim 1.   The display device according to claim 4, wherein the thin film transistor is formed in a pixel switching element and a peripheral circuit. A method of manufacturing a thin film transistor, wherein a semiconductor layer having a microcrystalline semiconductor film is provided at least on an interface portion in contact with the gate insulating film on a gate insulating film covering a gate electrode formed on a substrate,
Forming a SiN film on the gate electrode, forming a SiN oxide layer on the surface of the SiN film, and forming the gate insulating film including the SiN film and the SiN oxide layer;
Forming a microcrystalline semiconductor film by directly forming an amorphous semiconductor film on the surface of the SiN oxide layer and crystallizing the amorphous semiconductor film by laser annealing. Manufacturing method. The method of manufacturing a thin film transistor according to claim 6, wherein in the step of forming the gate insulating film, the SiN oxide layer is formed by performing plasma treatment using at least O ₂ or N ₂ O on the surface of the SiN film. A method of manufacturing a thin film transistor, wherein a semiconductor layer having a microcrystalline semiconductor film is provided at least on an interface portion in contact with the gate insulating film on a gate insulating film covering a gate electrode formed on a substrate,
Forming a SiN film on the gate electrode, forming a SiO ₂ film having a thickness of 20 nm or less on the SiN film, and forming the gate insulating film including the SiN film and the SiO ₂ film;
Forming a microcrystalline semiconductor film by directly forming an amorphous semiconductor film on the surface of the SiO ₂ film and crystallizing the amorphous semiconductor film by laser annealing. Manufacturing method. 9. The method of manufacturing a thin film transistor according to claim 8, wherein in the step of forming the gate insulating film, the SiO ₂ film having a thickness of 10 nm or less is formed on the SiN film.   A method for manufacturing a display device, wherein a thin film transistor is formed in a pixel switching element and a peripheral circuit using the manufacturing method according to claim 6.

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