JP2010222187A - Production method of group iii nitride semiconductor layer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a production method of a group III nitride semiconductor layer, by which generation of warpage can be reduced. <P>SOLUTION: The production method of the group III nitride semiconductor layer includes steps of: forming a carbide layer 11 selected from titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide and tantalum carbide on a base substrate 10; growing a group III nitride semiconductor layer 12 above the carbide layer 11; and removing the base substrate 10 by inducing cracks in the group III nitride semiconductor layer 12 to obtain the group III nitride semiconductor layer. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a group III nitride semiconductor layer.

  In recent years, it has been proposed to use a gallium nitride (GaN) crystal as a substrate for producing a nitride-based optical device or an electronic device, and many research institutions have attempted to produce a bulk crystal to obtain this substrate. Yes. However, since the dissociation pressure of GaN is high, it is difficult to obtain a large bulk crystal from a melt like GaAs, and it is very difficult to produce a GaN bulk crystal that can be used as a GaN substrate.

For this reason, as a method of manufacturing a GaN substrate, a GaN layer to be a GaN substrate is grown on a dissimilar material substrate such as sapphire (Al ₂ O ₃ ) by an HVPE (Hydride Vapor Phase Epitaxy) method, and then the dissimilar material substrate is separated. A method of obtaining a GaN substrate by removing it is widely adopted. As a conventional technique related to such a GaN substrate manufacturing method, Patent Document 1 discloses a GaN semiconductor substrate manufacturing method using the HVPE method. This method is a so-called FIELO (Facet-Initiated Epitaxial Lateral Overgrowth) method.
First, on a sapphire (Al ₂ O ₃ ) substrate, a mask having a rectangular cross-section covering portion arranged in a stripe shape and an opening formed between the covering portions is formed.
After forming the mask, a GaN layer is grown from the opening, and a group III nitride semiconductor is selectively grown in the lateral direction while forming a facet structure. Then, the growth is stopped without completely covering the upper surface of the covering portion of the mask. Thereby, an exposed portion in which a part of the upper surface of the covering portion of the mask is exposed is formed.
Next, the mask is removed by dry etching to form a void, and a GaN layer is grown. Thereafter, the sapphire substrate is peeled off to obtain a GaN semiconductor substrate having a GaN layer.

Japanese Patent Laid-Open No. 10-312971

  In recent years, there has been a demand for further reduction of warpage of the GaN semiconductor substrate. However, when a GaN semiconductor substrate is manufactured by the method described in Patent Document 1, it has been difficult to meet the demand for such warpage reduction.

  An object of the present invention is to provide a method for producing a group III nitride semiconductor layer capable of reducing the occurrence of warpage.

As a result of intensive studies, the present inventor has found that there are the following problems when a GaN semiconductor substrate is manufactured by the method described in Patent Document 1.
When a group III nitride semiconductor is formed by the FIELO method, facets are formed at the initial stage of growth of the GaN layer. Due to the appearance of the facet, the dislocation advances toward the facet, and the dislocation extending perpendicularly to the base substrate cannot extend in the vertical direction. Crystal defects are bent laterally as the facet grows, and as the film thickness of the GaN layer increases, crystal defects decrease in the growth region.
Therefore, there are many crystal defects on the base substrate side of the GaN layer, and there are fewer crystal defects on the surface side of the GaN layer. Such a difference in the rate of occurrence of crystal defects in the thickness direction of the GaN layer causes the warpage of the GaN layer.

  The present invention has been devised to solve such problems, and according to the present invention, any one selected from titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide, or tantalum carbide on the base substrate. A step of forming a carbide layer, a step of growing a group III nitride semiconductor layer on the carbide layer, a region above the surface of the carbide layer on the group III nitride semiconductor layer side, and There is provided a method of manufacturing a group III nitride semiconductor layer, including a step of generating a crack in a region in the group III nitride semiconductor layer, removing the base substrate, and obtaining the group III nitride semiconductor layer.

According to this invention, any carbide layer selected from titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide is formed on the base substrate.
By forming such a carbide layer, the dislocation density can be reduced from the initial growth stage of the group III nitride semiconductor layer. Therefore, the difference in dislocation density in the thickness direction of the group III nitride semiconductor layer is reduced, and the occurrence of warpage of the group III nitride semiconductor layer can be reduced.
Furthermore, in the present invention, the base substrate is removed by causing a crack in the group III nitride semiconductor layer. By doing in this way, the area | region on the base substrate side in which a comparatively many dislocation exists compared with the surface side of a group III nitride semiconductor layer can be removed with a base substrate. Therefore, the difference in dislocation density in the thickness direction of the group III nitride semiconductor layer can be reduced, and the occurrence of warpage of the group III nitride semiconductor layer can be reduced.

Although the detailed principle has not been clarified, titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide, and tantalum carbide are all face-centered cubic carbides, and the (111) surface is a good group III nitride semiconductor. Since it has lattice matching, a group III nitride semiconductor layer with reduced defects due to lattice mismatch can be formed. When these carbide surfaces are exposed to an atmosphere containing moisture or oxygen, an oxide film is formed. Since this oxide film has a crystal structure different from that of carbide, it is difficult to transfer crystal information from the carbide, and it becomes a film made of polycrystals having various different orientations. Although the growth of the group III nitride semiconductor layer is suppressed on the oxide film, the oxide film is heated to a high temperature during the growth of the group III nitride semiconductor layer, or when the oxide film comes into contact with a reducing gas, It is considered that a void is formed, and the group III nitride semiconductor layer is selectively grown from the lower carbide layer through the void. Whichever carbide layer is used, the dislocation density can be reduced from the initial growth stage of the group III nitride semiconductor layer.
Titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide, and tantalum carbide are generally known to have a non-stoichiometric composition, and the C / M molar ratio is 1/1 or less (hereinafter, M is Ti, Zr, Hf, V, Ta). When the C / M molar ratio exceeds 1/1, C is liberated and the carbide layer becomes an MC mixed C film.

  Here, in the step of growing the group III nitride semiconductor layer, it is preferable to form a crack promoting layer for generating a crack in the group III nitride semiconductor layer in the group III nitride semiconductor layer.

  Further, in the step of growing a group III nitride semiconductor layer on the carbide layer, the step of forming a first group III nitride semiconductor layer containing an impurity that becomes the crack promoting layer and the first group III The first group III nitride semiconductor layer preferably includes a step of forming a second group III nitride semiconductor layer having a different impurity concentration on the group nitride semiconductor layer.

When the group III nitride semiconductor layer includes at least two layers having different impurity concentrations, the elastic modulus differs between the two layers.
In this case, in the process of cooling the group III nitride semiconductor layer, it is possible to cause cracks in the group III nitride semiconductor layer due to the difference in elastic modulus of each layer of the group III nitride semiconductor layer. Become.

  Further, the step of growing the group III nitride semiconductor layer on the carbide layer includes the step of forming a first undoped group III nitride semiconductor layer that is not doped with impurities, and the first undoped group III nitride. A step of forming a group III nitride semiconductor layer doped with an impurity on the oxide semiconductor layer as the first group III nitride semiconductor layer; and an impurity doped on the group III nitride semiconductor layer doped with the impurity Forming a second undoped group III nitride semiconductor layer as the second group III nitride semiconductor layer.

  By forming the first undoped group III nitride semiconductor layer, the group III nitride semiconductor layer doped with impurities, and the second undoped group III nitride semiconductor layer, there are a plurality of regions where the group III nitride semiconductor layer is likely to be cracked. Will be formed. Specifically, the interface between the first undoped group III nitride semiconductor layer and the group III nitride semiconductor layer doped with impurities, in the group III nitride semiconductor layer doped with impurities, or group III doped with impurities Cracks are likely to occur in a region such as an interface between the nitride semiconductor layer and the second undoped group III nitride semiconductor layer.

  Furthermore, the step of forming the first group III nitride semiconductor layer includes a step of forming a group III nitride semiconductor layer by three-dimensional growth while forming pits, and the second group III nitride semiconductor is formed. In the step of forming the layer, it is preferable to form a second group III nitride semiconductor layer having a pit density lower than that of the first group III nitride semiconductor layer by two-dimensional growth.

In the three-dimensional growth accompanying pit formation, impurities are easily taken from the atmosphere during crystal growth. Therefore, a first group III nitride semiconductor layer including a layer composed of a three-dimensionally grown portion by pit formation is formed, and a second group III having a pit density lower than that of the first group III nitride semiconductor layer is formed thereon. When the group nitride semiconductor layer is grown, a first group III nitride semiconductor layer and a second group III nitride semiconductor layer having different impurity concentrations can be formed. Thereby, cracks are likely to occur near the interface between the first group III nitride semiconductor layer and the second group III nitride semiconductor layer.
Also, in the process of forming a group III nitride semiconductor layer by three-dimensional growth while forming pits, dislocations contained in a large amount in the group III nitride semiconductor layer grown on the carbide layer are laterally represented by facets that appear in a three-dimensional length. Since it is bent in the direction, it effectively works to reduce defects.
Here, the three-dimensional growth means that crystal nuclei grow preferentially toward a space perpendicular to the base substrate surface rather than a horizontal growth along the base substrate surface.
The two-dimensional growth means growing in the horizontal direction along the surface of the base substrate. In the case of two-dimensional growth, the growth in the horizontal direction is much faster than the growth in the vertical direction of the substrate.

  At this time, the impurity is preferably Si or O. Si acts as an n-type dopant, and since Si is generally used as a dopant for a group III nitride semiconductor, it is convenient. O is an impurity that easily enters due to corrosion of a quartz structural member or the like during crystal growth, and can be doped without preparing a special dopant agent.

Furthermore, the present invention does not include a step of forming a mask for growing a group III nitride semiconductor layer from the opening on the base substrate.
Thereby, the labor for forming the mask can be saved, and the production of the group III nitride semiconductor layer can be simplified.
When a mask for growing a group III nitride semiconductor layer from an opening is formed, dislocation density varies between the region immediately above the mask and the region immediately above the opening in the group III nitride semiconductor layer. There is a possibility.
On the other hand, in the present invention, since no mask is used, variation in dislocation density in the surface direction of the group III nitride semiconductor layer can be suppressed.

  The carbide layer is preferably a titanium carbide layer. Titanium carbide has a group III nitride semiconductor layer with reduced defects due to lattice mismatch because the lattice matching with the base substrate (eg sapphire) and group III nitride and the thermal expansion coefficient of the base substrate are almost the same. Can be formed. In this way, the dislocation density can be reliably reduced from the initial growth stage of the group III nitride semiconductor layer.

The thickness of the carbide layer is preferably 20 nm or more and 500 nm or less.
By setting the thickness of the carbide layer to 20 nm or more, the carbide layer has good crystallinity and has the effect of improving the crystallinity of the group III nitride semiconductor layer.
In addition, even if the thickness of the carbide layer is greater than 500 nm, the crystallinity of the carbide layer is difficult to improve, and a problem occurs in that productivity decreases due to the long time required for film formation. There is an effect that a carbide layer having excellent crystallinity can be formed without a decrease in productivity.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the group III nitride semiconductor layer which can reduce generation | occurrence | production of curvature is provided.

It is a figure which shows the manufacturing process of the GaN layer concerning one Embodiment of this invention. It is a figure which shows the manufacturing process of the GaN layer concerning one Embodiment of this invention. It is a figure which shows the manufacturing process of the GaN layer concerning one Embodiment of this invention. It is a figure which shows the manufacturing process of the GaN layer concerning one Embodiment of this invention. It is a figure which shows the manufacturing process of the GaN layer concerning one Embodiment of this invention. It is a figure which shows the manufacturing process of the GaN layer concerning one Embodiment of this invention. It is a photograph of the GaN layer peeled off in Example 9 of the present invention and the GaN layer remaining on the sapphire substrate. It is the fluorescence-microscope photograph of the sapphire substrate after peeling the GaN layer of Example 9 of this invention, and a GaN layer. It is a figure which shows the relationship between the dislocation density of the TiC layer film thickness concerning Examples 10-17 of this invention, and the comparative example 2, and a GaN layer. It is a figure which shows the relationship between the GaN layer film thickness concerning Example 19 of this invention, and the comparative example 3, and a dislocation density.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, an outline of a method for manufacturing a group III nitride semiconductor layer of the present embodiment will be described. In the present embodiment, the group III nitride semiconductor layer is a GaN layer.
The method for producing a group III nitride semiconductor layer according to the present embodiment includes a step of forming any carbide layer selected from titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide, or tantalum carbide on a base substrate; A step of growing a group III nitride semiconductor layer on top of the layer, and a step of generating a crack in the group III nitride semiconductor layer to remove the base substrate to obtain the group III nitride semiconductor layer. .

Next, the manufacturing method of the GaN layer of this embodiment will be described in detail.
(Step of forming a carbide layer)
First, as shown in FIG. 1A, a base substrate is prepared. As the base substrate, for example, a 3-inch φ sapphire (Al ₂ O ₃ ) substrate 10 having a thickness of 550 μm is prepared.
Next, the titanium carbide layer 11 is formed on the sapphire substrate 10.
The conditions for forming the titanium carbide layer 11 are, for example, as follows.
Film forming method: reactive sputtering film forming temperature: 500 to 1000 ° C.
Deposition time: 4.5 to 114 minutes Pressure: 0.3 Pa to 0.5 Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: Ti
Film thickness: 20 nm to 500 nm
The film formation temperature is preferably 500 ° C. or more and 1000 ° C. or less, preferably 600 ° C. or more, and preferably 900 ° C. or less.
In addition, the thickness of the titanium carbide layer 11 is preferably 20 nm or more and 500 nm or less. In particular, from the viewpoint of improving crystallinity, the thickness is preferably 40 nm or more. Moreover, it is preferable to set it as 200 nm or less from a viewpoint of not spending a long time for formation of a titanium carbide layer.

(Deposition of GaN layer)
Next, a GaN layer 12 (see FIG. 2B) is epitaxially grown on the titanium carbide layer 11. Here, a mask for growing a GaN layer, such as the FIELO method, is not used. Further, the step of forming the GaN layer 12 is performed without providing the step of nitriding the titanium carbide layer 11.
First, as shown in FIG. 1B, a first GaN layer 121 is epitaxially grown on the titanium carbide layer 11.
The growth conditions of the first GaN layer 121 can be set as follows, for example.

Film forming method: HVPE (hydride vapor phase epitaxy) film forming temperature: 900 ° C. to 1050 ° C.
Film thickness: 50 μm to 100 μm
Impurity doping: None

  The thickness of the first GaN layer 121 is preferably 50 to 100 μm, particularly preferably 65 μm or more and 85 μm or less. By doing so, there is an effect that crystal defects can be reduced from the GaN layer 121 grown on the titanium carbide layer 11.

Next, as shown in FIG. 1C, a second GaN layer 122 is formed on the first GaN layer 121.
The growth conditions of the second GaN layer 122 can be set as follows, for example.

Film forming method: HVPE (hydride vapor phase epitaxy) film forming temperature: 1000 ° C. to 1050 ° C.
Film thickness: 50 μm to 350 μm
Impurity doping: Yes (Si)
The thickness of the second GaN layer 122 is preferably 50 to 350 μm, and particularly preferably 150 μm or more and 250 μm or less. With such a film thickness, there is an effect that a difference in physical properties such as the elastic modulus and the GaN layer 121 appears clearly, and cracks are easily generated.
Here, as a method for doping impurities, for example, Si can be doped using dichlorosilane. The impurity concentration is preferably 1 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less. By setting the impurity concentration to 1 × 10 ¹⁸ cm ⁻³ or more, there is an advantage that the elastic modulus can be made different from that of the undoped GaN layer 121. Moreover, there is an advantage that the crystal quality deterioration of the GaN layer can be suppressed by setting the impurity concentration to 5 × 10 ¹⁸ cm ⁻³ or less.
The second GaN layer 122 is a crack promoting layer for generating a crack in the GaN layer 12 in order to separate the sapphire substrate 10 as the base substrate.

Next, as shown in FIG. 2A, a third GaN layer 123 is formed on the second GaN layer 122.
The growth conditions of the third GaN layer 123 can be set as follows, for example.

Film forming method: HVPE (hydride vapor phase epitaxy) film forming temperature: 1000 ° C. to 1050 ° C.
Film thickness: 50 μm to 350 μm
Impurity doping: none The thickness of the third GaN layer 123 is preferably 50 to 350 μm, particularly preferably 150 μm or more and 250 μm or less. By doing so, a difference in physical properties such as elastic modulus with the GaN layer 122 becomes clear, and there is an effect that cracks are easily induced.

Thereafter, as shown in FIG. 2B, a fourth GaN layer 124 is formed on the third GaN layer 123. As a result, the GaN layer 12 including the first GaN layer 121 to the fourth GaN layer 124 is formed.
The growth conditions of the fourth GaN layer 124 can be set as follows, for example.

Film forming method: HVPE (hydride vapor phase epitaxy) film forming temperature: 1000 ° C. to 1050 ° C.
Film thickness: 200 μm to 1500 μm
Impurity doping: Yes (Si)
The thickness of the fourth GaN layer 124 is preferably 200 to 1500 μm, and particularly preferably 800 μm or more and 1200 μm or less. By doing in this way, there exists an effect that the probability that the GaN layer 124 will peel without a crack becomes high.
Here, as a method for doping impurities, for example, Si can be doped using dichlorosilane. The impurity concentration is preferably 0.5 × 10 ¹⁸ cm ⁻³ or more and 3 × 10 ¹⁸ cm ⁻³ or less. By setting the impurity concentration to 0.5 × 10 ¹⁸ cm ⁻³ or more, there is an advantage that necessary conductivity as an n-type GaN substrate can be secured. Moreover, there is an advantage that GaN crystallinity deterioration can be suppressed by setting the impurity concentration to 3 × 10 ¹⁸ cm ⁻³ or less.

(Sapphire substrate peeling process)
Next, as shown in FIG. 3, a crack is generated in the GaN layer 12, and the sapphire substrate 10 is removed. Specifically, the temperature of the HVPE apparatus on which the GaN layer 12 is formed is lowered, and the GaN layer 12 is cooled to room temperature.
The GaN layer 12 includes a second GaN layer 122 doped with Si, an undoped first GaN layer 121 that is not doped with Si, and a third GaN layer 123. Therefore, the elastic modulus is different between the second GaN layer 122 and the first GaN layer 121 and between the second GaN layer 122 and the third GaN layer 123. That is, the elastic modulus of the second GaN layer 122 is smaller than the elastic modulus of the first GaN layer 121 and the third GaN layer 123.
In the process of cooling the GaN layer 12, a convex warpage occurs in the GaN layer 12 due to a difference in thermal expansion coefficient between the sapphire substrate 10 and the GaN layer 12. Due to the influence of this warp and the difference between the elastic modulus of the second GaN layer 122 and the elastic modulus of the first GaN layer 121 and the third GaN layer 123, the second GaN layer is formed inside the second GaN layer 122. Cracks occur in a region such as the interface between the layer 122 and the first GaN layer 121 or the interface between the second GaN layer 122 and the third GaN layer 123.
As a result, a crack occurs in the GaN layer 12, and the sapphire substrate 10 is removed as shown in FIG.
Thereafter, by polishing the front and back surfaces of the GaN layer 12 ′ peeled from the sapphire substrate 10, a GaN substrate that is a flattened self-standing substrate can be produced.

Next, the effect of this embodiment is demonstrated.
In this embodiment, the titanium carbide layer 11 is formed on the sapphire substrate 10 which is a base substrate.
By forming such a carbide layer, the dislocation density can be reduced in the growth stage of the GaN layer 12. Therefore, the difference in dislocation density in the thickness direction of the GaN layer 12 is reduced, and the occurrence of warpage of the GaN layer 12 can be reduced.
Furthermore, in this embodiment, a crack is generated in the GaN layer 12 to remove the sapphire substrate 10. By doing in this way, the area | region by the side of the sapphire substrate 10 in which comparatively many dislocations exist compared with the surface side of the GaN layer 12 can be removed with the sapphire substrate 10. Therefore, the dislocation density difference in the thickness direction of the GaN layer 12 ′ separated from the sapphire substrate 10 can be reduced, and the occurrence of warpage of the GaN layer can be reduced.

In the present embodiment, the GaN layer 12 is composed of a plurality of layers having different elastic moduli. Specifically, the second GaN layer 122 doped with Si, the first GaN layer 121 and the third GaN layer 123 which are undoped layers are formed, and the elastic moduli of these layers are different. .
In the process of cooling the GaN layer 12, a convex warpage occurs in the GaN layer 12 due to a difference in thermal expansion coefficient between the sapphire substrate 10 and the GaN layer 12. Due to the influence of this warp and the difference between the elastic modulus of the second GaN layer 122 and the elastic modulus of the first GaN layer 121 and the third GaN layer 123, the second GaN layer is formed inside the second GaN layer 122. Cracks occur at the interface between the layer 122 and the first GaN layer 121 or at the interface between the second GaN layer 122 and the third GaN layer 123. Thus, the sapphire substrate 10 and the sapphire substrate 10 side region of the GaN layer 12 can be easily removed.

  Further, the titanium carbide layer 11 is nitrided with a gas containing nitrogen in the process of forming the GaN layer 12. That is, TiN is formed on the surface of the titanium carbide layer 11, and this TiN is suitable for epitaxial growth of the GaN layer 12 because it is the same face-centered cubic crystal as TiC and has a lattice constant approximating.

  Furthermore, in this embodiment, the thickness of the titanium carbide layer 11 is 20 nm or more and 500 nm or less. By setting the thickness of the titanium carbide layer to 20 nm or more, there is an effect that the crystallinity of the titanium carbide layer can be improved. In addition, when the thickness of the titanium carbide layer is 500 nm or less, there is an effect that it does not take a long time to form the titanium carbide layer.

Further, when a GaN layer is formed by the conventional FIELO method, it is necessary to form a mask that covers the sapphire substrate. Since the mask is used in this way, there is a problem that costs are increased. In forming the mask, generally, an SiO ₂ film is formed, and this film is selectively removed by etching to form an opening. Therefore, it takes time to form the mask.
On the other hand, in this embodiment, a mask is not required and a titanium carbide layer may be formed, so that the cost can be reduced and the time for etching or the like can be saved because the mask is formed.
In addition, when a mask for growing a GaN layer from an opening is formed, there is a possibility that dislocation density varies between the region immediately above the mask and the region immediately above the opening in the GaN layer. .
On the other hand, in this embodiment, since no mask is used, variation in dislocation density in the plane direction of the GaN layer 12 can be suppressed.

  In the above-described embodiment, the titanium carbide layer 11, the GaN layer 12, and the like are manufactured under specific manufacturing conditions, but there is no particular limitation. That is, the above-described film thickness and manufacturing conditions are merely examples, and can be appropriately changed according to the composition and structure of the semiconductor layer to be formed.

For example, a layer containing TiC and C (hereinafter, TiC-dispersed C film) 112 may be formed on the titanium carbide layer 11.
As shown in FIG. 4 (A), a titanium carbide layer 111 similar to the titanium carbide layer 11 of the above embodiment is formed on the sapphire substrate 10, and then the titanium carbide layer 111 is shown in FIG. 4 (B). A two-layer structure is formed in which a TiC-dispersed C film 112 having a composition with a C / Ti ratio exceeding 1 is formed.
Thereafter, a GaN layer is formed on the TiC-dispersed C film 112 without providing a step of nitriding the titanium carbide layer 11 and the TiC-dispersed C film 112 as in the above embodiment. As shown in FIG. 4C, when the GaN layer 121 is grown, C in the TiC-dispersed C film 112 reacts with hydrogen in the nitriding gas and vaporizes as CH ₄ , so that the TiC-dispersed C film 112 is carbonized. Voids communicating with the titanium layer 111 are generated. Further, since TiC in the TiC-dispersed C film 112 is a particle having a random crystal orientation and forms an oxide film when exposed to the atmosphere, the growth of the GaN layer 121 is suppressed, so that the titanium carbide layer The selective growth of the GaN layer 121 can be realized with good reproducibility from the gap 111 to the TiC-dispersed C film.
As shown in FIG. 4C, the GaN layer 121 grows three-dimensionally while forming a facet structure from crystal nuclei.
Thereafter, when the GaN layer 121 is made thicker while adjusting the growth conditions, three-dimensional growth of GaN accompanied by formation of pits P occurs as shown in FIG. At this time, the facets collide and grow while being bonded, and the GaN layer 121 becomes an uneven surface state. Thereafter, the growth rate in the vertical direction of the three-dimensional growth sapphire substrate is reduced, and the GaN layer 121 is completed by shifting from the three-dimensional growth to the two-dimensional growth. The GaN layer 121 is used as the first GaN layer, and a GaN layer 122 grown under growth conditions in which pit formation is suppressed as shown in FIG. 5B is grown thereon.
The GaN layer 122 is a layer formed by two-dimensional growth, and the pit density of the GaN layer 122 is less than the pit density of the GaN layer 121. When the GaN layers 121 and 122 are formed, impurities are doped. At this time, since impurities are taken into the pits, the first GaN layer and the second GaN layer having different impurity concentrations can be easily formed. Can be formed.
While the temperature of the HVPE apparatus in which the GaN layers 121 and 122 are formed is lowered and the GaN layers 121 and 122 are cooled to room temperature, cracks occur near the interface between the GaN layer 121 and the GaN layer 122, as shown in FIG. In addition, the sapphire substrate 10 is removed.
The three-dimensional growth and two-dimensional growth of GaN can be controlled by adjusting the growth rate of GaN. By increasing the growth rate, three-dimensional growth is facilitated, and pits are easily formed at this time. By slowing the growth rate, two-dimensional growth is facilitated and pit formation is suppressed.
Even in this case, a mask for growing the GaN layer from the opening is not used.

Furthermore, the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.
For example, in each of the above embodiments, the sapphire substrate 10 is used as the base substrate, but a spinel substrate, SiC substrate, ZnO substrate, silicon substrate, GaAs substrate, GaP substrate, or the like may be used.
Moreover, in the said embodiment, although the titanium carbide layer was formed as a carbide | carbonized_material layer, not only this but a zirconium carbide, hafnium carbide, vanadium carbide, or a tantalum carbide may be sufficient.
These carbide layers have a face-centered cubic structure, the crystal structure does not change after nitriding, and the (111) plane of carbide and nitrided carbide has a common point that it is excellent in lattice matching with the group III nitride semiconductor layer, From the viewpoint that the GaN layer 12 can be epitaxially grown, any of the effects similar to the titanium carbide layer can be achieved.

In the step of peeling the sapphire substrate 10 of the above embodiment, the sapphire substrate 10 is separated by cooling the sapphire substrate 10 and the GaN layer 12. The sapphire substrate 10 may be peeled off by applying a force to such an extent that does not apply.
However, as in the above embodiment, if the sapphire substrate 10 is separated and removed with little external force applied by cooling, damage to the GaN layer can be reliably suppressed. For this reason, a high-quality GaN semiconductor substrate with little damage can be stably obtained.

  By producing a group III nitride element structure on such a group III nitride semiconductor substrate, it is possible to produce a light emitting element such as a light emitting diode or a laser diode having an up / down electrode structure on the top and bottom. Application to electronic devices such as transistors is also possible. The III-nitride semiconductor substrate is best polished to a mirror surface, dry etching or chemical mechanical polishing (CMP), and then a light emitting element such as a light emitting diode or a laser diode, and an electronic device such as a transistor. is there. Further, it is possible to grow a high-quality GaN crystal by using a group III nitride semiconductor substrate as a seed crystal by an HVPE method, a flux method, an ammonothermal method, or the like.

Furthermore, in the said embodiment, although the carbide | carbonized_material layer was formed into a film by sputtering, you may form into a film by not only this but another method.
For example, the carbide layer may be formed by vacuum deposition. Further, for example, the carbide layer may be formed by stacking a metal film and a carbon film while heating the base substrate. It is also possible to form a film by CVD (Chemical Vapor Deposition) using metal chloride and hydrocarbon as raw materials.

Next, examples of the present invention will be described.
Example 1
A GaN semiconductor substrate was manufactured by the same method as in the previous embodiment. A sapphire substrate was used as the substrate.
(Step of forming a carbide layer)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: Ti
Film thickness: 120nm

(Step of forming GaN layer)
(First GaN layer)
The first GaN layer was composed of a GaN buffer layer and a high temperature growth layer. The first GaN layer is undoped.
(GaN buffer layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 970 ° C.
Deposition gas: GaCl gas 180 cc / min, NH ₃ gas 3300 cc / min (V / III ratio = 10)
Thickness: 5μm
(High temperature growth layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 1040 ° C.
Deposition gas: GaCl gas 200 cc / min, NH ₃ gas 2000 cc / min (V / III ratio = 10)
Thickness: 70 μm

(Second GaN layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 1040 ° C.
Deposition gas: GaCl gas 200 cc / min, NH ₃ gas 2000 cc / min (V / III ratio = 10)
Doping: Si doping (HCl 3 cc / min is mixed with 9 cc / min of dichlorosilane (Si ₂ H ₂ Cl ₂ ) having a content of 3000 ppm and introduced into the HVPE apparatus.)
Thickness: 175 μm

(Third GaN layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 1040 ° C.
Deposition gas: GaCl gas 200 cc / min, NH ₃ gas 2000 cc / min (V / III ratio = 10)
Thickness: 175 μm
The third GaN layer is undoped.

(Fourth GaN layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 1040 ° C.
Deposition gas: GaCl gas 180 cc / min, NH ₃ gas 1800 cc / min (V / III ratio = 10)
Doping: Si-doped (3 cc / min of dichlorosilane (Si ₂ H ₂ Cl ₂ ) having a content of 3000 ppm is mixed with 3 cc / min of HCl and introduced into the HVPE apparatus.)
Thickness: 1100μm

(Peeling method)
The temperature in the HVPE apparatus in which the GaN layer was formed was lowered, and the sapphire substrate, carbide layer, and GaN layer were cooled to room temperature.

(Example 2)
In Example 1, the thickness of the carbide layer was 20 nm. Others were the same as in Example 1.

Example 3
In Example 1, the thickness of the carbide layer was 500 nm. Others were the same as in Example 1.

(Comparative Example 1)
A GaN layer was formed by the FIELO method.
Specifically, a GaN layer was obtained as follows.
A (0001) plane sapphire substrate was prepared as a base substrate. On this sapphire substrate, a 1.5 μm GaN film was formed.
Next, an SiO ₂ film was formed on the GaN film, and a mask having an opening was formed by photolithography and wet etching. The mask was in the form of a stripe having a width of 3 μm, and the extending direction of the stripe was the <11-20> direction. The width (short side) of the opening was 4 μm.

Next, a facet structure was grown by the following HVPE method.
Specifically, gallium chloride (GaCl), which is a reaction product of gallium (Ga) and hydrogen chloride (HCl), was used as the group III material, and ammonia (NH ₃ ) gas was used as the group V material.
The sapphire substrate was set in a hydride growth apparatus and heated to a growth temperature of 1040 ° C. in a hydrogen atmosphere. After the growth temperature was stabilized, an HCl flow rate was supplied at 200 cc / min and an NH ₃ flow rate was supplied at 2000 cc / min for 5 minutes to grow a GaN facet structure consisting of {1-101} planes. .
Further, the epitaxial growth was continued, and the growth was temporarily stopped with a part of the mask surface exposed. Then, the mask was removed with an etchant (10% HF aqueous solution).
Thereafter, the substrate was set again in a hydride growth apparatus, and the temperature was raised to a growth temperature of 1040 ° C. in a hydrogen atmosphere. After the growth temperature was stabilized, the GaN layer was epitaxially grown by supplying an HCl flow rate of 180 cc / min and an NH ₃ flow rate of 1800 cc / min for 300 minutes. The thickness of the GaN layer was 1100 μm.
The temperature in the HVPE apparatus in which the GaN layer was formed was lowered, and the GaN layer including the sapphire substrate was cooled to room temperature.

(Results of Examples 1 to 3 and Comparative Example 1)
In Examples 1 to 3, cracks occurred in the GaN layer during cooling in the HVPE apparatus, and the sapphire substrate and the GaN layer were separated.
In Comparative Example 1, the sapphire substrate and the GaN layer were separated during cooling in the HVPE apparatus.
Table 1 shows the results of dislocation density and radius of curvature of Examples 1 to 3 and Comparative Example 1.
The dislocation density was examined by a method of observing the number of dark spots per unit observation area by the cathodoluminescence (CL) method. Using the Horiba Cathode Luminescence Measurement System MP-10 attached to Hitachi's scanning electron microscope S-3000N, the number of dark spots existing in the 10μm square from the 362nm emission image emitted from the GaN layer irradiated with the electron beam The dark spot density was determined as the dislocation density (cm ⁻² ).
The radius of curvature was measured using a 4-axis X-ray diffractometer (Philips X'Pert MRD). The change in tilt angle (c-axis tilt) was measured at a position 20 mm away from the center on the c-plane of the GaN crystal, and the radius of curvature was calculated.

The dislocation density of the GaN layers obtained in Examples 1 to 3 was 7 × 10 ⁶ cm ⁻² or less, and the radius of curvature was 8 m or more. In contrast, the dislocation density of the GaN layer obtained in Comparative Example 1 was 1 × 10 ⁷ cm ⁻² and the radius of curvature was 2 m.

Example 4
In Example 1, titanium carbide was changed to zirconium carbide.
Others were the same as Example 1.
The conditions for forming the zirconium carbide layer are as follows.
(Step of forming a carbide layer)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: Zr
Film thickness: 120nm

(Example 5)
In Example 1, titanium carbide was changed to hafnium carbide.
Others were the same as Example 1.
The conditions for forming the hafnium carbide layer are as follows.
(Step of forming a carbide layer)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: Hf
Film thickness: 120nm

(Example 6)
In Example 1, titanium carbide was changed to vanadium carbide.
Others were the same as Example 1.
The conditions for forming the vanadium carbide layer are as follows.
(Step of forming a carbide layer)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: V
Film thickness: 120nm

(Example 7)
In Example 1, titanium carbide was changed to tantalum carbide.
Others were the same as Example 1.
The conditions for forming the tantalum carbide layer are as follows.
(Step of forming a carbide layer)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: Ta
Film thickness: 120nm

(Results of Examples 4 to 7)
In Examples 4 to 7, cracks occurred in the GaN layer during cooling in the HVPE apparatus, and the sapphire substrate and the GaN layer were separated.
Table 2 shows the results of dislocation density and curvature radius of Examples 4 to 7, including Example 1. The method for measuring the dislocation density and the radius of curvature is the same as described above.

The dislocation density of the GaN layers obtained in Examples 4 to 7 and Example 1 was 8 × 10 ⁶ cm ⁻² or less, and the radius of curvature was 8 m or more.

(Example 8)
A GaN layer was obtained by the method shown in FIGS.
As the base substrate, a sapphire (Al ₂ O ₃ ) substrate 10 having a thickness of 550 μm and a diameter of 3 inches was used.
Next, a titanium carbide layer 11 was formed on the sapphire substrate 10.
The film forming conditions for the titanium carbide layer 11 were as follows.

(Step of forming a carbide layer)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: Ti
Film thickness: 120nm

(Step of forming the GaN layer 121)
(First GaN layer)
The first GaN layer was composed of a GaN buffer layer (three-dimensional growth), a three-dimensional growth initial layer, and a three-dimensional growth control layer.
(GaN buffer layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 970 ° C.
Deposition gas: GaCl gas 180 cc / min, NH ₃ gas 3300 cc / min (V / III ratio = 10)
Thickness: 5μm
(3D initial layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 1040 ° C.
Deposition gas: GaCl gas 80 cc / min, NH ₃ gas 2400 cc / min (V / III ratio = 10)
Thickness: 10 μm
The three-dimensional initial layer grew three-dimensionally while forming facets.
(3D growth control layer)
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 1040 ° C.
Deposition gas: GaCl gas 180 cc / min, NH ₃ gas 1800 cc / min (V / III ratio = 10)
Thickness: 250 μm
The three-point growth suppression layer is a layer provided to stop the three-dimensional growth, and the crystal growth has shifted from the three-dimensional growth to the two-dimensional growth.

(Second GaN layer 122)
The second GaN layer is grown by two-dimensional growth, under the condition that the three-dimensional growth is suppressed and flat growth (growth in which the growth along the horizontal direction of the substrate is preferentially performed) is performed. Implemented growth. The pit density of the first GaN layer was 32 pieces / cm ² , whereas it decreased to 2 pieces / cm ² in the second GaN layer. The pit density was measured with a microscope.
Film formation method: HVPE (hydride vapor phase epitaxy) film formation temperature: 1040 ° C.
Deposition gas: GaCl gas 180 cc / min, NH ₃ gas 1800 cc / min (V / III ratio = 10)
Doping: Si-doped (dichlorosilane content _{3000ppm (Si 2 H 2 Cl 2} ) were mixed HCl3cc / min to 3 cc / min, was introduced into the HVPE apparatus.)
Thickness: 1100μm

(Peeling method)
The temperature in the HVPE apparatus in which the GaN layer was formed was lowered, and the sapphire substrate, carbide layer, and GaN layer were cooled to room temperature.

Example 9
In Example 8, a TiC-dispersed C film was formed on the carbide layer. Others were the same as in Example 8. The pit density of the first GaN layer was 50 / cm ² , whereas it decreased to 9 / cm ² in the second GaN layer. The pit density was measured with a microscope.

(Carbide layer)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 1.9sccm
Target: Ti
Film thickness: 120nm
Film quality: TiC

(TiC-containing C film)
Deposition method: Reactive sputtering Deposition temperature: 800 ° C
Pressure: 0.4Pa
Sputtering gas: Ar gas reactive gas: CH ₄
Reactive gas flow rate: 7.4 sccm
Target: Ti
Film thickness: 20nm
Film quality: TiC-dispersed C film

(Results of Examples 8 to 9)
In Examples 8 to 9, cracks occurred in the GaN layer during cooling with the HVPE apparatus, and the sapphire substrate and the GaN layer were separated.
Table 3 shows the results of dislocation density and radius of curvature of Examples 8 to 9. The method for measuring the dislocation density and the radius of curvature is the same as described above.

The dislocation density of the GaN layers obtained in Examples 8 to 9 was 5 × 10 ⁶ cm ⁻² or less, and the radius of curvature was 10 m or more.
FIG. 7 is a photograph of the GaN layer peeled in Example 9 and the sapphire substrate on which the GaN layer remains. The GaN layer remaining on the sapphire substrate receives the color tone of the TiC layer and is black.
FIG. 8 is a fluorescence micrograph of a cross section of the peeled GaN layer of Example 9 and the GaN layer remaining on the sapphire substrate side. The GaN layer remaining on the sapphire substrate side is occupied by three-dimensional growth by pit formation as shown in the dark region, and the peeled GaN layer cracked in a state including the end portion of the dark region, leading to peeling. To be judged.

Table 4 shows SIMS of Si and O in the dark region (three-dimensional growth portion) of the GaN layer remaining on the sapphire substrate side and the bright region (flat growth (two-dimensional growth) portion) of the separated GaN layer shown in FIG. The analysis results are shown. The SIMS analysis was performed at a predetermined part depth of 3 μm.

In the peeled GaN layer, O and Si were 1 × 10 ¹⁶ cm ⁻³ and 1 × 10 ¹⁷ cm ⁻³ at the background level, respectively, whereas in the GaN layer remaining on the sapphire substrate side, O was 4 It was detected at a high concentration such as × 10 ¹⁸ cm ⁻³ . O is considered to be generated from oxygen contained in the quartz structural member and the raw material gas inside the HVPE apparatus.
The pit density in the first GaN layer is higher than the pit density in the second GaN layer.

Table 5 shows the elastic modulus and dynamic hardness of the GaN layer remaining on the sapphire substrate side of Example 9 and the separated GaN layer.
Further, the elastic modulus and dynamic hardness of the GaN layer remaining on the sapphire substrate side are values obtained by measuring a three-dimensionally grown portion shown in the dark region of FIG. The elastic modulus and dynamic hardness of the peeled GaN layer are values obtained by measuring the flat growth portion shown in the bright region of FIG.
The elastic modulus and dynamic hardness were obtained from a load-unloading test with a constant test force P (mN) using a 115 ° triangular pyramid indenter using a Shimadzu dynamic micro hardness tester (DUH-W201). . The dynamic hardness (DH) is given by DH = α · P / D ² , and the elastic modulus (Young's modulus E) is obtained by E = σ / ε. α is a coefficient unique to the indenter, 3.8584, D is the indentation depth (μm), σ is the force per unit area (Pa), and ε is the rate of change in length. The test conditions were a test force of 250 mN, a load speed of 71 mN / second, and a load holding time of 2 seconds.

  The elastic modulus of the GaN layer remaining on the sapphire substrate side decreased to 1/10 or less and the dynamic hardness increased 1.6 times compared to the peeled GaN layer. As apparent from Table 4, in the GaN layer remaining on the sapphire substrate side, the elastic modulus and dynamic hardness are changed by doping O as an impurity in the three-dimensionally grown portion. It is presumed that a crack in the horizontal direction was induced in the layer, leading to good peeling.

(Example 10)
In Example 9, the thickness of the carbide layer was 20 nm.
Others are the same as in the ninth embodiment.

(Example 11)
In Example 9, the thickness of the carbide layer was 40 nm.
Others were the same as Example 9.

Example 12
In Example 9, the thickness of the carbide layer was 60 nm.
Others were the same as Example 9.

(Example 13)
In Example 9, the thickness of the carbide layer was 100 nm.
Others were the same as Example 9.

(Example 14)
In Example 9, the thickness of the carbide layer was 150 nm.
Others were the same as Example 9.

(Example 15)
In Example 9, the thickness of the carbide layer was 200 nm.
Others were the same as Example 9.

(Example 16)
In Example 9, the thickness of the carbide layer was 300 nm.
Others were the same as Example 9.

(Example 17)
In Example 9, the thickness of the carbide layer was 500 nm.
Others were the same as Example 9.

(Example 18)
In Example 9, the thickness of the carbide layer was 10 nm.
Others were the same as Example 9.

(Results of Examples 10 to 18)
In Examples 10 to 18, cracks occurred in the GaN layer during cooling in the HVPE apparatus, and the sapphire substrate and the GaN layer were separated.
FIG. 9 shows the relationship between the thickness of the TiC layer according to Examples 9 to 18 and the dislocation density of the GaN layer. The method for measuring the dislocation density is as described above. The dislocation density of the GaN layers in Examples 9 to 17 was 4 × 10 ⁶ cm ⁻² or less, whereas in Example 18, it was 1.7 × 10 ⁷ cm ⁻² . However, the radius of curvature was larger than that of Comparative Example 1.

(Example 19)
In Example 9, the GaN layer thickness was arbitrarily set in the range of 100 to 1500 μm, and the GaN layer was grown.
Others were the same as Example 9.

(Comparative Example 2)
In Comparative Example 1, the GaN layer thickness was arbitrarily set in the range of 100 to 3000 μm, and the GaN layer was grown.
Others were the same as those in Comparative Example 1.

(Results of Example 19 and Comparative Example 2)
In Example 19, when the film thickness of the GaN layer was 950 μm or more, cracks occurred in the GaN layer without applying external force during cooling in the HVPE apparatus, and the sapphire substrate and the GaN layer were separated. On the other hand, in Comparative Example 2, when the GaN layer film thickness was 700 μm or more, cracks occurred in the GaN layer during cooling with the HVPE apparatus, and the sapphire substrate and the GaN layer were separated, but cracks occurred.
FIG. 10 shows the relationship between the GaN layer thickness and the dislocation density according to Example 19 in comparison with the case of Comparative Example 2. The method for measuring the dislocation density is as described above. When the film thickness of the GaN layer in Example 19 was 265 μm or less, since it was only the first GaN layer, a large number of pits existed. In Example 19, it can be seen that the dislocation density decreases when the GaN layer film thickness is thin, and the change in the dislocation density is small as the GaN layer film thickness increases.

10 Ground substrate (sapphire substrate)
11 Titanium carbide layer (carbide layer)
111 First titanium carbide layer 112 Second titanium carbide layer (TiC-dispersed C film)
12 GaN layer (Group III nitride semiconductor layer)
12'GaN layer (Group III nitride semiconductor layer)
121 First GaN layer 122 Second GaN layer 123 Third GaN layer 124 Fourth GaN layer

Claims (9)

Forming a carbide layer selected from titanium carbide, zirconium carbide, hafnium carbide, vanadium carbide or tantalum carbide on a base substrate;
Growing a group III nitride semiconductor layer on the carbide layer;
A region above the surface of the group III nitride semiconductor layer of the carbide layer, causing cracks in the group III nitride semiconductor layer, removing the base substrate, and removing the group III nitride semiconductor And a method for producing a group III nitride semiconductor layer. In the manufacturing method of the group III nitride semiconductor layer according to claim 1,
In the step of growing the group III nitride semiconductor layer,
A method for producing a group III nitride semiconductor layer, wherein a crack promoting layer for forming a crack in the group III nitride semiconductor layer is formed in the group III nitride semiconductor layer. In the manufacturing method of the group III nitride semiconductor layer according to claim 2,
In the step of growing a group III nitride semiconductor layer on the carbide layer,
Forming the first group III nitride semiconductor layer containing the impurity and the crack promoting layer;
Forming a second group III nitride semiconductor layer having a different impurity concentration from the first group III nitride semiconductor layer on the first group III nitride semiconductor layer; Layer manufacturing method. In the manufacturing method of the group III nitride semiconductor layer according to claim 3,
The step of growing a group III nitride semiconductor layer on the carbide layer includes:
Forming a first undoped group III nitride semiconductor layer that is not doped with impurities;
Forming a group III nitride semiconductor layer doped with impurities on the first undoped group III nitride semiconductor layer as the first group III nitride semiconductor layer;
Forming a second undoped group III nitride semiconductor layer, which is not doped with impurities, as the second group III nitride semiconductor layer on the group III nitride semiconductor layer doped with impurities. Method for manufacturing a semiconductor layer. In the manufacturing method of the group III nitride semiconductor layer according to claim 3,
The step of forming the first group III nitride semiconductor layer includes:
Forming a group III nitride semiconductor layer by three-dimensional growth while forming pits,
In the step of forming the second group III nitride semiconductor layer, the second group III nitride semiconductor layer having a pit density lower than that of the first group III nitride semiconductor layer is formed by two-dimensional growth III. A method for manufacturing a group nitride semiconductor layer. In the manufacturing method of the group III nitride semiconductor layer according to any one of claims 3 to 5,
The method for producing a group III nitride semiconductor layer, wherein the impurity is Si or O. In the manufacturing method of the group III nitride semiconductor layer according to any one of claims 1 to 6,
A method of manufacturing a group III nitride semiconductor layer that does not include a step of forming a mask for growing a group III nitride semiconductor layer from an opening on the base substrate. In the manufacturing method of the group III nitride semiconductor layer according to any one of claims 1 to 7,
The method for manufacturing a group III nitride semiconductor layer, wherein the carbide layer is a titanium carbide layer. In the manufacturing method of the group III nitride semiconductor layer according to any one of claims 1 to 8,
The thickness of the said carbide layer is a manufacturing method of the group III nitride semiconductor layer which is 20 nm or more and 500 nm or less.

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