JP6906205B2 - Manufacturing method of semiconductor laminate and manufacturing method of nitride crystal substrate - Google Patents

Description

The present invention relates to a method for producing a semiconductor laminate and a method for producing a nitride crystal substrate.

As a method for producing a semiconductor laminate or a nitride crystal substrate made of a group III nitride semiconductor, a method of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on a predetermined seed crystal substrate by a vapor phase growth method is disclosed. (For example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2005-236261

In recent years, it has been desired to produce a semiconductor laminate or a nitride crystal substrate having better crystal quality than the conventional method.

An object of the present invention is to provide a technique capable of producing a semiconductor laminate or a nitride crystal substrate having good crystal quality.

According to one aspect of the invention
A step of preparing a seed crystal substrate in which at least the surface layer is made of a group III nitride semiconductor and the surface layer contains a sinus.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
Have,
In the etching step,
A method for producing a semiconductor laminate in which residual impurities remaining in the sinus of the seed crystal substrate in the step of preparing the seed crystal substrate are removed together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate. , And related techniques are provided.

According to the present invention, a semiconductor laminate or a nitride crystal substrate having good crystal quality can be produced.

It is a flowchart which shows the manufacturing method of the semiconductor laminate or the manufacturing method of the nitride crystal substrate which concerns on 1st Embodiment of this invention. It is a schematic block diagram of the liquid phase growth apparatus used in the manufacturing method which concerns on 1st Embodiment of this invention. (A) to (e) are schematic cross-sectional views showing a substrate preparation process. (A) is a schematic cross-sectional view showing a seed crystal substrate after a slicing step, (b) is a schematic cross-sectional view showing a seed crystal substrate in a polishing step, and (c) is a seed crystal substrate after a washing step. It is a schematic cross-sectional view which shows the crystal substrate. It is a schematic block diagram of the vapor phase growth apparatus used in the manufacturing method which concerns on 1st Embodiment of this invention. It is a figure which shows the temperature change of the seed crystal substrate from the etching process of 1st Embodiment to a vapor phase growth process. (A) is a schematic cross-sectional view showing how the residual impurities are vaporized from the inside of the seed crystal substrate, and (b) is a schematic view showing how the residual impurities deposited on the upper surface of the seed crystal substrate are removed together with GaN. It is a cross-sectional view, and (c) is a schematic cross-sectional view showing a seed crystal substrate after an etching step. (A) is a schematic cross-sectional view showing a semiconductor laminate in a vapor phase growth step, and (b) is a schematic cross-sectional view showing a nitride crystal substrate produced in a slicing step. (A) is a diagram showing a change in the flow velocity of the gas flowing on the upper surface of the seed crystal substrate from the etching step to the vapor phase growth step of the modification 1 of the first embodiment, and (b) is a diagram showing the change in the flow velocity of the gas flowing on the upper surface of the seed crystal substrate, and (b) is a diagram showing the change in the flow velocity of the gas flowing on the upper surface of the seed crystal substrate. It is a figure which shows the pressure change in the processing chamber in the etching process and the gas phase growth process of the modification 2 of. It is a flowchart which shows the manufacturing method of the semiconductor laminate or the manufacturing method of the nitride crystal substrate which concerns on 2nd Embodiment of this invention. (A) is a diagram showing the temperature change of the seed crystal substrate from the vaporization step to the gas phase growth step of the second embodiment, and (b) is a diagram showing the temperature change from the vaporization step to the gas phase growth step of the second embodiment. It is a figure which shows the flow velocity change of the gas flowing on the upper surface of a seed crystal substrate. It is a figure which shows the temperature change of the seed crystal substrate from the vaporization step to the vapor phase growth step of the modification 1 of the 2nd Embodiment. (A) is a diagram showing the pressure change in the processing chamber from the vaporization step of the modified example 3 of the second embodiment to the vapor phase growth step, and (b) is the vaporization step of the modified example 4 of the second embodiment. It is a figure which shows the pressure change in a processing chamber from to a vapor phase growth process. It is a flowchart which shows the manufacturing method of the semiconductor laminate or the manufacturing method of the nitride crystal substrate which concerns on 3rd Embodiment of this invention. It is a figure which shows the temperature change of the seed crystal substrate from the etching process of 3rd Embodiment to the vapor phase growth process. (A) is a differential interference contrast image of the cross section of the seed crystal substrate, and (b) is a fluorescence image of the cross section of the seed crystal substrate. It is an SEM image of the cross section of the seed crystal substrate. It is an SEM image and a cathode luminescence image of the cross section of a seed crystal substrate. It is a cathode luminescence image of the cross section of the seed crystal substrate. (A) is a differential interference contrast image of the upper surface of the seed crystal substrate, (b) is a differential interference contrast image of the upper surface of the seed crystal substrate of Comparative Example 1 after the vaporization step, and (c) is the differential interference contrast image of the upper surface of the seed crystal substrate after the etching step. It is a differential interference contrast image of the upper surface of the seed crystal substrate of Comparative Example 1. (A) is a differential interference contrast image of the upper surface of the seed crystal substrate of Example 1 after the vaporization step, and (b) is a differential interference contrast image of the upper surface of the seed crystal substrate of Example 1 after the etching step. (A) is a photograph showing the appearance of the semiconductor laminate of Example 2, (b) is a cathodoluminescence image of the semiconductor laminate of Example 2, and (c) is a semiconductor laminate of Comparative Example 2. It is a photograph showing the appearance of an object, and (d) is a cathodoluminescence image of the semiconductor laminate of Comparative Example 2. (A) is a photograph showing the appearance of the semiconductor laminate of Example 3, (b) is a cathodoluminescence image of the semiconductor laminate of Example 3, and (c) is a semiconductor laminate of Example 4. It is a photograph showing the appearance of an object, and (d) is a cathodoluminescence image of the semiconductor laminate of Example 4. (A) is a photograph showing the appearance of the semiconductor laminate of Comparative Example 3, (b) is a cathodoluminescence image of the semiconductor laminate of Comparative Example 3, and (c) is a semiconductor laminate of Comparative Example 4. It is a photograph showing the appearance of an object, and (d) is a cathodoluminescence image of the semiconductor laminate of Comparative Example 4.

<Knowledge obtained by inventors>
First, the findings obtained by the inventors will be described.

As a method for growing a crystal made of a group III nitride semiconductor, for example, a liquid phase growth method and a vapor phase growth method are known. In the liquid phase growth method, crystals with a low dislocation density can be obtained because the crystal growth proceeds thermodynamically in a state close to an equilibrium state. Currently, it is possible to obtain an at least partially crystalline dislocation density of 10 ³ / cm ² approximately. However, in the liquid phase growth method, it tends to be difficult to increase the growth rate. On the other hand, in the vapor phase growth method, although the growth rate can be increased, it tends to be difficult to reduce the dislocation density in the crystal.

Therefore, in order to solve these problems, a method using a liquid phase growth method and a vapor phase growth method in this order is known (for example, Patent Document 1 described above). By using the liquid phase growth method and the vapor phase growth method in this order, a crystal having a low dislocation density can be obtained, and the productivity thereof can be improved.

The inventors, etc., have studied diligently, and the conventional methods using the liquid phase growth method and the vapor phase growth method in this order may cause the following problems in further improving the crystal quality. I found.

Here, the crystal growth process by the liquid phase growth method, the vapor phase growth method, and the like will be described. In the crystal growth process, first, the molecules or atoms of the raw material adhere to the upper surface of the substrate. Raw material molecules or atoms adhering to the upper surface of the substrate move (migrate) on the upper surface of the substrate. Some of the raw material molecules or atoms that move on the substrate are desorbed from the substrate, and the other parts gather on the substrate to form clusters and become crystal nuclei. Molecules or atoms of the raw material are further attached to the edges (kinks) of the crystal nuclei, and the crystal nuclei become larger. When the area of the crystal nuclei becomes equal to or larger than a predetermined value, the crystal nuclei become difficult to detach from the substrate. The crystal nuclei expand in the creeping direction of the substrate to form atomic steps. Meanwhile, crystal nuclei are also formed on the terrace of the atomic step. By repeating these steps, the crystal grows in a step flow.

In the liquid phase growth method, when a crystal is step-flow-grown, if there is a difference in the growth rate of each of the plurality of atomic steps, the plurality of atomic steps may be aggregated and step bunching on the order of microns may occur. .. When step bunching occurs in the crystal, the raw material of the liquid phase growth method begins to accumulate at the end of the step bunching. If the crystal growth is continued while the raw materials of the liquid phase growth method are accumulated in the crystal, the crystals grow so as to protrude onto the accumulated raw materials, and the accumulated raw materials are confined. Therefore, inclusions derived from the raw material of the liquid phase growth method are formed. As the crystal growth progresses further, the inclusion is confined between the crystal portion that has grown so as to protrude onto the inclusion and the crystal portion that has grown in the creeping direction of the substrate adjacent to the inclusion, and in the normal direction of the substrate. On the other hand, it extends in an oblique direction. Therefore, intricately intricate cavities (including cavities, voids, grooves, etc.) are formed in the crystal by inclusion.

After obtaining an ingot composed of crystals in which such a cavity is formed, the ingot is fixed to a predetermined support member with wax and sliced with a cutting fluid to prepare a plurality of seed crystal substrates. There is a possibility that a cavity opens on the upper surface or the lower surface of the seed crystal substrate, and wax or cutting fluid may infiltrate and remain in the cavity of the seed crystal substrate. Further, when the seed crystal substrate is fixed to a predetermined support member with wax and polished with a polishing liquid and an abrasive, the wax, the polishing liquid or the polishing material may infiltrate and remain in the sinus of the seed crystal substrate. There is sex. Further, when the seed crystal substrate is washed with a predetermined cleaning liquid, the cleaning liquid may infiltrate into the sinus of the seed crystal substrate and remain. Further, if the cleaning is insufficient, inclusions and the like may remain in the sinus of the seed crystal substrate.

Then, when the semiconductor layer is grown on the seed crystal substrate that has undergone the above steps by the vapor phase growth method, at least one of inclusions, waxes, cutting fluids, polishing liquids, abrasives, and cleaning liquids remaining in the sinus of the seed crystal substrate is used. Outgas can be generated from residual impurities (contaminants) including cutting fluid. At least a part of the residual impurities discharged from the sinus of the seed crystal substrate as outgas can be redeposited and precipitated on the upper surface of the seed crystal substrate.

The surface energy of the residual impurities deposited on the upper surface of the seed crystal substrate is different from the surface energy of the upper surface of the seed crystal substrate. Therefore, the crystal nuclei may grow in a direction different from the crystal orientation of the seed crystal substrate, starting from the residual impurities precipitated on the upper surface of the seed crystal substrate. When the growth direction of the crystal nuclei changes in this way, there is a possibility that the associating crystal planes may be tilted or the lattices of the associating crystals may be displaced at the meeting part of the atomic step that has grown in the step flow. be. As a result, dislocations may occur at the meeting site.

Further, there is a possibility that crystal nuclei are preferentially formed on the residual impurities precipitated on the upper surface of the seed crystal substrate. Therefore, the semiconductor layer may grow abnormally starting from the precipitated residual impurities.

On the other hand, it may be difficult for crystal nuclei to be formed on the residual impurities precipitated on the upper surface of the seed crystal substrate. Therefore, there is a possibility that a non-growth region in which the semiconductor layer does not grow is formed starting from the precipitated residual impurities.

Further, when residual impurities are deposited on the upper surface of the seed crystal substrate, normal step flow growth is inhibited and three-dimensional island-like growth may occur. Therefore, when the crystal nuclei become large and the island-shaped crystals associate with each other, tensile stress may occur at the meeting surface. As a result, the crystal plane of the semiconductor layer may be warped. For the model in which tensile stress is introduced at the time of association of island-shaped crystals, refer to R. W. Hoffman, Surf. Interface Anal. , 3 (1981) 62.

In order to suppress the above phenomenon during the growth of the semiconductor layer, it is conceivable to directly etch (remove) the residual impurities remaining in the sinus of the seed crystal substrate before the growth of the semiconductor layer. However, even if an attempt is made to directly etch the residual impurities, it is difficult to completely remove the residual impurities.

This is because the residual impurities remaining in the sinus of the seed crystal substrate may contain various materials as described above. Therefore, it is difficult to specify the material constituting the residual impurities in advance, and it is difficult to select an etching method and conditions suitable for the material. Further, since the sinus of the seed crystal substrate is complicatedly intricate, it is difficult to reach the etching medium (solvent or etching gas) to the residual impurities remaining in the depth of the cavity. As a result, even if an attempt is made to directly etch the residual impurities, it becomes difficult to completely remove the residual impurities.

The present invention described below is based on the above-mentioned new problems found by the present inventors and the like.

<First Embodiment of the present invention>
Hereinafter, the first embodiment of the present invention will be described with reference to the drawings.

(1) Method for Manufacturing Semiconductor Laminate or Method for Manufacturing Nitride Crystal Substrate With reference to FIGS. 1 to 8, a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride crystal substrate according to the present embodiment will be described. FIG. 1 is a flowchart showing a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride crystal substrate according to the present embodiment. The step is abbreviated as S. FIG. 2 is a schematic configuration diagram of a liquid phase growth apparatus used in the production method according to the present embodiment. 3A to 3E are schematic cross-sectional views showing a substrate preparation process. FIG. 4A is a schematic cross-sectional view showing the seed crystal substrate after the slicing step, FIG. 4B is a schematic cross-sectional view showing the seed crystal substrate in the polishing step, and FIG. 4C is a schematic cross-sectional view showing the seed crystal substrate after the cleaning step. It is a schematic cross-sectional view which shows the seed crystal substrate of. FIG. 5 is a schematic configuration diagram of a vapor phase growth apparatus used in the manufacturing method according to the present embodiment. FIG. 6 is a diagram showing the temperature change of the seed crystal substrate from the etching step to the vapor phase growth step of the present embodiment. FIG. 7 (a) is a schematic cross-sectional view showing how residual impurities are vaporized from the inside of the seed crystal substrate, and FIG. 7 (b) shows how residual impurities deposited on the surface of the seed crystal substrate are removed together with GaN. It is a schematic cross-sectional view which shows, and (c) is a schematic cross-sectional view which shows the seed crystal substrate after an etching process. FIG. 8A is a schematic cross-sectional view showing a semiconductor laminate in the vapor phase growth step, and FIG. 8B is a schematic cross-sectional view showing a nitride crystal substrate produced in the slicing step.

In the following, in various substrates and the like used in the present embodiment, the upper main surface (front surface) is referred to as "upper surface", and the lower main surface (back surface) is referred to as "lower surface".

In the present embodiment, a case where, for example, a semiconductor laminate 1 or a nitride crystal substrate 2 made of gallium nitride (GaN) is manufactured as a group III nitride semiconductor will be described.

(S110: Substrate preparation process)
First, a substrate preparation step S110 is performed in which at least the surface layer is made of a group III nitride semiconductor, and the seed crystal substrate 20 (hereinafter, abbreviated as “substrate 20”) having the surface layer including the sinus 20a is prepared. In the present embodiment, as an example, a substrate 20 made of a group III nitride semiconductor whose surface layer is formed by a liquid phase growth method is prepared.

The substrate preparation step S110 of the present embodiment includes, for example, a liquid phase growth step S112, a slicing step S114, a polishing step S116, and a cleaning step S118. The slicing step S114, the polishing step S116, and the cleaning step S118 constitute a crystal processing step. In the present embodiment, for example, the substrate 20 is produced by the multipoint seed bonding method as follows.

(S112: Liquid phase growth step)
First, as shown in FIG. 3A, for example, a multipoint seed substrate 10 (MPS substrate 10) is prepared. The MPS substrate 10 has a support substrate 11 and a point seed portion 12 (PS portion 12). The support substrate 11 is made of, for example, sapphire. The PS portions 12 are arranged on the support substrate 11 at predetermined intervals. The PS portion 12 is formed by, for example, a vapor phase growth method. Further, the upper surface of the PS portion 12 is, for example, a (0001) plane (+ c plane) or a plane having a predetermined off angle with respect to the (0001) plane. The size of the off angle (off amount) is, for example, within 2 °. The dislocation density (average dislocation density) on the upper surface of the PS portion 12 is, for example, 1 × 10 ⁷ pieces / cm ² or more and 1 × 10 ⁹ pieces / cm ² or less.

Next, using the liquid phase growth apparatus 300 shown in FIG. 2, the liquid phase growth layer 14 made of a group III nitride semiconductor is grown on the MPS substrate 10.

The liquid phase growth device 300 of the present embodiment is configured as, for example, a growth device by the flux method. The liquid phase growth device 300 includes a pressure-resistant container 303 made of stainless steel (SUS) or the like and having a pressurizing chamber 301 inside. The inside of the pressurizing chamber 301 is configured so that the pressure can be increased to a high pressure state of, for example, about 5 MPa. A crucible 308, a heater 307 for heating the inside of the crucible 308, and a temperature sensor 309 for measuring the temperature inside the pressurizing chamber 301 are provided in the pressurizing chamber 301. The crucible 308 contains, for example, a Group III raw material solution in which an alkali metal or a transition metal is used as a solvent (flux), and a substrate (for example, MPS substrate 10) is used as a raw material with its main surface (crystal growth surface) facing upward. It is configured so that it can be immersed in a solution. _{A gas supply pipe 332 for supplying nitrogen (N 2} ) gas or ammonia (NH ₃ ) gas (or a mixed gas thereof) into the pressurizing chamber 301 is connected to the pressure-resistant container 303. The gas supply pipe 332 is provided with a pressure control device 333, a flow rate controller 341, and a valve 343 in this order from the upstream side. Each member included in the liquid phase growth apparatus 300 is connected to a controller 380 configured as a computer, and is configured so that a processing procedure and processing conditions described later are controlled by a program executed on the controller 380. There is.

The liquid phase growth step S112 can be carried out by using the liquid phase growth apparatus 300 described above, for example, by the following processing procedure.

After preparing the MPS substrate 10, for example, sodium (Na) as a flux raw material, Ga as a group III raw material, and the MPS substrate 10 described above are housed in the crucible 308, and the pressure-resistant container 303 is sealed. Then, by starting the heating by the heater 307, a raw material solution (Ga solution using Na as a medium) is generated in the crucible 308, and a state in which the MPS substrate 10 is immersed in the raw material solution is generated. In this state, N ₂ gas (or _{a mixed gas of NH 3} gas and N ₂ gas) is supplied into the pressurizing chamber 301, nitrogen (N) is dissolved in the raw material solution, and this state is maintained for a predetermined time. ..

As a result, as shown in FIG. 3B, the liquid phase growth layer 14 made of GaN is epitaxially grown on the PS portion 12 of the MPS substrate 10. In the early stage of growth, the liquid phase growth layer 14 grows as island-like crystals separated from each other. As the growth of the liquid phase growth layer 14 progresses, the island-shaped crystals become larger and the adjacent crystals associate with each other to form the liquid phase growth layer 14 as a continuous film (FIG. 3 (c)).

When the growth of the liquid phase growth layer 14 having a predetermined thickness is completed, the pressure-resistant container 303 is returned to the atmospheric pressure, and the MPS substrate 10 on which the liquid phase growth layer 14 is formed is taken out from the crucible 308.

At this time, when the temperature of the MPS substrate 10 is lowered, as shown in FIG. 3D, the stress caused by the difference in the coefficient of linear expansion between the support substrate 11 and the liquid phase growth layer 14 causes the support substrate 11 to start. The liquid phase growth layer 14 spontaneously peels off. As a result, the ingot 16 composed of the liquid phase growth layer 14 is produced.

The following are examples of processing conditions when the liquid phase growth step S112 is carried out.
Film formation temperature (temperature of raw material solution): 600 to 1200 ° C., preferably 800 to 900 ° C.
Film formation pressure (pressure in the pressurizing chamber): 0.1 to 10 MPa, preferably 1 to 6 MPa
Ga concentration in the raw material solution [Ga / (Na + Ga)]: 5 to 70%, preferably 10 to 50%.

At this time, by performing the liquid phase growth step S112 under the above conditions, the growth of the liquid phase growth layer 14 proceeds in a state thermodynamically close to the equilibrium state, so that the dislocation density is lower than that of the PS portion 12 of the MPS substrate 10. Liquid phase growth layer 14 can be obtained. Specifically, the dislocation density on the upper surface of the liquid phase growth layer 14 can be, for example, 1 × 10 ⁶ pieces / cm ² or less, preferably 5 × 10 ⁵ pieces / cm ² or less. The lower limit of the dislocation density on the upper surface of the liquid phase growth layer 14 is not limited because the lower it is, the better. However, since there is a possibility that at least one penetrating dislocation is formed in the liquid phase growth layer 14 for each PS portion 12, for example, when the MPS substrate 10 having a pitch of the PS portion 12 of 500 μm is used. The lower limit of the dislocation density on the upper surface of the liquid phase growth layer 14 is considered to be ^{, for example, about 400 pieces / cm 2.}

On the other hand, at this time, when the liquid phase growth step S112 is performed under the above conditions, the amount of N dissolved in the raw material solution is small, so that the growth rate of the liquid phase growth layer 14 by the liquid phase growth method is the vapor phase growth method. Is lower than the growth rate of. Specifically, the growth rate of the liquid phase growth layer 14 is, for example, 3 μm / h or more and 30 μm / h or less.

Since the growth rate of the liquid phase growth layer 14 is low in this way, if a large number of final nitride crystal substrates 2 are to be obtained only from the liquid phase growth layer 14, a considerable growth time will be required. Become. Therefore, in the present embodiment, in the slicing step S114 described later, one or more and five or less substrates 20 are cut out from the liquid phase growth layer 14 formed in the liquid phase growth step S112. Therefore, the thickness of the liquid phase growth layer 14 formed in the liquid phase growth step S112 is set so that, for example, one or more and five or less substrates 20 can be cut out from the liquid phase growth layer 14. Specifically, the thickness of the liquid phase growth layer 14 is set to, for example, 0.5 mm or more and 5 mm or less, preferably 0.5 mm or more and 3 mm or less.

(S114: Slicing process)
Next, as shown in FIG. 3 (e), the ingot 16 is sliced (cut out) using a cutting fluid in a state of being fixed with wax to prepare a plurality of substrates 20 as GaN free-standing substrates.

At this time, the thickness of the substrate 20 sliced from the liquid phase growth layer 14 depends on the diameter of the substrate 20, but is, for example, 300 μm or more and 1 mm or less. Typically, when the diameter of the substrate 20 is 2 inches, the thickness of the substrate 20 is 300 μm or more and 450 μm or less.

As described above, by forming the substrate 20 by slicing from the liquid phase growth layer 14 epitaxially grown on the upper surface of the MPS substrate 10, the upper surface of the substrate 20 is the same as the upper surface of the PS portion 12 of the MPS substrate 10. , (0001) plane, or a plane having a predetermined off angle with respect to the (0001) plane.

In the liquid phase growth step S112 described above, the liquid phase growth layer 14 has a lower dislocation density as the growth progresses. Therefore, the more the sliced portion of the substrate 20 is the upper layer of the liquid phase growth layer 14, the more the dislocation of the substrate 20. The density will be low. Therefore, in the steps after the slicing step S114, the substrate 20 sliced from the uppermost layer of the liquid phase growth layer 14 is used.

The dislocation density on the upper surface of the substrate 20 can be, for example, 1 × 10 ⁶ pieces / cm ² or less, preferably 5 × 10 ⁵ pieces / cm ² or less. The lower limit of the dislocation density on the upper surface of the substrate 20 is not limited because the lower the value, the lower the dislocation density, but the lower limit of the dislocation density on the upper surface of the liquid phase growth layer 14 is, for example, 400 pieces /. It is considered to be about ^{cm 2.}

Here, as shown in FIG. 4A, intricately intricate cavities 20a (including grooves and the like) can be formed on the substrate 20 by inclusions generated during crystal growth using the liquid phase growth method. At least a part of the cavity 20a is open to the upper surface or the lower surface of the substrate 20. Further, the cavity 20a is recessed from the upper surface side to the lower surface side of the substrate 20, conversely recessed from the lower surface side to the upper surface side of the substrate 20, or is recessed from the lower surface side to the upper surface side of the substrate 20. It may penetrate. In addition, a plurality of dongs 20a may be formed in combination. Such a cavity 20a may cause a decrease in crystal quality in a subsequent process.

(S116: Polishing process)
Since the upper surface and the lower surface of the substrate 20 after the slicing step S114 are rough, at least the upper surface of the substrate 20 is polished using a predetermined polishing device.

Specifically, first, as shown in FIG. 4B, the substrate 20 is fixed to a predetermined support member 500 with wax 30. With the substrate 20 fixed to the support member 500, the support member 500 is rotated to polish the upper surface of the substrate 20 with a polishing liquid and an abrasive. As a result, the upper surface of the substrate 20 becomes an epiready surface (mirror surface). Specifically, the surface roughness of the upper surface of the substrate 20 is set to, for example, 5 nm or less, preferably 2 nm or less.

Here, as shown in FIG. 4B, for example, when the substrate 20 is fixed to the support member 500 with the wax 30, the wax 30 enters the cavity 20a of the substrate 20 by a capillary phenomenon. Therefore, the wax 30 is filled in every detail in the cave 20a.

(S118: Cleaning process)
Next, the substrate 20 after the polishing step S116 is washed. Specifically, the wax 30 used in the polishing step S116 is removed by cleaning the substrate 20 with a cleaning liquid composed of a predetermined organic solvent. Further, by cleaning the substrate 20 with a cleaning liquid composed of a predetermined acid solvent or alkaline solvent, the residue of the flux raw material exposed on the upper surface of the substrate 20 or remaining in the cavity 20a of the substrate 20 is removed. ..

However, as shown in FIG. 4C, since the cavities 20a formed in the substrate 20 are intricately intricate, even if wet cleaning is performed with a predetermined cleaning liquid in the cleaning step S118 described above, the substrate 20 Residual impurities 31 remain in the details of the cave 20a.

The "residual impurity 31" referred to here is derived from, for example, a part of the inclusions (Na or Ga / Na alloy) formed in the substrate 20 in the liquid phase growth step S112, and the wax or cutting fluid used in the slicing step S114. It contains at least one of the impurities to be added, the wax 30 used in the polishing step S116, the residue derived from the polishing liquid or the polishing material, and the residue derived from the cleaning liquid used in the cleaning step S118.

Further, as described above, the “cave 20a” here includes not only a cave that is at least partially opened on the upper surface or the lower surface of the substrate 20, but also a cave that is closed without an opening. Further, the "cave 20a" includes a cave containing at least a part of the residual impurities 31, a cave whose entire interior is filled with the residual impurities 31, or an empty cave.

When the semiconductor layer 40 is grown on the substrate 20 by the vapor phase growth method with the residual impurities 31 remaining in the cavities 20a of the substrate 20 in this way, outgas can be generated from the residual impurities 31. At least a part of the residual impurities 31 discharged from the cavity 20a of the substrate 20 as outgas can be redeposited and deposited on the upper surface of the substrate 20. Therefore, the crystal nuclei may grow in an orientation different from the crystal orientation of the substrate 20 starting from the residual impurities 31 precipitated on the upper surface of the substrate 20. As a result, dislocations may occur at the meeting part of the atomic step that has grown in the step flow due to the displacement of the crystal lattice or the like. Alternatively, the semiconductor layer 40 may grow abnormally starting from the residual impurities 31 precipitated on the upper surface of the substrate 20, or conversely, a non-growth region in which the semiconductor layer 40 does not grow may be formed. Alternatively, when the residual impurities 31 are deposited on the upper surface of the substrate 20, the step flow growth is inhibited and three-dimensional island-like growth may occur. Therefore, when the islands meet, tensile stress is generated at the meeting surface, and the crystal plane (c plane) of the semiconductor layer 40 may be warped.

Therefore, in the present embodiment, the following etching step S130 is performed before the vapor phase growth step S140.

(S130: Etching process)
In the present embodiment, for example, the vapor phase growth apparatus 400 shown in FIG. 5 is used to perform an etching step S130 in which an exposed portion of the substrate 20 is etched in the vapor phase.

The vapor phase growth apparatus 400 is configured as, for example, a hydride vapor phase growth apparatus (HVPE apparatus). The vapor phase growth apparatus 400 includes an airtight container 403 made of a heat-resistant material such as quartz and having a processing chamber 401 inside. A susceptor 408 for holding the substrate 20 is provided in the processing chamber 401. The susceptor 408 is connected to a rotation shaft 415 of the rotation mechanism 416, and the substrate 20 mounted on the susceptor 408 is configured to be rotatable in the circumferential direction (direction along the upper surface). At one end of the airtight container 403, a gas supply pipe 432a for supplying hydrogen chloride (HCl) gas to be described later gas generator vessel 433a, the process chamber gas supply pipe for supplying the NH ₃ gas as the film forming gas into the 401 432b , A gas supply pipe 432c for supplying HCl gas as an etching gas into the processing chamber 401 is connected, respectively. _{In addition to the HCl gas and NH 3} gas, the gas supply pipes 432a to 432c use _{hydrogen (H 2} ) gas as a carrier gas or etching _{gas, and N 2} gas as an inert gas, carrier gas or purge gas. It is also configured to be available for supply. The gas supply pipes 432a to 432c are provided with a flow rate controller and a valve (none of which are shown) for each of these gas types, and flow control and supply start / stop of various gases are individually performed for each gas type. It is configured so that it can be done. A gas generator 433a for accommodating a Ga melt as a raw material is provided downstream of the gas supply pipe 432a. The gas generator 433a has a nozzle 449a that supplies gallium chloride (GaCl) gas as a film-forming gas generated by the reaction of HCl gas and Ga melt toward the substrate 20 held on the susceptor 408. It is connected. Nozzles 449b and 449c that supply the gas supplied from these gas supply pipes toward the substrate 20 held on the susceptor 408 are connected to the downstream sides of the gas supply pipes 432b and 432c, respectively. The nozzles 449a to 449c are arranged so as to allow gas to flow in a direction parallel to the upper surface of the substrate 20 (direction along the upper surface). On the other hand, at the other end of the airtight container 403, an exhaust pipe 430 for exhausting the inside of the processing chamber 401 is provided. The exhaust pipe 430 is provided with a pump 431 via a pressure regulator (APC) 429. A zone heater 407 that heats the substrate 20 held in the gas generator 433a or the susceptor 408 to a desired temperature is provided on the outer periphery of the airtight container 403, and the temperature in the processing chamber 401 is measured in the airtight container 403. Sensors 409 are provided respectively. Each member of the vapor phase growth apparatus 400 is connected to a controller 480 configured as a computer, and is configured so that a processing procedure and processing conditions described later are controlled by a program executed on the controller 480. There is.

The etching step S130 can be carried out by using the above-mentioned vapor phase growth apparatus 400, for example, by the following processing procedure.

First, the substrate 20 is put into (carried in) into the airtight container 403 and held on the susceptor 408. At this time, the Ga melt as a raw material used in the vapor phase growth step S140, which will be described later, is housed in the gas generator 433a. Then, from at least one of the gas supply pipe 432a~432c into the process chamber 401 to supply _{N 2} gas, to implement the heating and evacuation of the processing chamber 401. At this time, the rotation of the susceptor 408 also starts.

As shown in FIG. 6, the temperature of the substrate 20 gradually rises due to the heating in the processing chamber 401. When the temperature of the substrate 20 reaches a predetermined temperature Te and the pressure in the processing chamber 401 reaches a predetermined pressure, a predetermined etching gas is supplied to the upper surface of the substrate 20.

As a result, the exposed portion of the substrate 20 can be etched in the gas phase. The exposed portion of the substrate 20 referred to here means a portion that is exposed to the outer atmosphere of the substrate 20 and can come into contact with the outer atmosphere (for example, etching gas). Specifically, the exposed portion of the substrate 20 includes the upper surface of the substrate 20 and the side surface of the substrate 20, and may include at least a part of the inner wall of the cavity 20a of the substrate 20.

At this time, in the etching step S130, for example, the residual impurities 31 remaining in the cavity 20a opened on the upper surface of the substrate 20 are removed together with the GaN constituting the substrate 20 by the following mechanism.

As shown in FIG. 7A, by heating the substrate 20 to a predetermined temperature Te in the etching step S130, at least a part of the residual impurities 31 is vaporized (welled out) from the inside of the cavity 20a of the substrate 20. At least a part of the residual impurities 31 vaporized in the cave 20a reaches the opening of the cave 20a through the cave 20a. At least a part of the residual impurities 31 that have reached the opening of the cavity 20a is discharged to the outside of the substrate 20 by the etching gas. On the other hand, the other portion of the residual impurities 31 is ejected from the opening of the cave 20a on the upper surface of the substrate 20 and reattached and deposited in the vicinity of the opening. The other portion of the residual impurity 31 may be redeposited and deposited on a portion of the upper surface of the substrate 20 other than the vicinity of the opening of the cavity 20a.

Further, as shown in FIG. 7B, the exposed portion of the substrate 20 is etched with the etching gas supplied in the etching step S130. As the etching of the upper surface of the substrate 20 progresses, the etching gas also enters between at least a part of the residual impurities 31 deposited on the upper surface of the substrate 20 and the upper surface of the substrate 20. When the portion of the upper surface of the substrate 20 in contact with the residual impurities 31 is etched, the residual impurities 31 are gradually peeled off from the upper surface of the substrate 20. The peeled residual impurities 31 are removed (discharged) to the outside of the substrate 20 according to the flow of the etching gas with respect to the upper surface of the substrate 20.

As described above, in the present embodiment, the processes shown in FIGS. 7A and 7B occur continuously or simultaneously to reduce the residual impurities 31 in the cavity 20a of the substrate 20, and the vapor phase growth described later. In step S140, it can be withered to the extent that outgas is not released from the cave 20a. Further, the residual impurities 31 precipitated on the upper surface of the substrate 20 can be removed together with the GaN constituting the matrix of the substrate 20.

In the above process of removing the residual impurities 31 together with the matrix of the substrate 10, it is considered that the residual impurities 31 are removed together with the GaN by a principle similar to the so-called "lift-off" used for patterning a metal film or the like in the semiconductor process. You may.

In the etching step S130 of the present embodiment, for example, the exposed portion of the substrate 20 is etched under the condition that the region of the upper surface of the substrate 20 excluding the crystal defect portion is smooth. The "crystal defect portion" of the substrate 20 here means dislocations, pits, and the like. Further, the "condition in which the region of the upper surface of the substrate 20 excluding the crystal defect portion is smooth" is the region of the upper surface of the substrate 20 excluding the crystal defect portion, that is, the field of view not including the etching pit ( For example, when compared in a 1 μm square field), the difference between the surface roughness before the etching step S130 (arithmetic mean roughness Ra) and the surface roughness after the etching step S130 is within 10 nm, preferably within 5 nm. That is. Even when etching is performed under the above conditions, a predetermined facet may occur at the crystal defect portion on the upper surface of the substrate 20. By keeping the upper surface of the substrate 20 smooth under such mild etching conditions, the semiconductor layer 40 can be smoothly epitaxially grown on the upper surface of the substrate 20 in the vapor phase growth step S140 described later.

Specific etching conditions, for example, etched in an atmosphere containing HCl gas and H ₂ gas as the etching gas. For example, the upper surface of the substrate 20 from the gas supply pipe 432c, and supplies the HCl gas and _{H 2} gas as the etching gas. By etching in an atmosphere containing HCl gas, the GaN constituting the substrate 20 can be etched by the following reaction formula (1).
2GaN + 2HCl → 2GaCl + H ₂ + N ₂ ... (1)
At this time, Ga droplets may be generated as a by-product of a reaction other than the reaction formula (1). Here, since the mild etching conditions are applied as described above, the above-mentioned Ga droplets are likely to occur. _{Therefore, by etching in an atmosphere containing H 2} gas in addition to HCl gas, Ga droplet as a by-product can be vaporized and removed as _{galan (GaH 3) which is a hydride of Ga.} ..

Further, for example, in addition to the above-mentioned HCl gas and H ₂ gas as the etching gas, etching is performed in an atmosphere containing _{N 2} gas as an inert gas (diluting gas), and the partial pressure of the _{N 2 gas is divided into the HCl gas and the H 2 gas.} H ₂ higher than the respective partial pressures of the gas. As a result, the exposed portion of the substrate 20 can be mildly etched, and the region of the upper surface of the substrate 20 excluding the crystal defect portion can be kept smooth.

At this time, the ratio of the partial pressures of the HCl gas and the H _{2 gas to the partial pressure of the N 2} gas (partial pressure ratio) is, for example, 1% or more and 10% or less. If the partial pressure ratio is less than 1%, the etching rate of the GaN constituting the substrate 20 becomes low, so that the time until the residual impurities 31 are removed may become excessively long. On the other hand, by setting the partial pressure ratio to 1% or more, the etching rate of the GaN constituting the substrate 20 is secured to a predetermined value or more, and the lengthening of the time until the residual impurities 31 are removed is suppressed. Can be done. On the other hand, if the partial pressure ratio is more than 10%, the GaN constituting the substrate 20 is excessively etched, so that the upper surface of the substrate 20 may be roughened. On the other hand, by setting the partial pressure ratio to 10% or less, the exposed portion of the substrate 20 can be mildly etched, and the region of the upper surface of the substrate 20 excluding the crystal defect portion can be kept smooth.

Further, for example, etching is performed under an atmosphere in which the free NH ₃ gas. When _{etching is performed in an atmosphere containing NH 3} gas, GaN constituting the substrate 20, Ga-containing gas (GaCl or GaH _{3 ) generated by the reaction with each of HCl gas and H 2} gas, and NH ₃ gas Reacts and GaN re-grows on the exposed portion of the substrate 20. Since the regrown GaN is formed in an irregular shape, the upper surface of the substrate 20 may be roughened. In contrast, by performing the etching in an atmosphere which is a non-containing NH ₃ gas, it is possible to suppress the regrowth of GaN. As a result, the upper surface of the substrate 20 can be kept smooth.

Further, the temperature (etching temperature) Te of the substrate 20 in the etching step S130 is set to, for example, a critical temperature or higher at which the GaN constituting the substrate 20 starts to be etched. As a result, the residual impurities 31 in the cavities 20a of the substrate 20 can be removed while etching the GaN constituting the matrix of the substrate 20.

On the other hand, as shown in FIG. 6, the etching temperature Te of the substrate 20 in the etching step S130 is set lower than, for example, the temperature (deposition temperature) Tg of the substrate 20 in the vapor phase growth step S140 described later. As a result, the exposed portion of the substrate 20 can be mildly etched, and the region of the upper surface of the substrate 20 excluding the crystal defect portion can be kept smooth.

The following are exemplified as more detailed etching conditions in the etching step S130.
Etching temperature Te: 500-900 ° C, preferably 600-800 ° C
Pressure in processing chamber 401: 90-105 kPa, preferably 90-95 kPa
HCl gas partial pressure / N ₂ gas partial pressure: 1-10%, preferably 1-5%
H ₂ gas partial pressure / N ₂ gas partial pressure: 1-10%, preferably 3-7%
Gas flow velocity: 5 to 15 cm / s
(Note that the gas flow velocity is a value calculated from the amount of gas supplied without considering the volume expansion due to heating.)
Etching time: 1-10h, preferably 2-5h
Etching rate: 0.1 to 10 μm / h, preferably 0.5 to 3 μm / h

By the above etching, as shown in FIG. 7C, the residual impurities 31 in the cavity 20a of the substrate 20 can be removed.

After removing residual impurities 31 in the sinus 20a of the substrate 20, the supply of HCl gas and _{H 2} gas as an etching gas into the processing chamber 401 is stopped, thereby terminating the etching step S130.

In the etching step S130, the residual impurities 31 in the cavity 20a of the substrate 20 wither to the extent that outgas is not released from the cavity 20a in the vapor phase growth step S140 described later, and the residual impurities 31 precipitated on the upper surface of the substrate 20 are present. It suffices if it is removed together with the GaN constituting the matrix of the substrate 20. That is, the residual impurities 31 in the cavity 20a of the substrate 20 may not be completely removed.

(S140: Vapor deposition process)
Next, a vapor phase growth step S140 is performed on the upper surface of the substrate 20 to epitaxially grow a semiconductor layer (vapor phase growth layer) 40 made of a group III nitride semiconductor by a vapor phase growth method. For example, the semiconductor layer 40 is epitaxially grown by the HVPE method using the above-mentioned vapor phase growth apparatus 400.

In the present embodiment, for example, after the completion of the etching step S130 described above, the same vapor is used as it is without opening the processing chamber 401 of the vapor deposition apparatus 400 to the atmosphere and without carrying out the substrate 20 from the processing chamber 401. The following vapor phase growth step S140 is continuously performed in the processing chamber 401 of the phase growth apparatus 400. In that sense, the above-mentioned etching step S130 can be considered as an in-situ etching step (in-situ etching step).

Specifically, the vapor phase growth step S140 can be carried out by, for example, the following processing procedure.

_{In the etching step S130, after stopping the supply of the HCl gas and the H 2} gas as the etching gas into the processing chamber 401, the supply of the N ₂ gas into the processing chamber 401, the exhaust gas in the processing chamber 401, and the susceptor in a state of being continued holding and rotation of the substrate 20 by 408, and supplies the NH ₃ gas to the upper surface of the substrate 20 of the processing chamber 401 through the gas supply pipe 432b. That is, the atmosphere in the processing chamber 401 is switched to an atmosphere that does not contain etching gas, that is, an atmosphere that contains NH ₃ gas and N _{2 gas.} As a result, it is possible to suppress the decomposition of the GaN constituting the substrate 20 and suppress the roughness of the surface of the substrate 10 at the time of raising the temperature. After _{supplying NH 3} gas into the processing chamber 401, the inside of the processing chamber 401 is further heated.

As shown in FIG. 6, the temperature of the substrate 20 rises above the temperature Te of the substrate 20 in the etching step S130 due to the heating in the processing chamber 401. Temperature of the substrate 20 has reached a predetermined temperature Tg, When the pressure in the processing chamber 401 reaches a predetermined pressure, while the NH ₃ gas _is supplied to the upper surface of the substrate 20, gas generated from the gas supply pipe 432a HCl gas is supplied into the vessel 433a, and GaCl gas is supplied to the upper surface of the substrate 20. At this time, H ₂ gas may be supplied into the processing chamber 401.

As a result, as shown in FIG. 8A, the semiconductor layer 40 made of GaN is epitaxially grown on the upper surface of the substrate 20.

At this time, as described above, the residual impurities 31 in the cavity 20a of the substrate 20 are withered to the extent that the outgas is not released in the etching step S130, so that the semiconductor layer 40 is grown in the vapor phase growth step S140. , It is possible to suppress the precipitation of residual impurities 31 on the upper surface of the substrate 20. As a result, it is possible to suppress the formation of dislocations in the semiconductor layer 40, the abnormal growth of the semiconductor layer 40, the formation of non-growth regions of the semiconductor layer 40, or the occurrence of warpage of the crystal plane of the semiconductor layer 40.

Further, at this time, as described above, by mildly etching the exposed portion of the substrate 20 in the etching step S130, the semiconductor layer 40 can be smoothly epitaxially grown on the upper surface of the substrate 20. At this time, it is possible to suppress the generation of facets other than the crystal plane ((0001) plane) constituting the upper surface of the semiconductor layer 40. Further, at this time, the semiconductor layer 40 grows laterally on the cavity 20a of the substrate 20, so that the cavity 20a of the substrate 20 can be closed by the semiconductor layer 40. As a result, the smooth semiconductor layer 40 can be formed.

Further, at this time, the semiconductor layer 40 can be epitaxially grown on the upper surface of the substrate 20 by the vapor phase growth method while inheriting the crystallinity of the substrate 20 having a low dislocation density by the liquid phase growth method. Thereby, the dislocation density on the upper surface of the semiconductor layer 40 can be made equal to the dislocation density on the upper surface of the substrate 20. Specifically, the dislocation density on the upper surface of the semiconductor layer 40 can be, for example, 1 × 10 ⁶ pieces / cm ² or less, preferably 5 × 10 ⁵ pieces / cm ² or less. The lower limit of the dislocation density on the upper surface of the semiconductor layer 40 is about the same as the lower limit of the dislocation density on the upper surface of the substrate 20.

Further, at this time, the growth rate of the semiconductor layer 40 by the vapor phase growth method can be made higher than the growth rate of the liquid phase growth layer 14 by the liquid phase growth method in the liquid phase growth step S112 described above. Specifically, the growth rate of the semiconductor layer 40 by the vapor phase growth method can be set to, for example, 100 μm / h or more and 1000 μm / h or less.

Further, at this time, a GaN free-standing substrate is used as the substrate 20, and a semiconductor layer 40 made of GaN having a lattice constant equal to the lattice constant of the substrate 20 is homoepitaxially grown on the substrate 20 to achieve a semiconductor in a low stress state. The layer 40 can be formed. Further, by making the coefficient of linear expansion of the substrate 20 equal to the coefficient of linear expansion of the semiconductor layer 40, cracks in the substrate 20 and the semiconductor layer 40 even when the temperature of the substrate 20 is lowered after the semiconductor layer 40 has grown. Can be suppressed. As a result, the semiconductor layer 40 can be formed into a thick film. Specifically, the thickness of the semiconductor layer 40 can be, for example, 45 μm or more and 5 mm or less, preferably 150 μm or more and 2 mm or less.

The following are examples of growth conditions when the vapor phase growth step S140 is carried out.
Growth temperature Tg: 980-1100 ° C, preferably 1050-1100 ° C
Pressure in processing chamber 401: 90-105 kPa, preferably 90-95 kPa
Partial pressure of GaCl gas: 1.5 to 15 kPa
Partial pressures of / GaCl gas of the NH ₃ gas: 2-6
Flow rate of N ₂ gas / Flow rate of H ₂ gas: 1 to 20
Gas flow velocity: 5 to 15 cm / s
(Note that the gas flow velocity is a value calculated from the amount of gas supplied without considering the volume expansion due to heating.)
In the present embodiment, the flow velocity of the gas flowing on the upper surface of the substrate 20 in the vapor phase growth step S140 is made equal to, for example, the flow velocity of the gas flowing on the upper surface of the substrate 20 in the etching step S130.

By growing the semiconductor layer 40 under the above growth conditions, the semiconductor laminate 1 having the substrate 20 and the semiconductor layer 40 can be produced.

When the growth of the semiconductor layer 40 is completed, _{while supplying NH 3} gas and N ₂ gas into the processing chamber 401, the inside of the processing chamber 401 is exhausted, and the HCl gas is supplied into the gas generator 433a, and the processing chamber is used. _{The supply of H 2} gas into the 401 and the heating by the heater 407 are stopped. When the temperature inside the processing chamber 401 drops below 500 ° C, _{the supply of NH 3} gas is stopped, and then the atmosphere inside the processing chamber 401 is _{replaced with N 2} gas to restore the atmospheric pressure, and the inside of the processing chamber 401 is changed to atmospheric pressure. After the temperature is lowered to a temperature at which it can be carried out, the semiconductor laminate 1 is carried out from the inside of the processing chamber 401.

(S150: Slicing process)
Next, as shown in FIG. 8B, the semiconductor layer 40 of the semiconductor laminate 1 is sliced to prepare a plurality of nitride crystal substrates 2 as GaN free-standing substrates.

After that, at least the upper surface of the nitride crystal substrate 2 is polished, and the upper surface of the nitride crystal substrate 2 is set as an epiready surface. After the polishing of the nitride crystal substrate 2 is completed, the nitride crystal substrate 2 is subjected to a predetermined cleaning.

As described above, the nitride crystal substrate 2 of the present embodiment is manufactured.

The upper surface of the nitride crystal substrate 2 manufactured in this manner is a (0001) plane or a plane having a predetermined off-angle with respect to the (0001) plane, similarly to the substrate 20. The dislocation density on the upper surface of the nitride crystal substrate 2 is, for example, 1 × 10 ⁶ / cm ² or less, preferably 5 × 10 ⁵ / cm ^{2, similar to the dislocation density on the upper surface of the semiconductor layer 40 described above.} It becomes as follows. The lower limit of the dislocation density on the upper surface of the nitride crystal substrate 2 is about the same as the lower limit of the dislocation density on the upper surface of the semiconductor layer 40 described above.

The above-mentioned vapor phase growth step S140 may be re-executed using the semiconductor laminate 1 left after slicing the nitride crystal substrate 2 or the sliced nitride crystal substrate 2. As a result, the nitride crystal substrate 2 having good crystal quality can be repeatedly manufactured.

(2) Effects obtained by the present embodiment According to the present embodiment, one or more of the following effects can be obtained.

(A) In the etching step S130, at least a part of the residual impurities 31 remaining in the cavity 20a of the substrate 20 in the substrate preparation step S110 is vaporized, and at least a part of the vaporized residual impurities 31 is deposited on the upper surface of the substrate 20. .. Then, at least a part of the residual impurities 31 precipitated on the upper surface of the substrate 20 is removed together with the GaN constituting the matrix of the substrate 20. As a result, the residual impurities 31 in the cavity 20a of the substrate 20 can be reduced, and the residue can be withered to the extent that outgas is not released from the cavity 20a in the vapor phase growth step S140. By withering the residual impurities 31 in the cavity 20a of the substrate 20 in the etching step S130, the precipitation of the residual impurities 31 on the upper surface of the substrate 20 is suppressed when the semiconductor layer 40 is grown in the vapor phase growth step S140. Can be done. By suppressing the precipitation of the residual impurities 31 on the upper surface of the substrate 20, it is possible to suppress the occurrence of the deviation of the crystal orientation due to the residual impurities 31 precipitated on the upper surface of the substrate 20, and it is possible to suppress the occurrence of the deviation of the crystal orientation in the semiconductor layer 40. The formation of dislocations can be suppressed. Further, by suppressing the precipitation of the residual impurities 31 on the upper surface of the substrate 20, abnormal growth of the semiconductor layer 40 or non-growth in which the semiconductor layer 40 does not grow due to the residual impurities 31 precipitated on the upper surface of the substrate 20 The formation of regions can be suppressed. Further, by suppressing the precipitation of the residual impurities 31 on the upper surface of the substrate 20, the semiconductor layer 40 can be grown in a step flow, and the occurrence of three-dimensional island-like growth can be suppressed. As a result, it is possible to suppress the occurrence of tensile stress during the growth of the semiconductor layer 40 and the occurrence of warpage of the crystal plane of the semiconductor layer 40. As a result, it becomes possible to manufacture the semiconductor laminate 1 or the nitride crystal substrate 2 having good crystal quality. That is, it is possible to further improve the crystal quality of the semiconductor laminate 1 or the nitride crystal substrate 2 as compared with the conventional method.

(B) In the etching step S130, the residual impurities 31 are removed by etching the matrix of the substrate 10 to which the residual impurities 31 are attached, instead of directly etching the residual impurities 31. As a result, even if the material constituting the residual impurities 31, the amount of the residual impurities 31, the position of the residual impurities 31, and the like are unknown, the residual impurities 31 can be reliably removed together with the matrix of the substrate 10. .. Further, even if the residual impurities 31 are carbonized or nitrided by heating and become insoluble in any solvent, the residual impurities 31 can be reliably removed together with the matrix of the substrate 10.

(C) In the etching step S130 of the present embodiment, at least a part of the residual impurities 31 is vaporized from the inside of the cavity 20a of the substrate 20, and at least a part of the vaporized residual impurities 31 is deposited on the upper surface of the substrate 20. That is, the residual impurities 31 remaining in the cavity 20a of the substrate 20 are moved to a position on the substrate 20 where they can easily come into contact with the etching gas. After the residual impurities 31 are deposited on the upper surface of the substrate 20, at least a part of the residual impurities 31 precipitated on the upper surface of the substrate 20 is removed together with the GaN. By going through such a two-step process, even if the etching gas does not enter the cavity 20a of the substrate 20, and even if the etching conditions are mild, the etching conditions enter the cavity 20a of the substrate 20. The residual impurities 31 can be reliably removed.

(D) When the cavity 20a is formed in the substrate 20, the wax, cutting fluid, polishing liquid, abrasive, and cleaning liquid used in the slicing step S114, the polishing step S116, or the cleaning step S118 in the substrate preparing step S110. Residual impurities 31 derived from at least one of them are likely to remain in the cavity 20a of the substrate 20. Therefore, by performing the etching step S130 described above, the residual impurities 31 described above can be reliably removed. As a result, the influence of the residual impurities 31 generated in the process of the substrate preparation step S110 can be prevented from reaching the vapor phase growth step S140 as a subsequent step.

(E) By performing the substrate preparation step S110 using the liquid phase growth method and performing the vapor phase growth step S140 through the etching step S130, while inheriting the crystallinity of the substrate 20 having a low dislocation density by the liquid phase growth method, The semiconductor layer 40 can be epitaxially grown on the upper surface of the substrate 20. Thereby, the dislocation density on the upper surface of the semiconductor layer 40 can be made equal to the dislocation density on the upper surface of the substrate 20. On the other hand, at this time, by epitaxially growing the semiconductor layer 40 by the vapor phase growth method in the vapor phase growth step S140, the growth rate of the semiconductor layer 40 by the vapor phase growth method is set to the growth rate of the liquid phase growth layer 14 by the liquid phase growth method. It can be higher than the growth rate. Thereby, the thick semiconductor layer 40 can be easily formed. As a result, it is possible to improve the productivity of the semiconductor laminate 1 or the nitride crystal substrate 2 while improving the crystal quality. That is, it is possible to further improve the effect of the method using the liquid phase growth method and the vapor phase growth method in this order as compared with the conventional method.

(F) In the etching step S130, the exposed portion of the substrate 20 is etched under the condition that the region of the upper surface of the substrate 20 excluding the crystal defect portion is smooth. By keeping the upper surface of the substrate 20 smooth under such mild etching conditions, the semiconductor layer 40 can be smoothly epitaxially grown on the upper surface of the substrate 20 in the vapor phase growth step S140. Further, at this time, it is possible to suppress the generation of facets other than the crystal planes constituting the upper surface of the semiconductor layer 40. If facets other than the crystal planes constituting the upper surface of the semiconductor layer 40 are generated during the growth of the semiconductor layer 40, the uptake of impurities into the semiconductor layer 40 will increase. On the other hand, in the present embodiment, by suppressing the generation of such facets, it is possible to suppress the uptake of impurities into the semiconductor layer 40.

(G) The etching step S130 and the vapor phase growth step S140 are continuously performed in the same processing chamber 401 without opening the processing chamber 401 of the vapor phase growth apparatus 400 to the atmosphere. As a result, contamination at the interface between the substrate 20 and the semiconductor layer 40 can be suppressed between the etching step S130 and the vapor phase growth step S140. That is, the semiconductor layer 40 can be directly grown on the upper surface of the substrate 20 purified by the etching step S130. By suppressing contamination of the interface between the substrate 20 and the semiconductor layer 40 in this way, it is possible to take over to the semiconductor layer 40 without deteriorating the crystallinity of the substrate 20.

(H) In the substrate preparation step S110, for example, the substrate 20 is manufactured using the MPS substrate 10. In the substrate 20 produced by using such an MPS substrate 10, many dongs 20a tend to be formed at the association portion of the island-shaped crystals in the liquid phase growth step S112. Therefore, residual impurities 31 tend to remain in the cavity 20a of the substrate 20. Therefore, by applying the etching step S130 of the above-described embodiment to the substrate 20, even when the substrate 20 having many cavities 20a is used, residual impurities in the cavities 20a can be removed. can. As a result, it is possible to suppress the formation of crystal defect portions in the semiconductor layer 40 in the vapor phase growth step S140. Therefore, this embodiment is particularly effective when the semiconductor laminate 1 or the nitride crystal substrate 2 is manufactured by using the substrate 20 having many cavities 20a such as the substrate 20 manufactured by the MPS substrate 10.

(3) Modification Example of This Embodiment The etching step S130 of the above-described embodiment can be modified as in the modification shown below, if necessary. In addition, this modification corresponds to the case where the etching step S130 also serves as the vaporization step S120 described later. Hereinafter, only the elements different from the above-described embodiment will be described, and the elements substantially the same as the elements described in the above-described embodiment are designated by the same reference numerals and the description thereof will be omitted.

(Modification example 1)
FIG. 9 is a diagram showing a change in the flow velocity of the gas flowing on the upper surface of the seed crystal substrate from the etching step to the vapor phase growth step of the modification 1 of the present embodiment.
As in the first modification shown in FIG. 9, the flow velocity Ve of the gas flowing on the upper surface of the substrate 20 in the etching step S130 is higher than the flow velocity Vg of the gas flowing on the upper surface of the substrate 20 in the vapor phase growth step S140, for example. You may. As a result, the residual impurities 31 in the cavity 20a of the substrate 20 can be sucked out of the cavity 20a due to the Venturi effect.

Specifically, the ratio (flow velocity ratio) of the gas flow velocity Ve in the etching step S130 to the gas flow velocity Vg in the vapor phase growth step S140 is, for example, 1.1 times or more and 5 times or less, preferably 1. .5 times or more and 3 times or less. If the flow velocity ratio is less than 1.1 times, the Venturi effect may not be sufficiently obtained. On the other hand, by setting the flow velocity ratio to 1.1 times or more, the Venturi effect can be sufficiently obtained. Further, by setting the flow velocity ratio to 1.5 times or more, the Venturi effect can be surely obtained. On the other hand, if the flow velocity ratio is more than 5 times, the etching gas is strongly sprayed on the upper surface of the substrate 20, so that the upper surface of the substrate 20 may be roughened. On the other hand, by setting the flow velocity ratio to 5 times or less, it is possible to suppress the strong spraying of the etching gas on the upper surface of the substrate 20, and it is possible to suppress the roughness of the upper surface of the substrate 20. Further, by setting the flow velocity ratio to 3 times or less, the roughness of the upper surface of the substrate 20 can be reliably suppressed.

For example, when the gas flow velocity Vg in the vapor phase growth step S140 is 5 cm / s or more and 10 cm / s or less, the gas flow velocity Ve in the etching step S130 is 5.5 cm / s or more and 50 cm / s or less, preferably. It shall be 7.5 cm / s or more and 30 cm / s or less.

According to the first modification, the Venturi effect is obtained by making the flow velocity Ve of the gas flowing on the upper surface of the substrate 20 in the etching step S130 higher than the flow velocity Vg of the gas flowing on the upper surface of the substrate 20 in the vapor phase growth step S140. The pressure inside the cavity 20a of the substrate 20 can be made lower than the pressure outside the cavity 20a. As a result, the residual impurities 31 in the cavity 20a of the substrate 20 can be sucked out of the cavity 20a. As a result, the efficiency of removing residual impurities 31 in the etching step S130 can be improved.

(Modification 2)
FIG. 9B is a diagram showing pressure changes in the processing chamber during the etching step and the vapor phase growth step of the modification 2 of the present embodiment.
As in the modification 2 shown in FIG. 9B, the pressure in the processing chamber 401 in the etching step S130 may be changed up and down. That is, the cycle including reducing the pressure in the processing chamber 401 in the etching step S130 and increasing the pressure may be repeated. As a result, the atmosphere in the cave 20a of the substrate 20 can be replaced.

At this time, the minimum pressure Pe1 in the processing chamber 401 in the etching step S130 is set to be lower than, for example, the pressure Pg in the processing chamber 401 in the vapor phase growth step S140. As a result, the atmosphere in the cave 20a of the substrate 20 can be efficiently replaced.

The maximum pressure Pe2 in the processing chamber 401 in the etching step S130 is not particularly limited, but can be made equal to, for example, the pressure Pg in the processing chamber 401 in the vapor phase growth step S140. The maximum pressure Pe2 in the processing chamber 401 in the etching step S130 may be higher than the pressure Pg in the processing chamber 401 in the vapor phase growth step S140.

At this time, the ratio of the minimum pressure Pe1 to the maximum pressure Pe2 in the processing chamber 401 in the etching step S130 (pressure ratio: Pe1 / Pe2) is set to, for example, 1/10 or more and 1/2 or less. If the pressure ratio is less than 1/10, the minimum pressure Pe1 is set excessively low, which may reduce the etching rate. In addition, it may take a long time to fluctuate the pressure in the processing chamber 401 with the pressure ratio. On the other hand, by setting the pressure ratio to 1/10 or more, it is possible to suppress a decrease in the etching rate. Further, the time for changing the pressure in the processing chamber 401 with the pressure ratio can be shortened. On the other hand, if the pressure ratio is more than 1/2, it may not be possible to sufficiently replace the atmosphere in the cavity 20a of the substrate 20. On the other hand, by setting the pressure ratio to 1/2 or less, the atmosphere in the cavity 20a of the substrate 20 can be sufficiently replaced.

At this time, the number of repetitions of the cycle of varying the pressure in the processing chamber 401 in the etching step S130 is set to, for example, 6 times or more and 20 times or less. If the number of repetitions is less than 6, it may not be possible to sufficiently replace the atmosphere in the cavity 20a of the substrate 20. On the other hand, by setting the number of repetitions to 6 or more, the atmosphere in the cavity 20a of the substrate 20 can be sufficiently replaced. On the other hand, if the number of repetitions exceeds 20, the time required to fluctuate the pressure in the processing chamber 401 may become longer depending on the number of repetitions. On the other hand, by setting the number of repetitions to 20 or less, the time for changing the pressure in the processing chamber 401 can be shortened by the number of repetitions. That is, the atmosphere in the cave 20a of the substrate 20 can be efficiently replaced.

According to the second modification, by changing the pressure in the processing chamber 401 in the etching step S130 up and down, the outgas of the residual impurities 31 is discharged from the inside to the outside of the cavity 20a of the substrate 20, while the outgas of the substrate 20 The clean atmosphere outside the cave 20a can be taken into the cave 20a. As a result, the atmosphere in the cave 20a of the substrate 20 can be replaced. That is, it may be considered that so-called cycle purging can be performed in the cavity 20a of the substrate 20. As a result, the outgas of the residual impurities 31 in the cavity 20a of the substrate 20 can be quickly reduced.

<Second Embodiment of the present invention>
In the above-described embodiment, the case where the etching step S130 is performed immediately after the substrate preparation step S110 has been described, but as in the second embodiment below, the residual impurities 31 are vaporized (evaporated) during these steps. The vaporization step S120 may be performed. Also in this embodiment, only the elements different from the above-described embodiment will be described.

(1) Method for Manufacturing Semiconductor Laminate or Method for Manufacturing Nitride Crystal Substrate With reference to FIGS. 10 and 11, a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride crystal substrate according to the present embodiment will be described. FIG. 10 is a flowchart showing a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride crystal substrate according to the present embodiment. FIG. 11A is a diagram showing a temperature change of the seed crystal substrate from the vaporization step to the gas phase growth step of the present embodiment, and FIG. 11B is a diagram showing the temperature change of the seed crystal substrate from the vaporization step to the gas phase growth step of the present embodiment. It is a figure which shows the flow velocity change of the gas flowing on the upper surface of a seed crystal substrate.

(S120: Vaporization process)
In the present embodiment, after the substrate preparation step S110 and before the etching step S130, the substrate 20 is heated to a predetermined temperature or higher, and at least a part of the residual impurities 31 in the cavity 20a of the substrate 20 is vaporized in the vaporization step S120. I do. The process of "vaporizing at least a part of the residual impurities 31" here may be considered as a process of causing at least a part of the residual impurities 31 to spring out from the inside of the cavity 20a of the substrate 20.

The vaporization step S120 can be carried out by using the above-mentioned vapor phase growth apparatus 400, for example, by the following processing procedure.

First, the substrate 20 is put into (carried in) into the airtight container 403 and held on the susceptor 408. At this time, the Ga melt as a raw material used in the vapor phase growth step S140 is housed in the gas generator 433a. Next, a predetermined gas (hereinafter, exhaust gas) is supplied into the processing chamber 401 from at least one of the gas supply pipes 432a to 432c, and heating and exhausting in the processing chamber 401 are performed. At this time, the rotation of the susceptor 408 also starts.

At this time, the exhaust gas supplied into the processing chamber 401 is mainly N ₂ gas, for example. As a result, etching of the GaN constituting the substrate 20 can be suppressed. The exhaust gas may contain _{H 2 gas.} As a result, when Ga droplets are generated due to N omission from the GaN constituting the substrate 20, the Ga droplets can be vaporized as _{GaH 3 and removed.} However, from the viewpoint of suppressing etching of the GaN constituting the substrate 20, it is preferable that the exhaust gas does not contain HCl gas as the etching gas. That is, it is preferable to perform the vaporization step S120 in an atmosphere containing no etching gas.

As shown in FIG. 11A, the temperature of the substrate 20 gradually rises due to the heating inside the processing chamber 401. In the present embodiment, the temperature of the substrate 20 reaches a predetermined temperature Td, the pressure in the processing chamber 401 reaches a predetermined pressure, and then the temperature of the substrate 20 and the pressure in the processing chamber 401 are adjusted for a predetermined time. Keep each constant constant.

As a result, as shown in FIG. 7A described above, by heating the substrate 20 to a predetermined temperature Td in the vaporization step S120, at least a part of the residual impurities 31 in the cavity 20a of the substrate 20 is vaporized. (Make it spring up). At least a part of the residual impurities 31 vaporized in the cave 20a reaches the opening of the cave 20a through the cave 20a. At least a part of the residual impurities 31 that have reached the opening of the cave 20a is discharged to the outside of the substrate 20 by the exhaust gas. On the other hand, the other portion of the residual impurities 31 is ejected from the opening of the cave 20a on the upper surface of the substrate 20 and is deposited in the vicinity of the opening. The other portion of the residual impurity 31 may be redeposited and deposited on a portion of the upper surface of the substrate 20 other than the vicinity of the opening of the cavity 20a.

At this time, as shown in FIG. 11A, the temperature Td of the substrate 20 in the vaporization step S120 is made equal to, for example, the temperature Te of the substrate 20 in the etching step S130, and the substrate 20 in the vapor phase growth step S140. The temperature is lower than Tg. As a result, in the vaporization step S120, the thermal decomposition of the GaN constituting the substrate 20 can be suppressed.

At this time, as shown in FIG. 11A, after the substrate 20 is heated to a predetermined temperature Td, the temperature of the substrate 20 is maintained for a certain period of time. As a result, in the vaporization step S120, a predetermined amount of residual impurities 31 in the cavity 20a of the substrate 20 can be stably vaporized.

At this time, as shown in FIG. 11B, the flow velocity Vd of the gas flowing on the upper surface of the substrate 20 in the vaporization step S120 is, for example, the flow velocity Ve of the gas flowing on the upper surface of the substrate 20 in the etching step S130. Also raise. As a result, the residual impurities 31 in the cavity 20a of the substrate 20 can be sucked out of the cavity 20a due to the Venturi effect.

Specifically, the ratio (flow velocity ratio) of the gas flow velocity Vd in the vaporization step S120 to the gas flow velocity Ve in the etching step S130 is set to, for example, 1.1 times or more, preferably 1.5 times or more. .. By setting the flow velocity ratio to 1.1 times or more, the Venturi effect can be sufficiently obtained. Further, by setting the flow velocity ratio to 1.5 times or more, the Venturi effect can be surely obtained. The upper limit of the flow velocity ratio in the vaporization step S120 is not limited because the higher the value, the better. However, considering the typical exhaust capacity of the vapor phase growth apparatus 400, it is, for example, about 5 times. be.

For example, when the gas flow velocity Ve in the etching step S130 is 5 cm / s or more and 10 cm / s or less, the gas flow velocity Vd in the vaporization step S120 is 5.5 cm / s or more and 50 cm / s or less, preferably 7. It shall be 5 cm / s or more and 30 cm / s or less.

Further, at this time, the time of the vaporization step S120 is made longer than the time of, for example, the etching step S130. Thereby, before the etching step S130, the residual impurities 31 can be discharged to the outside of the substrate 20 by the exhaust gas, or the residual impurities 31 can be deposited on the upper surface of the substrate 20. As a result, the residual impurities 31 that have penetrated into the cavity 20a of the substrate 20 can be reduced. When the residual impurities 31 can be discharged in a short time by adjusting the gas flow velocity Vd in the vaporization step S120, the time of the vaporization step S120 may be set to be equal to or less than the time of the etching step S130.

After a lapse of a predetermined time, when a predetermined amount of residual impurities 31 in the cavity 20a of the substrate 20 is discharged from the substrate 20 by exhaust gas, the temperature of the substrate 20 and the pressure in the processing chamber 401 are kept constant, and the processing chamber 401 is used. _{The flow rate of N 2} gas or the like as the exhaust gas supplied to the inside is reduced, and the gas flow velocity is adjusted to be the gas flow velocity Ve in the etching step S130. As a result, the vaporization step S120 is completed. The supply of such N ₂ gas into the processing chamber 401 is continued.

(Processes after etching process 130)
Next, the etching step S130 and the vapor phase growth step S140 are performed.

In the etching step S130, as shown in FIG. 7B described above, at least a part of the residual impurities 31 precipitated on the upper surface of the substrate 20 in the vaporization step S120 is removed together with the GaN constituting the matrix of the substrate 20.

In the present embodiment, the processing chamber 401 of the vapor phase growth apparatus 400 is not opened to the atmosphere, and the substrate 20 is not carried out from the processing chamber 401. The vaporization step S120, the etching step S130, and the vapor phase growth step S140 are continuously performed. As a result, contamination at the interface between the substrate 20 and the semiconductor layer 40 can be suppressed between the vaporization step S120 and the vapor phase growth step S140.

The steps after the vapor phase growth step S140 are the same as those in the first embodiment.

(2) Effects obtained by the present embodiment According to the present embodiment, one or more of the following effects can be obtained.

(A) In the vaporization step S120, after the substrate preparation step S110 and before the etching step S130, the substrate 20 is heated to a predetermined temperature or higher to vaporize at least a part of the residual impurities 31 in the cavity 20a of the substrate 20. At least a part of the vaporized residual impurities 31 is deposited on the upper surface of the substrate 20. That is, before the etching step S130, the residual impurities 31 remaining in the cavity 20a of the substrate 20 are moved to a position on the substrate 20 where they can easily come into contact with the etching gas. As a result, the residual impurities 31 that have penetrated into the depth of the cavity 20a of the substrate 20 can be reduced. As a result, in the etching step S130, residual impurities remaining in the cavity 20a of the substrate 20 even if the etching gas does not enter the cavity 20a of the substrate 20 and even if the etching conditions are mild. 31 can be reliably removed.

(B) In the present embodiment, the vaporization step S120 for vaporizing the residual impurities 31 and the etching step S130 for removing the residual impurities 31 together with GaN are performed separately. Thereby, conditions such as gas and temperature suitable for the operation of each step can be selected. For example, the exhaust gas used in the vaporization step S120 may be prevented from containing HCl gas, or the time of the vaporization step S120 may be lengthened. As a result, the residual impurities 31 in the cavity 20a of the substrate 20 can be reliably vaporized. As a result, the residual impurities 31 that have entered the inner part of the cave 20a of the substrate 20 can be reliably discharged from the inner part of the cave 20a to at least outside the opening of the cave 20a.

(C) The flow velocity Vd of the gas flowing on the upper surface of the substrate 20 in the vaporization step S120 is made higher than the flow velocity Ve of the gas flowing on the upper surface of the substrate 20 in the etching step S130. As a result, the Venturi effect can be generated, and the pressure inside the cavity 20a of the substrate 20 can be made lower than the pressure outside the cavity 20a. As a result, the residual impurities 31 in the cavity 20a of the substrate 20 can be sucked out of the cavity 20a. As a result, at least a part of the vaporized residual impurities 31 can be easily discharged to the outside of the cavity 20a of the substrate 20.

(3) Modified Example of the Present Embodiment The vaporization step S120 of the above-described embodiment can be changed as in the modified example shown below, if necessary. Also in the following modification, only the elements different from the above-described embodiment will be described.

(Modification example 1)
FIG. 12 is a diagram showing the temperature change of the seed crystal substrate from the vaporization step to the vapor phase growth step of the modification 1 of the present embodiment.
As in the first modification shown in FIG. 12, the temperature Td of the substrate 20 in the vaporization step S120 may be higher than the temperature Te of the substrate 20 in the etching step S130, for example. In this modification, for example, the temperature Td of the substrate 20 in the vaporization step S120 is maintained constant. By increasing the temperature Td of the substrate 20 in the vaporization step S120 in this way, it is possible to easily vaporize the residual impurities 31 in the cavity 20a of the substrate 20 before the etching step S130.

The temperature Td of the substrate 20 in the vaporization step S120 is preferably lower than the temperature Tg of the substrate 20 in the vaporization step S140. As a result, in the vaporization step S120, the thermal decomposition of the GaN constituting the substrate 20 can be suppressed.

Specifically, the temperature Td of the substrate 20 in the vaporization step S120 is set to, for example, 700 ° C. or higher and 900 ° C. or lower. By setting the temperature Td to 700 ° C. or higher, the weight reduction of the residual impurities 31 in the cavity 20a of the substrate 20 can be promoted by heating. On the other hand, by setting the temperature Td to 900 ° C. or lower, thermal decomposition of the GaN constituting the substrate 20 can be suppressed.

According to the first modification, by making the temperature Td of the substrate 20 in the vaporization step S120 higher than the temperature Te of the substrate 20 in the etching step S130, residual impurities in the cavity 20a of the substrate 20 before the etching step S130. 31 can be easily vaporized. As a result, in the etching step S130, the residual impurities 31 in the cavity 20a of the substrate 20 can be reliably removed even if the etching conditions are mild.

(Modification 2)
FIG. 13A is a diagram showing a pressure change in the processing chamber from the vaporization step to the vapor phase growth step of the modification 2 of the present embodiment.
As in the second modification shown in FIG. 13A, the pressure Pd in the processing chamber 401 in the vaporization step S120 may be lower than the pressure Pe in the processing chamber 401 in the etching step S130, for example. In this modification, for example, the pressure Pd in the processing chamber 401 in the vaporization step S120 is maintained constant. By lowering the pressure Pd in the processing chamber 401 in the vaporization step S120 in this way, it is possible to promote the vaporization of at least a part of the residual impurities 31 in the cavity 20a of the substrate 20 before the etching step S130.

Specifically, the pressure Pd in the processing chamber 401 in the vaporization step S120 is set to, for example, 1 kPa or less. As a result, it is possible to promote the vaporization of at least a part of the residual impurities 31 in the cavity 20a of the substrate 20. The lower limit of the pressure Pd in the processing chamber 401 in the vaporization step S120 is not limited as it is lower, but if the typical exhaust capacity of the vapor phase growth apparatus 400 is taken into consideration, for example. , About 90 Pa.

According to the second modification, the pressure Pd in the processing chamber 401 in the vaporization step S120 is made lower than the pressure Pe in the processing chamber 401 in the etching step S130, so that the cavity 20a of the substrate 20 is before the etching step S130. It is possible to promote the vaporization of at least a part of the residual impurities 31 in the inside. As a result, in the etching step S130, the residual impurities 31 in the cavity 20a of the substrate 20 can be reliably removed even if the etching conditions are mild.

(Modification example 3)
FIG. 13B is a diagram showing a pressure change in the processing chamber from the vaporization step to the vapor phase growth step of the modification 3 of the present embodiment.
As in the modification 3 shown in FIG. 13B, the pressure in the processing chamber 401 in the vaporization step S120 may be changed up and down. That is, the cycle including reducing the pressure in the processing chamber 401 in the vaporization step S120 and increasing the pressure may be repeated. As a result, the atmosphere in the cavity 20a of the substrate 20 can be replaced in the same manner as in the etching step S130 of the second modification of the first embodiment.

At this time, the minimum pressure Pd1 in the processing chamber 401 in the vaporization step S120 is made lower than, for example, the pressures Pe and Pg in the processing chamber 401 in the etching step S130 and the vapor phase growth step S140. As a result, the atmosphere in the cave 20a of the substrate 20 can be efficiently replaced. In this case, the pressure Pe in the processing chamber 401 in the etching step S130 is equal to the pressure Pg in the processing chamber 401 in the vapor phase growth step S140.

The maximum pressure Pd2 in the processing chamber 401 in the vaporization step S120 is not particularly limited, but is equal to, for example, the pressures Pe and Pg in the processing chamber 401 in the etching step S130 and the vapor phase growth step S140. can do. The maximum pressure Pd2 in the processing chamber 401 in the vaporization step S120 may be higher than the pressures Pe and Pg in the processing chamber 401 in the etching step S130 and the vapor phase growth step S140.

At this time, the ratio of the minimum pressure Pd1 to the maximum pressure Pd2 in the processing chamber 401 in the vaporization step S120 (pressure ratio: Pd1 / Pd2) is set to, for example, 1/10 or more and 1/2 or less. If the pressure ratio is less than 1/10, the time required to fluctuate the pressure in the processing chamber 401 at the pressure ratio may become long. On the other hand, by setting the pressure ratio to 1/10 or more, the time for changing the pressure in the processing chamber 401 at the pressure ratio can be shortened. On the other hand, if the pressure ratio is more than 1/2, it may not be possible to sufficiently replace the atmosphere in the cavity 20a of the substrate 20. On the other hand, by setting the pressure ratio to 1/2 or less, the atmosphere in the cavity 20a of the substrate 20 can be sufficiently replaced.

At this time, the number of repetitions of the cycle of varying the pressure in the processing chamber 401 in the vaporization step S120 is set to, for example, 6 times or more and 20 times or less. If the number of repetitions is less than 6, it may not be possible to sufficiently replace the atmosphere in the cavity 20a of the substrate 20. On the other hand, by setting the number of repetitions to 6 or more, the atmosphere in the cavity 20a of the substrate 20 can be sufficiently replaced. On the other hand, if the number of repetitions exceeds 20, the time required to fluctuate the pressure in the processing chamber 401 may become longer depending on the number of repetitions. On the other hand, by setting the number of repetitions to 20 or less, the time for changing the pressure in the processing chamber 401 can be shortened by the number of repetitions. That is, the atmosphere in the cave 20a of the substrate 20 can be efficiently replaced.

According to the third modification, by changing the pressure in the processing chamber 401 in the vaporization step S120 up and down, the outgas of the residual impurities 31 is discharged from the inside of the cavity 20a of the substrate 20 to the outside, while the outgas of the substrate 20 is discharged. The clean atmosphere outside the cave 20a can be taken into the cave 20a. As a result, the atmosphere in the cave 20a of the substrate 20 can be replaced. That is, it may be considered that so-called cycle purging can be performed in the cavity 20a of the substrate 20. As a result, the outgas of the residual impurities 31 in the cavity 20a of the substrate 20 can be quickly reduced.

<Third Embodiment of the present invention>
In the above-described embodiment, the case where the semiconductor layer 40 is grown at a predetermined growth temperature Tg in the vapor phase growth step S140 has been described, but the growth temperature in the vapor phase growth step S140 is changed as in the third embodiment below. You may let me. Also in this embodiment, only the elements different from the above-described embodiment will be described.

(1) Knowledge obtained by the inventor and the like By performing the etching step S130 as in the above-described embodiment, the inclusion, wax, cutting fluid, abrasive liquid, and polishing remaining in the cavity 20a of the substrate 20 in the substrate preparation step S110. Residual impurities 31 containing at least one of the material and the cleaning liquid can be removed together with the GaN constituting the matrix of the substrate 20. However, depending on the state of inclusion in the substrate 20, the following problems may occur.

Here, inclusions may be randomly distributed in the substrate 20 formed by the liquid phase growth method or the like. When the substrate 20 is polished, the position and depth of inclusions in the substrate 20 may be randomly determined.

When the opening of the cavity 20a is formed on the upper surface of the substrate 20, the inclusion as the residual impurities 31 in the cavity 20a can be removed by performing the etching step S130 as described above. However, for example, when the opening of the cavity 20a is not formed on the upper surface of the substrate 20, or when the opening of the cavity 20a in the substrate 20 is small, the residual impurities 31 (even if the etching step S130 is performed) Inclusion may remain included.

When the temperature of the substrate 20 is raised to a predetermined growth temperature (for example, 1050 ° C. or higher and 1100 ° C. or lower) in the vapor phase growth step S140 while the inclusions are contained in the substrate 20, the inclusions in the substrate 20 grow. It will be heated to a temperature and will expand thermally. At this time, the inclusions in the substrate 20 formed by the liquid phase growth method or the like are confined at a temperature lower than the growth temperature of the vapor phase growth step S140 (for example, 850 ° C. or higher and 950 ° C. or lower). Therefore, the pressure of the inclusion in the substrate 20 increases according to the difference between the temperature when the inclusion is confined in the substrate 20 and the growth temperature in the vapor phase growth step S140. If the inclusion pressure rises excessively, the crystal portion of the substrate 20 that has blocked the upper part of the inclusion may be destroyed, and the inclusion may explode.

Further, when the inclusion explodes, plastic deformation may occur in the crystal portion of the substrate 20 that has blocked the inclusion. Therefore, there is a possibility that dislocations may be introduced into the semiconductor layer 40 grown on the portion of the substrate 20 where the plastic deformation has occurred.

Further, when the inclusion explodes, the crystal portion of the substrate 20 that has blocked the inclusion may become fragments and scatter. The debris may rest on the top surface of the substrate 20 in random orientation. Therefore, regardless of the size of the fragments, the semiconductor layer 40 may grow abnormally on the fragments randomly placed on the upper surface of the substrate 20.

The above-mentioned problem regarding the inclusion explosion is not limited to the case where the substrate 20 includes the cavity 20a. That is, even when the substrate 20 includes only inclusions (only the inclusion-filled sinuses 20a), the same problems as described above can occur.

The present embodiment described below is based on the above-mentioned new problem found by the present inventors.

(2) Method for Manufacturing Semiconductor Laminate or Method for Manufacturing Nitride Crystal Substrate With reference to FIGS. 14 and 15, a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride crystal substrate according to the present embodiment will be described. FIG. 14 is a flowchart showing a method for manufacturing a semiconductor laminate or a method for manufacturing a nitride crystal substrate according to the present embodiment. FIG. 15 is a diagram showing a temperature change of the seed crystal substrate from the etching step to the vapor phase growth step of the present embodiment.

(S110: Substrate preparation process)
First, the substrate 20 is prepared. The substrate 20 contains, for example, inclusions. Further, the surface of the substrate 20 is polished. Therefore, the position and depth of inclusions in the substrate 20 are randomly determined. For example, as described above, not only when the opening of the cavity 20a is formed on the upper surface of the substrate 20, but also when the opening of the cavity 20a is not formed on the upper surface of the substrate 20, the opening of the cavity 20a in the substrate 20 is formed. If it is small, inclusions may be formed in the substrate 20 without forming the cavities 20a. That is, the upper part of the inclusion in the substrate 20 may be blocked.

(S130: Etching process)
Next, the vapor phase growth apparatus 400 is used to perform an etching step S130 in which the exposed portion of the substrate 20 is etched in the gas phase. As a result, at least a part of the residual impurities 31 including inclusions remaining in the cavity 20a of the substrate 20 is vaporized, and at least a part of the vaporized residual impurities 31 is deposited on the upper surface of the substrate 20. Then, at least a part of the residual impurities 31 precipitated on the upper surface of the substrate 20 can be removed together with the GaN constituting the matrix of the substrate 20.

However, even if the etching step S130 is performed, if the opening of the cavity 20a is not formed on the upper surface of the substrate 20, the residual impurities 31 including inclusions may remain contained.

(S140: Vapor deposition process)
Next, a vapor phase growth step S140 is performed in which the semiconductor layer 40 is epitaxially grown on the upper surface of the substrate 20 by the vapor phase growth method. In the present embodiment, the gas phase growth step S140 is composed of, for example, a two-step growth step, and includes a first layer growth step (explosion suppression layer growth step) S142 and a second layer growth step (full-scale growth step) S144. have.

(S142: 1st layer growth step)
After the completion of the etching step S130, the temperature of the substrate 20 is raised above the temperature Te of the substrate 20 in the etching step S130. When the temperature of the substrate 20 reaches a predetermined growth temperature Tg1, a first layer (explosion suppression layer) made of, for example, GaN is grown on the upper surface of the substrate 20 as a group III nitride semiconductor.

At this time, for example, the growth temperature Tg1 in the first layer growth step S142 is set to be lower than the growth temperature Tg2 in the second layer growth step S144 described later. Thereby, the first layer can close (thicken) the upper part of the inclusion in the substrate 20 so as to suppress the explosion of the inclusion. That is, the first layer can function as an upper lid of the inclusion or an explosion suppression layer of the inclusion.

At this time, the growth temperature Tg1 in the first layer growth step S142 is set to, for example, a critical temperature or less at which the explosion of inclusions is suppressed. As a result, in the first layer growth step S142, the first layer can be grown while suppressing the explosion of inclusions.

Specifically, the growth temperature Tg1 in the first layer growth step S142 is set to, for example, 940 ° C. or higher and lower than 1050 ° C. If the growth temperature Tg1 is less than 940 ° C., the first layer may not be able to grow as a single crystal (the first layer may become polycrystal). On the other hand, by setting the growth temperature Tg1 to 940 ° C. or higher, the first layer can be grown as a single crystal. On the other hand, if the growth temperature Tg1 is 1050 ° C. or higher, inclusions may explode during the first layer growth step S142. On the other hand, by setting the growth temperature Tg1 to less than 1050 ° C., it is possible to suppress the explosion of inclusions in the first layer growth step S142.

Further, at this time, the thickness of the first layer is set to a critical thickness at which the explosion of inclusions is suppressed when, for example, the temperature of the substrate 20 is heated to the growth temperature Tg2 in the second layer growth step S144 described later. That's all. As a result, even if the temperature of the substrate 20 is heated to the growth temperature Tg2 in the second layer growth step S144 and the inclusion pressure in the substrate 20 rises, it is possible to prevent the first layer at the upper part of the inclusion from being destroyed. can do.

Specifically, the thickness of the first layer is, for example, 10 μm or more and 1000 μm or less. If the thickness of the first layer is less than 10 μm, the first layer may be destroyed and inclusions may explode in the second layer growth step S144. On the other hand, by setting the thickness of the first layer to 10 μm or more, it is possible to suppress the destruction of the first layer and suppress the explosion of inclusions in the second layer growth step S144. On the other hand, if the thickness of the first layer exceeds 1000 μm, that is, if the thickness of the first layer, which has a relatively low crystal quality, increases, the crystal quality of the second layer may also deteriorate due to the influence. There is. On the other hand, by setting the thickness of the first layer to 1000 μm or less, it is possible to suppress the deterioration of the crystal quality of the second layer due to the thickness of the first layer, which has a relatively low crystal quality. ..

(S144: Second layer growth step)
After the completion of the first layer growth step S142, the temperature of the substrate 20 is raised above the temperature Tg1 of the substrate 20 in the first layer growth step S142. When the temperature of the substrate 20 reaches a predetermined growth temperature Tg2, a second layer (full-scale growth layer) made of, for example, GaN is grown on the upper surface of the first layer as a group III nitride semiconductor.

At this time, even if the temperature of the substrate 20 is heated to the growth temperature Tg2, the crystal quality is good while suppressing the explosion of inclusions by growing the second layer with the cover covered by the first layer described above. The second layer can be grown stably.

At this time, the growth temperature Tg2 in the second layer growth step S144 is set to, for example, 1050 ° C. or higher and 1100 ° C. or lower. If the growth temperature Tg2 is less than 1050 ° C., the crystal quality of the second layer may deteriorate. On the other hand, by setting the growth temperature Tg2 to 1050 ° C. or higher, a second layer having good crystal quality can be obtained. On the other hand, if the growth temperature Tg2 is more than 1100 ° C., the surface of the second layer may be roughened. On the other hand, by setting the growth temperature Tg2 to 1100 ° C. or lower, the surface roughness of the second layer can be suppressed.

(3) Effects obtained by the present embodiment According to the present embodiment, one or more of the following effects can be obtained.

(A) The vapor phase growth step S140 includes a first layer growth step S142 and a second layer growth step S144. Further, in the first layer growth step S142, the growth temperature Tg1 is set to be lower than the growth temperature Tg2 in the second layer growth step S144. Thereby, the first layer can close (thicken) the upper part of the inclusion in the substrate 20 so as to suppress the explosion of the inclusion. After that, in the second layer growth step S144, by growing the second layer with the first layer covered, the second layer having good crystal quality is stably grown while suppressing the explosion of inclusions. be able to. Specifically, by suppressing the explosion of inclusions, it is possible to suppress plastic deformation in the crystal portion that closes the upper part of the inclusions. As a result, it is possible to prevent dislocations from occurring at the upper part of the inclusion. In addition, by suppressing the explosion of inclusions, it is possible to suppress the scattering of fragments of the crystal portion that blocks the upper part of the inclusions. Thereby, the abnormal growth of the semiconductor layer 40 caused by the debris can be suppressed. As a result, it becomes possible to manufacture the semiconductor laminate 1 or the nitride crystal substrate 2 having good crystal quality. That is, it is possible to further improve the crystal quality of the semiconductor laminate 1 or the nitride crystal substrate 2 as compared with the conventional method.

(B) The growth temperature Tg1 in the first layer growth step S142 is set to be equal to or lower than the critical temperature at which inclusion explosion is suppressed. As a result, in the first layer growth step S142, the first layer can be grown while suppressing the explosion of inclusions. As a result, the first layer can stably close the upper part of the inclusion in the substrate 20.

(C) The thickness of the first layer is set to be equal to or greater than the critical thickness at which the explosion of inclusions is suppressed when the temperature of the substrate 20 is heated to the growth temperature Tg2 in the second layer growth step S144. As a result, even if the temperature of the substrate 20 is heated to the growth temperature Tg2 in the second layer growth step S144 and the inclusion pressure in the substrate 20 rises, it is possible to prevent the first layer at the upper part of the inclusion from being destroyed. can do. As a result, the explosion of inclusions can be suppressed in the second layer growth step S144.

(D) By growing the second layer while suppressing the explosion of inclusions by the first layer in the second layer growth step S144, the growth temperature in the second layer growth step S144 is set to be good for the group III nitride semiconductor. It can be raised to a temperature at which crystal quality is obtained. As a result, the formation of pits on the upper surface of the second layer can be suppressed.

<Other Embodiments>
The embodiments of the present invention have been specifically described above. However, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist thereof.

In the above embodiment, the case where each of the seed crystal substrate 20 and the nitride crystal substrate 2 is a GaN free-standing substrate has been described, but each of the seed crystal substrate 20 and the nitride crystal substrate 2 is not limited to the GaN free-standing substrate. For example, group III nitride semiconductors such as aluminum nitride (AlN), aluminum gallium nitride (AlGaN), indium gallium nitride (InN), indium gallium nitride (InGaN), and aluminum indium gallium nitride (AlInGaN), that is, Al _x In _y. It may be a self-supporting substrate made of a Group III nitride semiconductor represented by the composition formula of Ga _1-x-y N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

The seed crystal substrate 20 may be a substrate whose surface layer is at least a group III nitride semiconductor. For example, a support substrate made of sapphire or the like and Al _x In _y Ga _1-xy N (0 ≦ x ≦). It may be a group III nitride semiconductor template having a semiconductor layer made of a group III nitride semiconductor represented by the composition formula of 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1).

In the above-described embodiment, the case where the MPS substrate 10 is used in the liquid phase growth step S112 has been described, but a group III nitride semiconductor self-supporting substrate or a group III nitride semiconductor template is used as the base substrate in the liquid phase growth step S112. You may.

In the above-described embodiment, the case where the flux method is used as the liquid phase growth method in the liquid phase growth step S112 has been described, but in the liquid phase growth step S112, for example, the amonothermal method or the high temperature and high pressure synthesis method may be used. ..

In the above-described embodiment, the method of preparing the seed crystal substrate 20 formed by the liquid phase growth method in the substrate preparation step S110 has been described, but in the substrate preparation step S110, the seed crystal substrate 20 formed by another method is used. You may prepare it. For example, the seed crystal substrate 20 formed by the method described in Japanese Patent No. 3533938 may be prepared.

In the above-described embodiment, the case where the seed crystal substrate 20 whose surface layer contains the sinus 20a is used has been described, but the seed crystal substrate 20 whose surface layer contains only inclusions (only the sinus 20a filled with inclusions) may be used. In this case, if the temperature of the substrate 20 is raised to a predetermined growth temperature, inclusions may explode. Therefore, in such a case, it is effective to apply the above-mentioned third embodiment.

In the above-described embodiment, in the etching step S130, at least a part of the vaporized residual impurities 31 is deposited on the upper surface of the substrate 20, and at least a part of the residual impurities 31 precipitated on the upper surface of the substrate 20 is removed together with GaN by an etching gas. However, the etching gas supplied to the upper surface of the substrate 20 may enter the cavity 20a of the substrate 20. In this case, the etching gas that has entered the cavity 20a of the substrate 20 etches the inner wall of the cavity 20a. At this time, the residual impurities 31 remaining in the cavity 20a do not have to be etched by the etching gas. As the etching of the inner wall of the cave 20a progresses, the etching gas also enters between the inner wall of the cave 20a and the residual impurities 31. When all the portions of the inner wall of the cave 20a that are in contact with the residual impurities 31 are etched, the residual impurities 31 are peeled off from the inner wall of the cave 20a. The peeled residual impurities 31 are removed (discharged) to the outside of the substrate 20 according to the flow of the etching gas with respect to the upper surface of the substrate 20. Even in such a case, the residual impurities 31 remaining in the cavity 20a of the substrate 20 can be removed together with the GaN constituting the matrix of the substrate 20.

In the above-described embodiment, the case where the HVPE method is used as the vapor phase growth method in the vapor phase growth step S140 has been described. However, in the vapor phase growth step S140, for example, the organic metal vapor deposition method (MOVPE) May be used. However, when it is necessary to increase the growth rate of the semiconductor layer 40, it is preferable to use the HVPE method.

In the above-described embodiment, doping in the vapor phase growth step S140 has not been described, but in order to impart predetermined conductivity or insulation to the semiconductor layer 40, impurities are added to the semiconductor layer 40 in the vapor phase growth step S140. It may be doped.

In the first and third embodiments described above, the case where the etching step S130 and the vapor phase growth step S140 are continuously performed in the processing chamber 401 of the same vapor phase growth apparatus 400 has been described, but the etching step S130 has been described. And the vapor phase growth step S140 may be performed by different devices. However, it is preferable that the etching step S130 and the vapor phase growth step S140 are continuously performed in the processing chamber 401 of the same vapor phase growth apparatus 400 because contamination of the interface between the substrate 20 and the semiconductor layer 40 can be suppressed.

In the second embodiment described above, the case where the vaporization step S120 to the vapor phase growth step S140 are continuously performed in the processing chamber 401 of the same vapor phase growth apparatus 400 has been described. The vapor phase growth step S140 may be performed by different devices. However, it is preferable that the vaporization step S120 to the vapor phase growth step S140 are continuously performed in the processing chamber 401 of the same vapor phase growth apparatus 400 because contamination of the interface between the substrate 20 and the semiconductor layer 40 can be suppressed.

In the third embodiment described above, the case where the first layer and the second layer are each made of GaN has been described, but the first layer and the second layer may be made of different group III nitride semiconductors.

In the above-described embodiment, the case where the manufacturing method of the present invention having the etching step S130 is applied when the semiconductor laminate 1 is sliced to manufacture the nitride crystal substrate 2 has been described, but the Schottky barrier diode (SBD) has been described. ), The manufacturing method of the present invention may be applied when manufacturing the semiconductor laminate 1 for manufacturing a device such as a high mobility transistor (HEMT) or a light emitting element.

Hereinafter, various experimental results supporting the effects of the present invention will be described.

<1> Confirmation of the effect of the etching process <1-1> Seed crystal substrate A seed crystal substrate made of a GaN free-standing substrate was prepared by using the flux method as a liquid phase growth method. The prepared seed crystal substrate was cleaved and its cross section was observed by a differential interference microscope, a fluorescence microscope, a scanning electron microscope (SEM), or a cathodoluminescence (CL) method.

The results will be described with reference to FIGS. 16 to 19. FIG. 16A is a differential interference contrast image of the cross section of the seed crystal substrate, and FIG. 16B is a fluorescence image of the cross section of the seed crystal substrate. FIG. 17 is an SEM image of a cross section of the seed crystal substrate. FIG. 18 is an SEM image and a cathodoluminescence image of a cross section of the seed crystal substrate. FIG. 19 is a cathodoluminescence image of a cross section of the seed crystal substrate.

As shown in the differential interference contrast image of FIG. 16A, it was confirmed that sinuses having various shapes were formed in the seed crystal substrate by inclusion. It was also confirmed that a part of the cave reached the upper surface of the seed crystal substrate and a groove was formed on the upper surface of the seed crystal substrate.

Further, as shown in the fluorescence image of FIG. 16B, by observing the state of the crystal in the depth direction (direction perpendicular to the paper surface) of the seed crystal substrate by the fluorescence image, a plurality of caves in the seed crystal substrate can be formed. After combining, it was confirmed that a part of the cavity was opened on the upper surface of the seed crystal substrate.

Further, as shown in the SEM image of FIG. 17, it was confirmed that the sinus formed in the seed crystal substrate extends over several hundred μm in the thickness direction of the seed crystal substrate. Further, in this portion, the sinus formed in the seed crystal substrate is recessed from the upper surface side to the lower surface side of the seed crystal substrate, or conversely, is recessed from the lower surface side to the upper surface side of the seed crystal substrate. I confirmed that I would go out.

Further, as shown in the SEM image and the CL image of FIG. 18, it was confirmed that a plurality of sinuses were formed at the step bunching end in the seed crystal substrate along the extending direction of the step bunching end. ..

Further, as shown in the CL image of FIG. 19, it was confirmed that the step bunching in the seed crystal substrate was intricately formed, and that the cave formed at the step bunching end was like a limestone cave or a cave. ..

In this way, it was confirmed that a sinus having a complicated shape was formed in the seed crystal substrate prepared by the liquid phase growth method.

<1-2> Residual Impurities In order to confirm the effect of residual impurities when the seed crystal substrate (hereinafter, may be abbreviated as substrate) is heated, the following experiments were conducted.

(Comparative Example 1)
Seed crystal substrate: Same as <1-1> Vaporization process:
Gas: NH ₃ gas, temperature: 600 ° C
Etching step 1:
Solvent: Acetone, Method: Ultrasonic cleaning, Time: 5 minutes Etching step 2:
Solvent: Nitric acid, Temperature: 85 ° C, Time: 30 minutes

(Example 1)
Seed crystal substrate: Same as Comparative Example 1 Vaporization step:
Gas: NH ₃ gas, temperature: 600 ° C
Etching process:
Equipment: HVPE equipment Etching temperature: 650 ° C
Processing chamber pressure: constant (95 kPa)
Gas: N ₂ gas, HCl gas, H ₂ gas HCl gas partial pressure / N ₂ gas partial pressure: 3%
H ₂ gas partial pressure / N ₂ gas partial pressure: 5%
Etching time: 3h

The results will be described with reference to FIGS. 20 and 21. FIG. 20A is a differential interference contrast image of the upper surface of the seed crystal substrate, FIG. 20B is a differential interference contrast image of the upper surface of the seed crystal substrate of Comparative Example 1 after the vaporization step, and FIG. 20C is etching. It is a differential interference contrast image of the upper surface of the seed crystal substrate of Comparative Example 1 after the step. FIG. 21 (a) is a differential interference contrast image of the upper surface of the seed crystal substrate of Example 1 after the vaporization step, and FIG. 21 (b) is a differential interference contrast image of the upper surface of the seed crystal substrate of Example 1 after the etching step. be.

As shown in FIG. 20 (a), a plurality of cavities were opened on the upper surface of the substrate used.

As shown in FIG. 20 (b), in Comparative Example 1, at least a part of the residual impurities in the cavity of the substrate was vaporized by heating the substrate. In addition, at least a part of the vaporized residual impurities was ejected from the opening of the cave of the substrate and precipitated in the vicinity of the opening of the cave.

As shown in FIG. 20 (c), although the substrate of Comparative Example 1 after the vaporization step was washed with acetone or nitric acid, residual impurities precipitated near the opening of the cavity of the substrate could be removed. There wasn't. Since the material constituting the residual impurities was unknown, it is considered that the etching method and conditions in the etching process were not suitable for the material. Alternatively, it is also considered that the residual impurities are not easily dissolved in any solvent because the residual impurities are carbonized or nitrided by heating.

On the other hand, it was confirmed that residual impurities were removed from the substrate of Example 1 as follows.

As shown in FIG. 21 (a), also in the substrate of Example 1, at least a part of the vaporized residual impurities was ejected from the opening of the cave of the substrate and deposited in the vicinity of the opening of the cave.

As shown in FIG. 21B, in Example 1, it was confirmed that the residual impurities precipitated on the upper surface of the substrate can be removed together with the GaN constituting the matrix of the substrate by the etching step in the gas phase. .. Since the inclusion patterns in the substrate match before and after the etching process, it is clear that the precipitated residual impurities have been removed. As described above, it was confirmed that by performing the etching step of the present invention, residual impurities precipitated on the upper surface of the substrate can be removed and the upper surface of the substrate can be kept smooth.

<1-3> Semiconductor Laminates (1) Production of Semiconductor Laminates The semiconductor laminate of Comparative Example 2 and the semiconductor laminate of Example 2 were produced under the following conditions.

(Comparative Example 2)
Seed crystal substrate: Same as <1-1> and <1-2> Etching step: Not performed Gas phase growth step:
Method: HVPE method Semiconductor layer material: GaN
Growth temperature: 1050 ° C
Processing chamber pressure: constant (95 kPa)
Partial pressure of NH ₃ gas / Partial pressure of GaCl gas: 3
Flow rate of N ₂ gas / Flow rate of H ₂ gas: 5
Semiconductor layer thickness: 200 μm

(Example 2)
Seed crystal substrate: Same as Comparative Example 2 Etching step: Implementation (same as Example 1 of <1-2>)
Equipment: HVPE equipment same as the vapor phase growth process Etching temperature: 650 ° C
Processing chamber pressure: constant (95 kPa)
Gas: N ₂ gas, HCl gas, H ₂ gas HCl gas partial pressure / N ₂ gas partial pressure: 3%
H ₂ gas partial pressure / N ₂ gas partial pressure: 5%
Etching time: 3h
Vapor deposition process:
Same as Comparative Example 2

(2) Evaluation For the semiconductor laminates of Comparative Example 2 and Example 2, the dislocation density on the upper surface of the semiconductor layer was measured by the cathodoluminescence method. The dislocation density on the upper surface of the seed crystal substrate was also measured by the same method.

Further, the X-ray locking curve of the diffraction peak of the (0002) plane (c plane) was measured in the upper surface of the seed crystal substrate, the semiconductor laminate of Comparative Example 2, and the semiconductor laminate of Example 2. As a result, the radius of curvature of the c-plane in the seed crystal substrate and the c-plane in the semiconductor layer of the semiconductor laminate are based on the distribution of the diffraction peak angle (ω value) with respect to the position on the upper surface of the seed crystal substrate or the semiconductor laminate. The radius of curvature of was calculated.

(3) Results The results will be described with reference to FIG. 22. FIG. 22A is a photograph showing the appearance of the semiconductor laminate of Example 2, FIG. 22B is a cathodoluminescence image of the semiconductor laminate of Example 2, and FIG. 22C is of Comparative Example 2. It is a photograph showing the appearance of the semiconductor laminate, and (d) is a cathodoluminescence image of the semiconductor laminate of Comparative Example 2. The black dots in the CL image indicate dislocations.

The dislocation density on the upper surface of the substrate used this time was 0.5 × 10 ^{5 to} 3 × 10 ⁵ pieces / cm ² . The radius of curvature of the c-plane on the substrate was 30 m.

However, in the semiconductor laminate of Comparative Example 2, the upper surface of the semiconductor layer was rough as shown in FIG. 22 (c). In the semiconductor laminate of Comparative Example 2, the semiconductor layer grew abnormally or a non-growth region where the semiconductor layer did not grow was formed starting from the residual impurities deposited on the upper surface of the substrate during the vapor phase growth step. It is probable that the upper surface of the semiconductor layer was rough. In the semiconductor laminate of Comparative Example 2, it is considered that an inclusion explosion occurred in the substrate.

Further, in the semiconductor laminate of Comparative Example 2, many dislocations occurred in the semiconductor layer as shown in FIG. 22 (d). The semiconductor multilayer structure of Comparative Example 2, the dislocation density in the upper surface of the semiconductor layer is higher than the dislocation density in the upper surface of the seed crystal substrate was 1 × 10 ⁷ cells / cm ^2.

Further, in the semiconductor laminate of Comparative Example 2, the radius of curvature of the c-plane in the semiconductor layer was 3 m.

In Comparative Example 2, it is considered that the precipitation of residual impurities from the inside of the cavity to the upper surface of the substrate occurred in the vapor phase growth step. Therefore, in Comparative Example 2, it is considered that in the vapor phase growth step, due to the residual impurities precipitated on the upper surface of the substrate, the crystal orientation was deviated and many dislocations were formed in the semiconductor layer. Further, in Comparative Example 2, it is considered that the step flow growth was inhibited and the three-dimensional island-like growth occurred due to the residual impurities deposited on the upper surface of the substrate. Therefore, it is considered that tensile stress is generated during the growth of the semiconductor layer and the c-plane of the semiconductor layer is warped.

On the other hand, in the semiconductor laminate of Example 2, as shown in FIG. 22A, the upper surface of the semiconductor layer is a smooth mirror surface, and the surface state thereof is remarkably improved as compared with Comparative Example 2. rice field.

Further, in the semiconductor laminate of Example 2, as shown in FIG. 22B, dislocations in the semiconductor layer were remarkably reduced as compared with Comparative Example 2. In the semiconductor laminate of Example 2, the dislocation density on the upper surface of the semiconductor layer was substantially the same as the dislocation density on the upper surface of the substrate, and was 0.5 × 10 ^{5 to} 3 × 10 ⁵ pieces / cm ² .

Further, in the semiconductor laminate of Example 2, the radius of curvature of the c-plane in the semiconductor layer was 80 m.

In Example 2, it is considered that the above result was obtained by the following mechanism. That is, in Example 2, at least a part of the residual impurities remaining in the cavity of the substrate was vaporized, and at least a part of the vaporized residual impurities could be deposited on the upper surface of the substrate. Then, at least a part of the residual impurities precipitated on the upper surface of the substrate could be removed together with the GaN constituting the matrix of the substrate. As a result, the residual impurities in the cavity of the substrate could be reduced, and the outgas could be withered to the extent that it was not released from the cavity in the vapor phase growth step. By withering the residual impurities in the cavity of the substrate in the etching step, it was possible to suppress the precipitation of the residual impurities on the upper surface of the substrate when the semiconductor layer was grown in the vapor phase growth step. By suppressing the precipitation of residual impurities on the upper surface of the substrate, it is possible to suppress the occurrence of deviation of crystal orientation due to the residual impurities deposited on the upper surface of the substrate, and the formation of dislocations in the semiconductor layer is suppressed. We were able to. Further, by suppressing the precipitation of residual impurities on the upper surface of the substrate, abnormal growth of the semiconductor layer and formation of a non-growth region in which the semiconductor layer does not grow due to the residual impurities precipitated on the upper surface of the substrate are suppressed. I was able to. Further, by suppressing the precipitation of residual impurities on the upper surface of the substrate, the semiconductor layer could be grown in a step flow, and the occurrence of three-dimensional island-like growth could be suppressed. As a result, it was possible to suppress the occurrence of tensile stress during the growth of the semiconductor layer and the occurrence of warpage on the c-plane of the semiconductor layer.

As described above, in Example 2, it was confirmed that a semiconductor laminate having good crystal quality can be produced.

<2> Confirmation of the effect of two-step growth in the vapor phase growth step (1) Production of semiconductor laminate Under the following conditions, the semiconductor laminates of Comparative Examples 3 to 4 and the semiconductor laminates of Examples 3 to 4 were used. Manufactured.

(Comparative Example 3)
Seed crystal substrate: Substrate sliced from the seed crystal ingot of <1-1> Etching step: Not performed Gas phase growth step:
Method: HVPE method Two-step growth: Not implemented Semiconductor layer material: GaN
Processing chamber pressure: constant (95 kPa)
Growth temperature: Predetermined temperature within the range of 1050 to 1100 ° C. Semiconductor layer thickness: 600 μm

(Comparative Example 4)
Seed crystal substrate: Same as Comparative Example 3 Etching step: Not performed Vapor phase growth step:
Method: HVPE method Two-step growth: Not implemented Semiconductor layer material: GaN
Processing chamber pressure: constant (95 kPa)
Growth temperature: A predetermined temperature in the range of 940 to 1050 ° C., which is lower than that of Comparative Example 3. Thickness of semiconductor layer: 600 μm

(Example 3)
Seed crystal substrate: Same as Comparative Example 3 Etching step: Implementation (same as Example 1 of <1-2>)
Vapor deposition process:
Method: HVPE method Two-step growth: Not implemented Semiconductor layer material: GaN
Processing chamber pressure: constant (95 kPa)
Growth temperature: Predetermined temperature in the range of 940 to 1050 ° C. Semiconductor layer thickness: 600 μm

(Example 4)
Seed crystal substrate: Same as Comparative Example 3 Etching step: Implementation (same as Example 1 of <1-2>)
Vapor deposition process:
Method: HVPE method Two-stage growth: Implementation First layer material: GaN
First processing chamber pressure: constant (95 kPa)
First layer growth temperature: A predetermined temperature lower than the second layer growth temperature and in the range of 940 to 1050 ° C. Thickness of the first layer: 200 μm
Material of the second layer: GaN
Second processing chamber pressure: constant (95 kPa)
Second growth temperature: A predetermined temperature higher than the growth temperature of the first layer and within the range of 1050 to 1100 ° C. Thickness of the second layer: 600 μm

(2) Evaluation For the semiconductor laminates of Comparative Examples 3 to 4 and Examples 3 to 4, the dislocation density on the upper surface of the semiconductor layer was measured by the cathodoluminescence method. The dislocation density on the upper surface of the seed crystal substrate was also measured by the same method.

(3) Results The results will be described with reference to FIGS. 23 and 24. FIG. 23A is a photograph showing the appearance of the semiconductor laminate of Example 3, FIG. 23B is a cathodoluminescence image of the semiconductor laminate of Example 3, and FIG. 23C is a photograph of Example 4. It is a photograph showing the appearance of the semiconductor laminate, and (d) is a cathodoluminescence image of the semiconductor laminate of Example 4. FIG. 24A is a photograph showing the appearance of the semiconductor laminate of Comparative Example 3, FIG. 24B is a cathodoluminescence image of the semiconductor laminate of Comparative Example 3, and FIG. 24C is a photograph of Comparative Example 4. It is a photograph showing the appearance of the semiconductor laminate, and (d) is a cathodoluminescence image of the semiconductor laminate of Comparative Example 4.

The dislocation density on the upper surface of the substrate used this time was 0.5 × 10 ^{5 to} 3 × 10 ⁵ pieces / cm ² .

In the semiconductor laminate of Comparative Example 3, the upper surface of the semiconductor layer was rough as shown in FIG. 23 (a). In the semiconductor laminate of Comparative Example 3, it is probable that the inclusion explosion and the like occurred because the growth temperature in the vapor phase growth step was high. Therefore, in the semiconductor laminate of Comparative Example 3, it is considered that the upper surface of the semiconductor layer was roughened because the semiconductor layer grew abnormally starting from the crystal fragments generated by the explosion of inclusion in the vapor phase growth step.

Further, in the semiconductor laminate of Comparative Example 3, many dislocations occurred in the semiconductor layer as shown in FIG. 23 (b). In the semiconductor laminate of Comparative Example 3, the dislocation density on the upper surface of the semiconductor layer was higher than the dislocation density on the upper surface of the substrate, and was 7.7 × 10 ⁶ pieces / cm ² .

In the semiconductor laminate of Comparative Example 3, it is considered that inclusion explosion and the like occurred in the vapor phase growth step, and plastic deformation occurred in the crystal portion of the substrate that blocked the inclusion. Therefore, it is considered that many dislocations have been formed in the semiconductor layer grown on the portion where the plastic deformation of the substrate has occurred.

In the semiconductor laminate of Comparative Example 4, as shown in FIG. 23 (c), the upper surface of the semiconductor layer was flat as compared with Comparative Example 3. It is considered that the semiconductor laminate of Comparative Example 4 had a lower growth temperature in the vapor phase growth step than that of Comparative Example 3, so that the inclusion explosion was suppressed. Therefore, it is considered that the upper surface of the semiconductor layer was flat in the semiconductor laminate of Comparative Example 4.

However, in the semiconductor laminate of Comparative Example 4, as shown in FIG. 23 (d), the dislocation density on the upper surface of the semiconductor layer was not reduced. Specifically, in the semiconductor laminate of Comparative Example 4, the dislocation density on the upper surface of the semiconductor layer was 1.6 × 10 ⁶ pieces / cm ² higher than the dislocation density on the upper surface of the substrate.

In the semiconductor laminate of Comparative Example 4, it is considered that the precipitation of residual impurities from the inside of the cavity to the upper surface of the substrate occurred in the vapor phase growth step. Therefore, in Comparative Example 4, it is considered that in the vapor phase growth step, due to the residual impurities precipitated on the upper surface of the substrate, the crystal orientation was deviated and many dislocations were formed in the semiconductor layer.

On the other hand, in the semiconductor laminate of Example 3, as shown in FIG. 22 (a), the upper surface of the semiconductor layer was flat as compared with Comparative Example 3. In the semiconductor laminate of Example 3, the residual impurities in the sinus of the substrate were withered in the etching step, so that the residual impurities could be suppressed from being deposited on the upper surface of the substrate during the vapor phase growth step. As a result, it was possible to suppress abnormal growth of the semiconductor layer and formation of a non-growth region in which the semiconductor layer does not grow due to residual impurities precipitated on the upper surface of the substrate. Further, in the semiconductor laminate of Example 3, since the growth temperature in the vapor phase growth step was lower than that of Comparative Example 3, the inclusion explosion could be suppressed, and the scattering of the fragments of the crystal portion blocking the upper part of the inclusion could be suppressed. I was able to suppress it. As a result, it was possible to suppress the abnormal growth of the semiconductor layer caused by the fragments.

Further, in the semiconductor laminate of Example 3, as shown in FIG. 22B, dislocations in the semiconductor layer were remarkably reduced as compared with Comparative Examples 3 and 4. In the semiconductor laminate of Example 3, the dislocation density on the upper surface of the semiconductor layer was equal to or less than the dislocation density on the upper surface of the substrate, and was 5 × 10 ⁴ pieces / cm ² .

In the semiconductor laminate of Example 3, by suppressing the precipitation of residual impurities on the upper surface of the substrate, it is possible to suppress the occurrence of deviation of crystal orientation due to the residual impurities deposited on the upper surface of the substrate. The formation of dislocations in the semiconductor layer could be suppressed. Further, in the semiconductor laminate of Example 3, as described above, the growth temperature in the vapor phase growth step is lower than that of Comparative Example 3 and the explosion of inclusion is suppressed, so that the crystal portion that closes the upper part of inclusion is formed. It was possible to suppress plastic deformation and prevent dislocations from occurring at the top of the inclusions. As a result, the dislocation density on the upper surface of the semiconductor layer could be equal to or less than the dislocation density on the upper surface of the substrate.

However, in the semiconductor laminate of Example 3, as shown in FIG. 22A, pits may be formed on the upper surface of the semiconductor layer. When the growth temperature is low as in Example 3, the migration of atoms or molecules adsorbed on the growth interface is not active, and creeping growth (lateral growth) is unlikely to occur. That is, the lateral growth rate is relatively slow. Since cavities due to step bunching edges and unfilled holes are frequently present on the surface of the flux-grown seed crystal substrate, for example, it may be difficult to fill the pits generated from the cavities on the surface of the seed crystal substrate. Conceivable. As a result, in the semiconductor laminate of Example 3, it is considered that pits were observed on the upper surface of the semiconductor layer.

In the semiconductor laminate of Example 4, as shown in FIG. 22 (c), the upper surface of the second layer was flat as compared with Comparative Example 3. In the semiconductor laminate of Example 4, similarly to Example 3, the residual impurities in the cavity of the substrate are withered in the etching step, so that the residual impurities are suppressed from being deposited on the upper surface of the substrate during the vapor phase growth step. We were able to. As a result, it was possible to suppress abnormal growth of the semiconductor layer and formation of a non-growth region in which the semiconductor layer does not grow due to residual impurities precipitated on the upper surface of the substrate. Further, in the semiconductor laminate of Example 4, by performing the second layer growth step after the first layer growth step at a low temperature, the second layer having good crystal quality is stabilized while suppressing the explosion of inclusions. I was able to grow into. As a result, it was possible to suppress the scattering of debris in the crystal portion that blocks the upper part of the inclusion. As a result, it was possible to suppress the abnormal growth of the semiconductor layer caused by the fragments.

Further, in the semiconductor laminate of Example 4, as shown in FIG. 22D, dislocations in the semiconductor layer were remarkably reduced as compared with Comparative Examples 3 and 4. In the semiconductor laminate of Example 4, the dislocation density on the upper surface of the second layer was equal to or less than the dislocation density on the upper surface of the substrate, and was 4.3 × 10 ⁴ pieces / cm ² .

In the semiconductor laminate of Example 4, similarly to Example 3, by suppressing the precipitation of residual impurities on the upper surface of the substrate, the occurrence of deviation of the crystal orientation due to the residual impurities deposited on the upper surface of the substrate and the like occurs. Was able to be suppressed, and the formation of dislocations in the semiconductor layer could be suppressed. Further, in the semiconductor laminate of Example 4, the explosion of inclusion is suppressed by the first layer when the second layer is grown, so that the plastic deformation in the crystal portion blocking the upper part of the inclusion can be suppressed, and the upper part of the inclusion can be suppressed. It was possible to suppress the occurrence of dislocations in. As a result, the dislocation density on the upper surface of the semiconductor layer could be equal to or less than the dislocation density on the upper surface of the substrate.

Further, in the semiconductor laminate of Example 4, creeping growth in the second layer is maintained by raising the growth temperature in the second layer growth step to a temperature at which good crystal quality of the group III nitride semiconductor can be obtained. , The formation of pits on the upper surface of the second layer could be suppressed.

(summary)
As described above, in Examples 3 and 4, it was confirmed that the semiconductor laminate having good crystal quality can be produced. Among them, it was confirmed that in Example 4 in which the two-step growth was carried out, a semiconductor laminate having even better crystal quality than in Example 3 could be obtained.

<Preferable Aspect of the Present Invention>
Hereinafter, preferred embodiments of the present invention will be added.

(Appendix 1)
A step of preparing a seed crystal substrate in which at least the surface layer is made of a group III nitride semiconductor and the surface layer contains a sinus.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
Have,
In the etching step,
A method for producing a semiconductor laminate in which residual impurities remaining in the sinus of the seed crystal substrate in the step of preparing the seed crystal substrate are removed together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate. ..

(Appendix 2)
The step of preparing the seed crystal substrate is
The process of slicing a predetermined ingot to prepare the seed crystal substrate, and
The step of polishing the seed crystal substrate and
The step of cleaning the seed crystal substrate and
Including the processing step of at least one of the crystals
In the etching step,
The method for producing a semiconductor laminate according to Appendix 1, which removes the residual impurities derived from at least one of wax, a cutting fluid, an abrasive liquid, an abrasive material, and a cleaning liquid used in the processing step.

(Appendix 3)
In the etching step,
The method for producing a semiconductor laminate according to Appendix 1 or 2, wherein the exposed portion of the surface layer is etched under the condition that the region of the upper surface of the surface layer excluding the crystal defect portion is smooth.

(Appendix 4)
In the etching step,
The method for producing a semiconductor laminate according to any one of Supplementary notes 1 to 3, wherein the etching is performed in an atmosphere containing hydrogen chloride gas and hydrogen gas.

(Appendix 5)
In the etching step,
The etching was performed in an atmosphere containing the hydrogen chloride gas, the hydrogen gas and an inert gas.
The method for producing a semiconductor laminate according to Appendix 4, wherein the partial pressure of the inert gas is made higher than the partial pressures of the hydrogen chloride gas and the hydrogen gas.

(Appendix 6)
In the etching step,
The method for producing a semiconductor laminate according to Appendix 5, wherein the ratio of the partial pressures of the hydrogen chloride gas and the hydrogen gas to the partial pressure of the inert gas is 1% or more and 10% or less.

(Appendix 7)
In the etching step,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 6, wherein the etching is performed in an atmosphere free of ammonia gas.

(Appendix 8)
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 7, wherein the temperature of the substrate in the etching step is made lower than the temperature of the substrate in the step of epitaxially growing the semiconductor layer.

(Appendix 9)
In the etching step,
At least a part of the residual impurities is vaporized from the inside of the cave of the seed crystal substrate, and at least a part of the vaporized residual impurities is deposited on the upper surface of the surface layer.
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 8, wherein at least a part of the residual impurities precipitated on the upper surface of the surface layer is removed together with the group III nitride semiconductor.

(Appendix 10)
After the step of preparing the seed crystal substrate and before the step of etching, the seed crystal substrate is heated to a predetermined temperature or higher, and at least a part of the residual impurities is vaporized from the inside of the cave of the seed crystal substrate. The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 8, which has a step of etching.

(Appendix 11)
In the step of vaporizing at least a part of the residual impurities,
At least a part of the vaporized residual impurities is precipitated on the upper surface of the surface layer.
In the etching step,
The method for producing a semiconductor laminate according to Appendix 10, wherein at least a part of the residual impurities precipitated on the upper surface of the surface layer is removed together with the group III nitride semiconductor.

(Appendix 12)
In the step of vaporizing at least a part of the residual impurities,
The method for producing a semiconductor laminate according to Appendix 10 or 11, wherein the seed crystal substrate is heated to a predetermined temperature or higher and then the temperature of the seed crystal substrate is maintained for a certain period of time.

(Appendix 13)
In the step of vaporizing at least a part of the residual impurities,
A predetermined gas is supplied to the seed crystal substrate,
The flow velocity of the predetermined gas flowing on the upper surface of the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made higher than the flow velocity of the gas flowing on the upper surface of the seed crystal substrate in the etching step. The method for producing a semiconductor laminate according to any one of Supplementary note 10 to 12.

(Appendix 14)
The semiconductor according to any one of Supplementary note 10 to 13, wherein the maximum temperature of the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made higher than the temperature of the seed crystal substrate in the etching step. Method for manufacturing laminates.

(Appendix 15)
In the step of vaporizing at least a part of the residual impurities,
The method for producing a semiconductor laminate according to any one of Supplementary note 10 to 14, wherein the pressure in the processing chamber containing the seed crystal substrate is changed up and down.

(Appendix 16)
Any one of Appendix 10 to 15 that lowers the minimum pressure in the processing chamber containing the seed crystal substrate in the step of vaporizing at least a part of the residual impurities to be lower than the pressure in the processing chamber in the step of etching. The method for producing a semiconductor laminate according to.

(Appendix 17)
Any of Appendix 1 to 16 in which the flow velocity of the gas flowing on the upper surface of the seed crystal substrate in the etching step is made higher than the flow velocity of the gas flowing on the upper surface of the seed crystal substrate in the step of epitaxially growing the semiconductor layer. The method for producing a semiconductor laminate according to one.

(Appendix 18)
In the etching step,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 17, wherein the pressure in the processing chamber containing the seed crystal substrate is changed up and down.

(Appendix 19)
The step of epitaxially growing the semiconductor layer is
A step of growing a first layer made of a group III nitride semiconductor on the seed crystal substrate, and
A step of growing a second layer made of a group III nitride semiconductor on the first layer, and
Have,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 18, wherein the growth temperature in the step of growing the first layer is lower than the growth temperature in the step of growing the second layer.

(Appendix 20)
In the step of preparing the seed crystal substrate,
As the seed crystal substrate, a substrate having inclusions on the surface layer is prepared.
In the step of growing the first layer,
The method for producing a semiconductor laminate according to Appendix 19, wherein the first layer closes the upper part of the inclusion in the seed crystal substrate so as to suppress the explosion of the inclusion.

(Appendix 21)
In the step of preparing the seed crystal substrate,
As the seed crystal substrate, a substrate having inclusions on the surface layer is prepared.
In the step of growing the first layer,
The method for producing a semiconductor laminate according to Appendix 19 or 20, wherein the growth temperature is equal to or lower than the critical temperature at which the explosion of the inclusion is suppressed.

(Appendix 22)
In the step of preparing the seed crystal substrate,
As the seed crystal substrate, a substrate having inclusions on the surface layer is prepared.
In the step of growing the first layer,
Addendum 19 that the thickness of the first layer is equal to or greater than the critical thickness at which the explosion of the inclusion is suppressed when the temperature of the seed crystal substrate is heated to the growth temperature in the step of growing the second layer. The method for producing a semiconductor laminate according to any one of ~ 21.

(Appendix 23)
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 22, wherein the etching step and the step of epitaxially growing the semiconductor layer are continuously performed in the same processing chamber.

(Appendix 24)
In the step of preparing the seed crystal substrate,
The method for producing a semiconductor laminate according to any one of Supplementary note 1 to 23, wherein a substrate having at least the surface layer formed by a liquid phase growth method is prepared as the seed crystal substrate.

(Appendix 25)
A step of preparing a seed crystal substrate made of a group III nitride semiconductor in which at least the surface layer of the crystal containing inclusions in the crystal is polished.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
Have,
In the etching step,
Semiconductor lamination that removes residual impurities containing the inclusions remaining at least on the surface layer of the seed crystal substrate in the step of preparing the seed crystal substrate together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate. How to make things.

(Appendix 26)
A step of preparing a seed crystal substrate in which at least the surface layer is made of a group III nitride semiconductor and the surface layer contains a sinus.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
A step of slicing the semiconductor layer to prepare a nitride crystal substrate, and
Have,
In the etching step,
Production of a nitride crystal substrate that removes residual impurities remaining in the sinus of the seed crystal substrate in the step of preparing the seed crystal substrate together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate. Method.

(Appendix 27)
A step of preparing a seed crystal substrate made of a group III nitride semiconductor in which at least the surface layer of the crystal containing inclusions in the crystal is polished.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
A step of slicing the semiconductor layer to prepare a nitride crystal substrate, and
Have,
In the etching step,
A nitride that removes residual impurities containing the inclusions remaining at least on the surface layer of the seed crystal substrate in the step of preparing the seed crystal substrate together with the group III nitride semiconductor constituting at least the surface layer of the seed crystal substrate. Method for manufacturing a crystal substrate.

1 Semiconductor laminate 2 Nitride crystal substrate 20 kinds of crystal substrate (substrate)
31 Residual impurities 40 Semiconductor layer

Claims (19)

A step of preparing a seed crystal substrate in which at least the surface layer is made of a group III nitride semiconductor and the surface layer contains a sinus.
A step of heating the seed crystal substrate to a predetermined temperature or higher and vaporizing at least a part of residual impurities remaining in the cave of the seed crystal substrate from the inside of the cave in the step of preparing the seed crystal substrate.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
Have,
In the step of vaporizing at least a part of the residual impurities,
A predetermined gas is supplied to the seed crystal substrate,
The flow velocity of the predetermined gas flowing on the upper surface of the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made higher than the flow velocity of the gas flowing on the upper surface of the seed crystal substrate in the etching step. ,
In the etching step,
Method for producing a front chopped distillate impurity, the group III nitride semiconductor semiconductor multilayer structure to remove with constituting at least the surface layer of the seed crystal substrate. A step of preparing a seed crystal substrate in which at least the surface layer is made of a group III nitride semiconductor and the surface layer contains a sinus.
A step of heating the seed crystal substrate to a predetermined temperature or higher and vaporizing at least a part of residual impurities remaining in the cave of the seed crystal substrate from the inside of the cave in the step of preparing the seed crystal substrate.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
Have,
The minimum pressure in the processing chamber containing the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made lower than the pressure in the processing chamber in the step of etching .
In the etching step,
The residual impurities are removed together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate.
A method for manufacturing a semiconductor laminate. The step of preparing the seed crystal substrate is
The process of slicing a predetermined ingot to prepare the seed crystal substrate, and
The step of polishing the seed crystal substrate and
The step of cleaning the seed crystal substrate and
Including the processing step of at least one of the crystals
In the etching step,
The method for producing a semiconductor laminate according to claim 1 or 2 , wherein the residual impurities derived from at least one of wax, a cutting fluid, an abrasive liquid, an abrasive material, and a cleaning liquid used in the processing step are removed. In the etching step,
The method for producing a semiconductor laminate according to any one of claims 1 to 3, wherein the exposed portion of the surface layer is etched under the condition that the region of the upper surface of the surface layer excluding the crystal defect portion is smooth. In the step of vaporizing at least a part of the residual impurities,
At least a part of the vaporized residual impurities is precipitated on the upper surface of the surface layer.
In the etching step,
At least a part of the residual impurities precipitated on the upper surface of the surface layer is removed together with the group III nitride semiconductor.
The method for producing a semiconductor laminate according to any one of claims 1 to 4. In the step of vaporizing at least a part of the residual impurities,
After heating the seed crystal substrate to a predetermined temperature or higher, the temperature of the seed crystal substrate is maintained for a certain period of time.
The method for producing a semiconductor laminate according to any one of claims 1 to 5. The maximum temperature of the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made higher than the temperature of the seed crystal substrate in the step of etching.
The method for producing a semiconductor laminate according to any one of claims 1 to 6. In the step of vaporizing at least a part of the residual impurities,
The pressure in the processing chamber containing the seed crystal substrate is changed up and down.
The method for producing a semiconductor laminate according to any one of claims 1 to 7. The step of epitaxially growing the semiconductor layer is
A step of growing a first layer made of a group III nitride semiconductor on the seed crystal substrate, and
A step of growing a second layer made of a group III nitride semiconductor on the first layer, and
Have,
The method for producing a semiconductor laminate according to any one of claims 1 to 8 , wherein the growth temperature in the step of growing the first layer is lower than the growth temperature in the step of growing the second layer. In the step of preparing the seed crystal substrate,
As the seed crystal substrate, a substrate having inclusions on the surface layer is prepared.
In the step of growing the first layer,
The method for producing a semiconductor laminate according to claim 9 , wherein the growth temperature is set to be equal to or lower than the critical temperature at which the explosion of the inclusion is suppressed. In the step of preparing the seed crystal substrate,
As the seed crystal substrate, a substrate having inclusions on the surface layer is prepared.
In the step of growing the first layer,
Claim that the thickness of the first layer is equal to or greater than the critical thickness at which the explosion of the inclusion is suppressed when the temperature of the seed crystal substrate is heated to the growth temperature in the step of growing the second layer. The method for producing a semiconductor laminate according to 9 or 10. The method for producing a semiconductor laminate according to any one of claims 1 to 11 , wherein the etching step and the step of epitaxially growing the semiconductor layer are continuously performed in the same processing chamber. In the step of preparing the seed crystal substrate,
The method for producing a semiconductor laminate according to any one of claims 1 to 12 , wherein a substrate having at least the surface layer formed by a liquid phase growth method is prepared as the seed crystal substrate. A step of preparing a seed crystal substrate made of a group III nitride semiconductor in which at least the surface layer of the crystal containing inclusions in the crystal is polished.
The seed crystal substrate is heated to a predetermined temperature or higher, and at least a part of residual impurities including the inclusions remaining on the surface layer of the seed crystal substrate is vaporized from the surface layer in the step of preparing the seed crystal substrate. Process and
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
Have,
In the step of vaporizing at least a part of the residual impurities,
A predetermined gas is supplied to the seed crystal substrate,
The flow velocity of the predetermined gas flowing on the upper surface of the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made higher than the flow velocity of the gas flowing on the upper surface of the seed crystal substrate in the etching step. ,
In the etching step,
Method for producing a front chopped distillate impurity, the group III nitride semiconductor semiconductor multilayer structure to remove with constituting at least the surface layer of the seed crystal substrate. A step of preparing a seed crystal substrate made of a group III nitride semiconductor in which at least the surface layer of the crystal containing inclusions in the crystal is polished.
The seed crystal substrate is heated to a predetermined temperature or higher, and at least a part of residual impurities including the inclusions remaining on the surface layer of the seed crystal substrate is vaporized from the surface layer in the step of preparing the seed crystal substrate. Process and
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
Have,
The minimum pressure in the processing chamber containing the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made lower than the pressure in the processing chamber in the step of etching.
In the etching step,
The residual impurities are removed together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate.
A method for manufacturing a semiconductor laminate. A step of preparing a seed crystal substrate in which at least the surface layer is made of a group III nitride semiconductor and the surface layer contains a sinus.
A step of heating the seed crystal substrate to a predetermined temperature or higher and vaporizing at least a part of residual impurities remaining in the cave of the seed crystal substrate from the inside of the cave in the step of preparing the seed crystal substrate.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
A step of slicing the semiconductor layer to prepare a nitride crystal substrate, and
Have,
In the step of vaporizing at least a part of the residual impurities,
A predetermined gas is supplied to the seed crystal substrate,
The flow velocity of the predetermined gas flowing on the upper surface of the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made higher than the flow velocity of the gas flowing on the upper surface of the seed crystal substrate in the etching step. ,
In the etching step,
The pre-chopped distillate impurities, at least the group III nitride crystal substrate manufacturing method of removing with a nitride semiconductor that constitutes the surface layer of the seed crystal substrate. A step of preparing a seed crystal substrate in which at least the surface layer is made of a group III nitride semiconductor and the surface layer contains a sinus.
A step of heating the seed crystal substrate to a predetermined temperature or higher and vaporizing at least a part of residual impurities remaining in the cave of the seed crystal substrate from the inside of the cave in the step of preparing the seed crystal substrate.
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
A step of slicing the semiconductor layer to prepare a nitride crystal substrate, and
Have,
The minimum pressure in the processing chamber containing the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made lower than the pressure in the processing chamber in the step of etching.
In the etching step,
The residual impurities are removed together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate.
A method for manufacturing a nitride crystal substrate. A step of preparing a seed crystal substrate made of a group III nitride semiconductor in which at least the surface layer of the crystal containing inclusions in the crystal is polished.
The seed crystal substrate is heated to a predetermined temperature or higher, and at least a part of residual impurities including the inclusions remaining on the surface layer of the seed crystal substrate is vaporized from the surface layer in the step of preparing the seed crystal substrate. Process and
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
A step of slicing the semiconductor layer to prepare a nitride crystal substrate, and
Have,
In the step of vaporizing at least a part of the residual impurities,
A predetermined gas is supplied to the seed crystal substrate,
The flow velocity of the predetermined gas flowing on the upper surface of the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made higher than the flow velocity of the gas flowing on the upper surface of the seed crystal substrate in the etching step. ,
In the etching step,
The pre-chopped distillate impurities, at least the group III nitride crystal substrate manufacturing method of removing with a nitride semiconductor that constitutes the surface layer of the seed crystal substrate. A step of preparing a seed crystal substrate made of a group III nitride semiconductor in which at least the surface layer of the crystal containing inclusions in the crystal is polished.
The seed crystal substrate is heated to a predetermined temperature or higher, and at least a part of residual impurities including the inclusions remaining on the surface layer of the seed crystal substrate is vaporized from the surface layer in the step of preparing the seed crystal substrate. Process and
A step of etching at least the exposed portion of the surface layer of the seed crystal substrate in the gas phase,
A step of epitaxially growing a semiconductor layer made of a group III nitride semiconductor on the seed crystal substrate by a vapor phase growth method.
A step of slicing the semiconductor layer to prepare a nitride crystal substrate, and
Have,
The minimum pressure in the processing chamber containing the seed crystal substrate in the step of vaporizing at least a part of the residual impurities is made lower than the pressure in the processing chamber in the step of etching.
In the etching step,
The residual impurities are removed together with at least the group III nitride semiconductor constituting the surface layer of the seed crystal substrate.
A method for manufacturing a nitride crystal substrate.

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