JP2010212608A - Method of machining wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of machining a wafer with which a wafer can be easily handled even if its thickness is reduced, and a laminated device that can be formed without damage. <P>SOLUTION: The method of machining the wafer includes: a backside grinding step of grinding into a predetermined thickness a backside, corresponding to a device area, of the wafer with which devices are formed over a plurality of areas partitioned by a plurality of streets arrayed in a lattice shape on a front surface of a substrate, and forming an annular reinforcing part along its outer circumference; a backside etching step of etching the ground backside of the wafer to protrude an electrode from the backside corresponding to the device area in the substrate; a resin layer-coating step of coating the backside, corresponding to the device area in the substrate, of the wafer with a resin layer to embed the electrode protruded from the backside corresponding to the device area in the substrate; and a resin layer turning step of turning the resin layer coating the backside, corresponding to the device area in the substrate, of the wafer to expose an end face of the electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention has a device region in which a device is formed in a plurality of regions partitioned by a plurality of streets arranged in a lattice pattern on the surface of a substrate, and an outer peripheral surplus region surrounding the device region, the device region The present invention relates to a wafer processing method for forming a wafer in which an electrode is embedded in a substrate having a predetermined thickness.

  In the semiconductor device manufacturing process, a plurality of regions are partitioned by dividing lines called streets arranged in a lattice pattern on the surface of a substantially wafer-shaped semiconductor wafer, and devices such as ICs, LSIs, etc. are partitioned in the partitioned regions. Form. The semiconductor wafer formed in this way is generally divided into individual devices by cutting along a street using a cutting device, and is widely used in electrical equipment.

  On the other hand, in recent years, laminated devices in which individual devices are laminated have been put into practical use in order to reduce the size of electrical equipment. A manufacturing method of a laminated device in which individual devices are laminated is disclosed in Patent Document 1 below. In the method for manufacturing a laminated device disclosed in Patent Document 1 below, the back surface of a wafer is ground to a predetermined thickness, and the front and back surfaces of a plurality of wafers whose back surfaces are ground in this manner face each other. Are joined so as to coincide with each other to form a laminated wafer, and then the laminated wafer is cut along a street by a dicing apparatus such as a cutting apparatus to form a laminated device.

Japanese Patent No. 3646720

  Thus, a laminated device in which individual devices are laminated has a large thickness, and there is a limit in reducing the size and weight. That is, when the back surface of the wafer is ground to form a wafer having a thickness of 50 μm or less, the rigidity is lowered, making it difficult to handle in a subsequent process. In addition, in order to stack the devices, it is necessary to make the electrodes embedded in each device protrude from the back surface of the wafer. If the devices are stacked with the electrodes protruding from the back surface, a space is created between the devices and the devices are damaged. There is a problem.

  The present invention has been made in view of the above-mentioned facts, and provides a wafer processing method that can be easily handled even if the wafer thickness is reduced and can form a laminated device without being damaged. is there.

In order to solve the above-mentioned main technical problem, according to the present invention, a device region in which devices are formed in a plurality of regions partitioned by a plurality of streets arranged in a lattice pattern on the surface of the substrate and the device region are surrounded. A processing method of a wafer having an outer peripheral surplus region, and an electrode embedded in a substrate in a device region,
Grinding the back surface corresponding to the device region in the wafer substrate to form a predetermined thickness, and forming an annular reinforcing portion in the region corresponding to the outer peripheral surplus region; and
Etching the back surface of the substrate of the wafer on which the back surface grinding step has been performed, and a back surface etching step of projecting the electrode from the back surface corresponding to the device region of the substrate;
A resin layer coating step in which a resin layer is coated on the back surface corresponding to the device region of the wafer substrate on which the back surface etching step has been performed, and an electrode protruding from the back surface corresponding to the device region on the substrate is buried;
A resin layer turning step of turning the resin layer coated on the back surface corresponding to the device region of the wafer substrate to expose the end face of the electrode,
A method for processing a wafer is provided.

After performing the resin layer turning step, a wafer dividing step is performed in which the wafer is cut along the streets and divided into individual devices.
In addition, after performing the resin layer turning process, a plurality of wafers are laminated to form a laminated wafer, and the laminated wafer is cut along the streets and divided into individual laminated devices.

According to the present invention, since the back surface corresponding to the device region on the substrate of the wafer is ground and formed to a predetermined thickness, the back surface grinding step of forming the annular reinforcing portion in the region corresponding to the outer peripheral surplus region is performed. Even if the device region is formed to be extremely thin, the annular reinforcing portion remains and the rigidity is secured, so that subsequent handling is not difficult. Therefore, since the thickness of the device region can be reduced, it is possible to obtain a laminated device having a thin overall thickness even when laminated in multiple layers.
In addition, according to the present invention, a back surface etching process is performed in which the back surface of the wafer substrate on which the back surface grinding process has been performed is etched to protrude an electrode from the back surface corresponding to the device area on the substrate. After performing the resin layer coating process that covers the resin layer on the back surface corresponding to the surface and embeds the electrode protruding from the back surface of the substrate, the resin layer coated on the back surface corresponding to the device area on the wafer substrate is turned. Since the resin layer turning process that exposes the end face of the electrode is performed, since the resin layer is coated on the back surface of the device, there is no space between the devices even if the devices are stacked. Absent.

The perspective view of the semiconductor wafer as a wafer divided | segmented into each device with the processing method of the wafer by this invention. Sectional drawing which expands and shows the principal part of the semiconductor wafer shown in FIG. The perspective view which shows the state which affixed the protection member on the surface of the semiconductor wafer shown in FIG. The perspective view which shows the principal part of the grinding device for implementing the back surface grinding process in the processing method of the wafer by this invention. Explanatory drawing of the back surface grinding process implemented by the grinding apparatus shown in FIG. Sectional drawing of the semiconductor wafer in which the back surface grinding process shown in FIG. 5 was implemented. Sectional drawing of the plasma etching apparatus for implementing the back surface etching process in the processing method of the wafer by this invention. Sectional drawing of the semiconductor wafer in which the back surface etching process shown in FIG. 7 was implemented. Explanatory drawing of the resin layer coating | coated process in the processing method of the wafer by this invention. Sectional drawing of the semiconductor wafer in which the resin layer coating process shown in FIG. 9 was implemented. The perspective view which shows the principal part of the turning apparatus for implementing the resin layer turning process in the processing method of the wafer by this invention. Explanatory drawing of the resin layer turning process implemented by the turning apparatus shown in FIG. Sectional drawing of the semiconductor wafer in which the resin layer turning process shown in FIG. 12 was implemented. Explanatory drawing of the wafer support process in the processing method of the wafer by this invention. The principal part perspective view of the cutting device for implementing the wafer division | segmentation process in the processing method of the wafer by this invention. Explanatory drawing of the wafer division | segmentation process in the processing method of the wafer by this invention. FIG. 17 is a perspective view of a device in which a semiconductor wafer is divided by the wafer dividing step shown in FIG. 16. Explanatory drawing of the wafer lamination process in the processing method of the wafer by this invention. Explanatory drawing of the cyclic | annular reinforcement part removal process in the processing method of the wafer by this invention. Explanatory drawing of the 2nd wafer lamination process in the processing method of the wafer by this invention. Explanatory drawing of the base wafer grinding process in the processing method of the wafer by this invention. Explanatory drawing which shows other embodiment of the wafer support process in the processing method of the wafer by this invention. Explanatory drawing which shows other embodiment of the wafer division | segmentation process in the processing method of the wafer by this invention. The perspective view of the lamination | stacking device by which the lamination | stacking wafer was divided | segmented by the wafer division | segmentation process shown in FIG.

DESCRIPTION OF EMBODIMENTS Hereinafter, preferred embodiments of a wafer processing method according to the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a perspective view of a semiconductor wafer as a wafer processed by the wafer processing method according to the present invention. In the semiconductor wafer 2 shown in FIG. 1, for example, a plurality of streets 21 are arranged in a lattice pattern on a surface 20a of a silicon substrate 20 having a thickness of 700 μm, and an IC is formed in a plurality of regions partitioned by the plurality of streets 21. A device 22 such as an LSI is formed. The semiconductor wafer 2 includes a plurality of bonding pads 23 disposed on the surface of the device 22 as shown in FIG. 2, and a metal such as copper embedded in the silicon substrate 20 connected to the bonding pads 23. An electrode 24 made of a material is provided. The semiconductor wafer 2 configured as described above includes a device region 220 in which the device 22 is formed, and an outer peripheral surplus region 230 surrounding the device region 220.

  In the wafer processing method according to the present invention, the back surface corresponding to the device region 220 in the silicon substrate 20 of the semiconductor wafer 2 shown in FIGS. 1 and 2 is ground to a predetermined thickness, and the outer peripheral surplus region 230 is formed. Before the back surface grinding step for forming the annular reinforcing portion in the corresponding region is performed, the protective member 3 for protecting the device 22 on the surface 20a of the silicon substrate 20 of the semiconductor wafer 2 is provided as shown in FIG. It sticks (protection member sticking process). Therefore, the semiconductor wafer 2 has a form in which the back surface 20b of the silicon substrate 20 is exposed.

  When the protective member attaching step is performed, the region corresponding to the device region 220 on the back surface 20b of the silicon substrate 20 of the semiconductor wafer 2 is ground to a predetermined thickness, and the region corresponding to the outer peripheral surplus region 230 is formed. A back grinding process for forming an annular reinforcing portion is performed. This back grinding process is performed by a grinding apparatus shown in FIG. The grinding apparatus 4 shown in FIG. 4 includes a chuck table 41 that holds a wafer as a workpiece, and a grinding means 42 that grinds the processed surface of the wafer held on the chuck table 41. The chuck table 41 is configured so that the wafer is sucked and held on the holding surface, which is the upper surface, and rotated in the direction indicated by the arrow 41a in FIG. The grinding means 42 includes a spindle housing 421, a rotating spindle 422 that is rotatably supported by the spindle housing 421 and rotated by a rotation driving mechanism (not shown), a mounter 423 attached to the lower end of the rotating spindle 422, and the mounter And a grinding wheel 424 attached to the lower surface of 423. The grinding wheel 424 includes a disk-shaped base 425 and a grinding wheel 426 that is annularly mounted on the lower surface of the base 425, and the base 425 is attached to the lower surface of the mounter 423.

  In order to perform the back surface grinding process using the grinding apparatus 4 described above, the protective member 3 side of the semiconductor wafer 2 conveyed by the wafer carry-in means (not shown) is placed on the upper surface (holding surface) of the chuck table 41, The semiconductor wafer 2 is sucked and held on the chuck table 41 by operating a suction means (not shown). Here, the relationship between the semiconductor wafer 2 held on the chuck table 41 and the annular grinding wheel 426 constituting the grinding wheel 424 will be described with reference to FIG. The rotation center P1 of the chuck table 41 and the rotation center P2 of the annular grinding wheel 426 are eccentric, and the outer diameter of the annular grinding wheel 426 is the boundary line between the device region 220 and the outer peripheral surplus region 230 of the semiconductor wafer 2. The size is set to be smaller than the diameter of 240 and larger than the radius of the boundary line 240, and the annular grinding wheel 426 passes through the rotation center P 1 (center of the semiconductor wafer 2) of the chuck table 41.

  Next, as shown in FIGS. 4 and 5, while rotating the chuck table 41 in the direction indicated by the arrow 41a at a rotational speed of, for example, 300 rpm, the grinding wheel 424 is rotated in the direction indicated by the arrow 424a, for example, at a rotational speed of 6000 rpm. At the same time, the grinding wheel 424 is moved downward to bring the grinding wheel 426 into contact with the back surface 20 b of the silicon substrate 20 of the semiconductor wafer 2. Then, the grinding wheel 424 is ground and fed downward by a predetermined amount at a predetermined grinding feed speed. As a result, as shown in FIG. 6, the back surface of the silicon substrate 20 of the semiconductor wafer 2 is ground and removed from the region corresponding to the device region 220 to form a circular recess 221, and an annular reinforcing portion is formed in the outer peripheral surplus region 230. 231 is formed. And the device area | region 220 in which the circular recessed part 221 was formed is formed in thickness, for example to 30 micrometers, and the end surface of the electrode 24 is exposed to the back surface 220b. Thus, even if the thickness of the device region 220 is extremely thin, for example, 30 μm, the annular reinforcing portion 231 remains and the rigidity is ensured in the semiconductor wafer 2, so that subsequent handling is not difficult.

  If the back surface grinding process mentioned above was implemented, the back surface etching process which etches the back surface of the semiconductor wafer 2 and makes the electrode 24 project from the back surface 220b corresponding to the device region 220 in the silicon substrate 20 of the semiconductor wafer 2 is performed. This back surface etching step is performed using the plasma etching apparatus shown in FIG. 7 in the illustrated embodiment. The plasma etching apparatus 5 shown in FIG. 7 includes an apparatus housing 51, a lower electrode 52 disposed in the apparatus housing 51 so as to be opposed in the vertical direction, and an upper electrode 53. The lower electrode 52 includes a disk-shaped workpiece holding portion 521 and a columnar support portion 522 formed so as to protrude from the center of the lower surface of the workpiece holding portion 521. A suction chuck 521a formed of a porous ceramic material is disposed on the upper surface of the workpiece holding part 521, and the semiconductor wafer 2 subjected to the back grinding step is placed on the suction chuck 521a. Suction is held by operating a suction means (not shown). The support portion 522 is connected to the high-frequency voltage applying means 54.

The upper electrode 53 includes a disk-like gas ejection portion 531 and a columnar support portion 532 formed so as to protrude from the center of the upper surface of the gas ejection portion 531. As described above, the upper electrode 53 including the gas ejection part 531 and the columnar support part 532 is disposed so that the gas ejection part 531 faces the workpiece holding part 521 constituting the lower electrode 52. The disc-shaped gas ejection portion 531 constituting the upper electrode 53 is provided with a plurality of ejection ports 531a that open to the lower surface. The plurality of jet outlets 531 a communicate with the gas supply means 55 through a communication path 531 b formed in the gas ejection part 531 and a communication path 532 a formed in the support part 532. The gas supply means 55 supplies a mixed gas for generating plasma mainly composed of a fluorine-based gas such as sulfur hexafluoride (SF ₆ ).

  In order to perform the etching process using the plasma etching apparatus 5 configured as described above, the silicon substrate of the semiconductor wafer 2 in which the back grinding process is performed on the workpiece holding portion 521 constituting the lower electrode 52. The side of the protective tape 3 adhered to the surface of 20 is placed, and a suction means (not shown) is operated to suck and hold the semiconductor wafer 2 on the workpiece holding portion 521. Therefore, in the semiconductor wafer 2 sucked and held on the workpiece holding portion 521, the back surface of the silicon substrate 20 is on the upper side.

  Next, the gas supply means 55 is operated to supply the plasma generating gas to the upper electrode 53. The plasma generating gas supplied from the gas supply means 55 is adsorbed and held by the lower electrode 52 from the plurality of jet outlets 531a through the communication passage 532a formed in the support portion 532 and the communication passage 531b formed in the gas ejection portion 531. It is ejected toward the back surface (upper surface) of the semiconductor wafer 2 held on 521. A high frequency voltage is applied between the lower electrode 52 and the upper electrode 53 from the high frequency voltage applying means 54 with the plasma generating gas supplied in this manner. As a result, plasma is generated in the space between the lower electrode 52 and the upper electrode 53, and the active material generated by this plasma acts on the back surface of the semiconductor wafer 2, so that the back surface of the silicon substrate 20 of the semiconductor wafer 2 is etched. The

The back surface etching step is performed, for example, under the following conditions.
Output of high-frequency voltage applying means 54: 2000W
Pressure in housing 51: 80Pa
Plasma generating gas: 76 ml / min of sulfur hexafluoride (SF ₆ ), helium (He)
15 ml / min, oxygen (O ₂ ) 27 ml / min
Or
: 76 ml / min of sulfur hexafluoride (SF ₆ ), methyl trifluoride
(CHF ₃ ) 15 ml / min, oxygen (O ₂ ) 27 ml / min
Or
: Sulfur hexafluoride (SF ₆ ) 76 ml / min, nitrogen (N ₂ )
15 ml / min, oxygen (O ₂ ) 27 ml / min Etching time: 3 min

  By performing the back surface etching step under the above-described processing conditions, the back surface of the silicon substrate 20 constituting the semiconductor wafer 2 is etched by 10 μm, for example. As a result, as shown in FIG. 8, the electrode 24 protrudes 10 μm from the back surface 220 b corresponding to the device region 220 of the silicon substrate 20 of the semiconductor wafer 2. In addition, the grinding distortion produced | generated on the back surface of the silicon substrate 20 in the said back surface grinding process can be removed by implementing a back surface etching process.

  In the above-described back surface etching step, an example was shown in which plasma etching using a plasma generating gas mainly composed of a fluorine-based gas was shown. However, the back surface etching step is an etching solution composed of a mixture of nitric acid and hydrofluoric acid. You may implement by the wet etching using this.

  If the above-described back surface etching step is performed, a resin layer is coated on the back surface 220b corresponding to the device region 220 in the silicon substrate 20 constituting the semiconductor wafer 2, and protrudes from the back surface 220b corresponding to the device region 220 in the silicon substrate 20. A resin layer coating step for burying the electrode 24 is performed. In this resin layer coating step, an underfill may be provided on the back surface 220b corresponding to the device region 220. An example in which the resin layer coating step is performed using the spin coater 6 as shown in FIG. 9 will be described. The spin coater 6 includes a chuck table 61 having suction holding means, and a nozzle 62 disposed above the center of the chuck table 61. The protective member 3 attached to the surface of the semiconductor wafer 2 on which the back surface etching process has been performed is placed on the chuck table 61 of the spin coater 6, and a suction means (not shown) is operated to place it on the chuck table 61. The semiconductor wafer 2 is sucked and held. Therefore, the back side of the semiconductor wafer 2 is the upper side. Next, a predetermined amount of liquid resin 25 is dropped from the nozzle 62 onto the back surface 220b corresponding to the device region 220 in the silicon substrate 20 constituting the semiconductor wafer 2, and the chuck table 61 is rotated in the direction indicated by the arrow 61a. As a result, the liquid resin 25 flows to the outer periphery of the device region 220 in the silicon substrate 20 constituting the semiconductor wafer 2 by centrifugal force. The resin that has flowed to the outer peripheral portion on the back surface 220b corresponding to the device region 220 in the silicon substrate 20 constituting the semiconductor wafer 2 as described above is cured with time and the device region in the silicon substrate 20 as shown in FIG. The resin layer 250 is coated on the back surface 220b corresponding to 220, and the electrode 24 protruding from the back surface 220b corresponding to the device region 220 is buried. The thickness of the resin layer 250 may be 20 to 30 μm.

  If the above-described resin layer coating step is performed, the resin layer 250 covered on the back surface 220b corresponding to the device region 220 in the silicon substrate 20 constituting the semiconductor wafer 2 is turned to expose the end surface of the electrode 24. Perform the turning process. This resin layer turning process is performed using the turning apparatus shown in FIG. The turning device 7 shown in FIG. 11 is a turning that is movably mounted on a pair of guide rails 711a and 711a that are provided at the rear end portion of the device housing 71 and extend upward in front of an upright wall 711. A turning unit 72 is provided as a means. The turning unit 72 includes a moving base 73 and a bite tool mounting member 74 attached to the moving base 73. The moving base 73 is provided with a pair of legs 731 and 731 extending in the vertical direction on both sides of the rear surface. The pair of legs 731 and 731 is slidably engaged with the pair of guide rails 711a and 711a. Guided grooves 731a and 731a are formed. In this way, the cutting tool mounting member 74 is attached to the front surface of the movable base 73 slidably mounted on the pair of guide rails 711 a and 711 a provided on the upright wall 711. The cutting tool mounting member 74 is provided with a cutting tool mounting hole 741 penetrating in the vertical direction, and a female screw hole 742 extending from the front end surface corresponding to the cutting tool mounting hole 741 to the cutting tool mounting hole 741. . By inserting the bite body 751 of the bite tool 75 into the bite attachment hole 741 of the bite tool mounting member 74 configured as described above, and screwing and tightening the tightening bolt 76 into the female screw hole 742, the bite tool 75 becomes the bite tool 75. The mounting member 74 is detachably mounted. In the illustrated embodiment, the cutting tool 75 includes a cutting tool body 751 formed of a tool steel such as a super steel alloy in a rod shape, and a cutting blade formed of diamond or the like provided at the tip of the cutting tool body 751. 752 is used.

  A turning apparatus 7 shown in FIG. 11 includes a turning unit feed mechanism 77 that moves the turning unit 72 in the vertical direction (a direction perpendicular to a holding surface of a chuck table described later) along the pair of guide rails 711a and 711a. ing. The turning unit feed mechanism 77 includes a male screw rod 771 disposed in the vertical direction on the front side of the upright wall 711. The male screw rod 771 is rotatably supported at its upper end and lower end by bearing members 772 and 773 attached to the upright wall 71. The upper bearing member 772 is provided with a pulse motor 774 as a drive source for rotationally driving the male screw rod 771, and an output shaft of the pulse motor 774 is connected to the male screw rod 771 by transmission. Note that a connecting portion (not shown) that protrudes rearward from the center portion in the width direction is also formed on the rear surface of the movable base 73, and a through female screw hole extending in the vertical direction is formed in the connecting portion. The male screw rod 771 is screwed into the female screw hole. Therefore, when the pulse motor 774 rotates forward, the moving base 73, that is, the turning unit 72 is lowered or advanced, and when the pulse motor 774 reversely moves, the moving base 73, that is, the turning unit 72 is raised, or retracted.

  Further, the turning device 7 shown in FIG. 11 includes a chuck table 78 disposed in the working portion 710 of the device housing 71. The chuck table 78 includes a suction chuck 781 made of an appropriate porous material such as porous ceramics on the upper surface, and the suction chuck 781 is connected to suction means (not shown). Accordingly, the workpiece is placed on the holding surface, which is the upper surface of the suction chuck 781, and the suction means (not shown) is operated to suck and hold the workpiece on the suction chuck 781. The chuck table 78 is configured to be rotatable by a rotation driving mechanism (not shown) and is moved in the directions indicated by arrows 78a and 78b by a chuck table moving mechanism (not shown).

  In order to perform the resin layer turning process using the turning device 7 described above, the protective member 3 side adhered to the surface of the semiconductor wafer 2 on which the resin layer coating process has been performed is placed on the chuck table 78. Then, the semiconductor wafer 2 is sucked and held on the chuck table 78 by operating a suction means (not shown). Therefore, the back surface of the semiconductor wafer 2 held on the chuck table 78 is the upper side. When the semiconductor wafer 2 is sucked and held on the chuck table 78 in this way, the chuck table moving mechanism (not shown) is operated to move the chuck table 78 to the machining area where the turning unit 72 is located, as shown in FIG. The right side of the resin layer 250 covered with the back surface 220b corresponding to the device region 220 in the silicon substrate 20 constituting the semiconductor wafer 2 held on the chuck table 78 is positioned directly below the tool bit 75. Next, while turning the chuck table 78 in the direction indicated by the arrow 780 at a rotational speed of, for example, 2000 rpm, the turning unit feeding mechanism 77 is operated to move the turning unit 72 downward, and the cutting tool 75 is cut and fed. The cutting position of the cutting tool 75 is set to a position reaching the end face of the electrode 24 embedded in the device region 220 in the silicon substrate 20 constituting the semiconductor wafer 2. When the cutting unit feed mechanism 77 is operated in this way, the turning unit feed mechanism 77 is operated. For example, when the turning width of the cutting edge 752 of the cutting tool 75 is 20 tens μm, the position indicated by the solid line in FIG. For example, at a feed rate of 0.6 mm / second in the direction indicated by arrow 78a. Then, as indicated by a two-dot chain line in FIG. 12, the device region in the silicon substrate 20 constituting the semiconductor wafer 2 by the cutting edge 752 of the cutting tool 75 by moving the center of rotation of the chuck table 78 to the cutting tool 75. The resin layer 250 and the electrode 24 covered with the back surface 220b corresponding to 220 are turned, and the end face of the electrode 24 is exposed as shown in FIG. In addition, since the electrode 24 is turned by the cutting tool 75, even if it is formed of a sticky metal such as copper, no burrs are generated.

  When the resin layer turning process described above is performed, the back surface 20b of the semiconductor wafer 2 on which the resin layer turning process has been performed is mounted on the annular frame F as shown in FIGS. Adhere to T (wafer support process). Accordingly, as shown in FIG. 14B, the surface 20a of the semiconductor wafer 2 adhered to the surface of the dicing tape T is on the upper side. And the protection member 3 is peeled (protection member peeling process).

  If the wafer support process and the protective member peeling process described above are performed, the wafer dividing process for dividing the semiconductor wafer 2 into a plurality of devices 22 by cutting the semiconductor wafer 2 along the plurality of streets 21 is performed. This wafer dividing step is performed using a cutting apparatus shown in FIG. A cutting device 8 shown in FIG. 15 includes a chuck table 81 that holds a workpiece, a cutting unit 82 that includes a cutting blade 821, and an imaging unit 83. The chuck table 81 is configured to suck and hold a workpiece. The chuck table 81 is moved in a cutting feed direction indicated by an arrow X in FIG. 15 by a cutting feed means (not shown) and is indicated by an arrow Y by an index feed means (not shown). It can be moved in the index feed direction shown. On the upper surface of the chuck table 81, as shown in FIG. 16A, a step portion 811 is formed in which a circular concave portion 221 formed on the back surface of the semiconductor wafer 2 is fitted. In order to perform the wafer dividing step by the cutting device 8, the dicing tape T side on which the back surface 20 b of the semiconductor wafer 2 is adhered is placed on the chuck table 81. Then, the semiconductor wafer 2 is held on the chuck table 81 by operating a suction means (not shown). Accordingly, the semiconductor wafer 2 sucked and held on the chuck table 81 has the surface 20a on the upper side. In FIG. 16, the annular frame F to which the dicing tape T is mounted is omitted, but the annular frame F is held by an appropriate frame holding means provided on the chuck table 81.

  In this way, the chuck table 81 that sucks and holds the semiconductor wafer 2 is positioned directly below the imaging means 83 by a cutting feed means (not shown). When the chuck table 81 is positioned directly below the image pickup means 83, an alignment operation for detecting an area to be cut of the semiconductor wafer 2 is performed by the image pickup means 83 and a control means (not shown). That is, the image pickup unit 83 and a control unit (not shown) execute image processing such as pattern matching for aligning the street 21 formed in a predetermined direction of the semiconductor wafer 2 with the cutting blade 821, and cutting region Alignment is performed (alignment process). Further, the alignment of the cutting area is similarly performed on the street 21 formed in the semiconductor wafer 2 and extending in a direction orthogonal to the predetermined direction.

  When the cutting area alignment of the semiconductor wafer 2 held on the chuck table 81 is performed as described above, the chuck table 81 holding the semiconductor wafer 2 is moved to the cutting start position of the cutting area. At this time, as shown in FIG. 16A, the semiconductor wafer 2 is positioned such that one end of the predetermined street 21 (the left end in FIG. 16A) is positioned to the right by a predetermined amount from directly below the cutting blade 821. . Then, the cutting blade 821 is rotated at a predetermined rotational speed in the direction indicated by an arrow 821a in FIG. 16 (a), and is shown by a solid line in FIG. 16 (a) by a cutting feed means (not shown) from a standby position indicated by a two-dot chain line. As shown, it cuts and feeds a predetermined amount downward. As shown in FIG. 16A, the cutting feed position is the same as that shown in FIG. 16B of the resin layer 250 in which the outer peripheral edge of the cutting blade 821 is covered with the back surface 220b corresponding to the device region 220 in the back surface 20b of the semiconductor wafer 2. In a), the lower surface, that is, the position reaching the surface of the dicing tape F is set.

  If cutting feed of the cutting blade 821 is performed as described above, the chuck table 81 is moved as shown in FIG. 16 (a) while rotating the cutting blade 821 in a direction indicated by an arrow 821a in FIG. In a), it is moved at a predetermined cutting feed speed in the direction indicated by the arrow X1. When the right end of the semiconductor wafer 2 held on the chuck table 81 passes directly below the cutting blade 821, the movement of the chuck table 81 is stopped. As a result, as shown in FIG. 16B, the semiconductor wafer 2 has a resin layer 250 (see FIG. 16A) coated on the back surface of the region corresponding to the device region 23 from the front surface 20a. A reaching dividing groove 26 is formed.

  As described above, when the wafer dividing step is performed along all the streets 21 extending in the predetermined direction of the semiconductor wafer 2, the chuck table 81 is rotated by 90 degrees, and the wafer is divided with respect to the predetermined direction. The wafer dividing step is executed along each street 21 extending in the orthogonal direction. As a result, the division grooves 26 are formed along all the streets 21 in the semiconductor wafer 2, and the device region 220 is divided into individual devices 22.

  When the wafer dividing step described above is performed, the divided devices 22 are separated from the dicing tape F and picked up to obtain individual devices 22 as shown in FIG. The device 22 is formed such that the back surface is covered with the resin layer 250 and the end surface of the electrode 24 is exposed on the back surface of the resin layer 250. Accordingly, by stacking the devices 22 shown in FIG. 17, a stacked device in which the bonding pads 23 and the electrodes 24 are connected to each other can be obtained.

Next, a method of obtaining individual laminated devices by forming a laminated wafer by laminating a plurality of semiconductor wafers 2 on which the resin layer turning process described above has been performed, and cutting the laminated wafer along a plurality of streets 21. Will be described with reference to FIGS.
In order to stack the semiconductor wafer 2 on which the above-described resin layer turning process has been performed, the outer peripheral surplus region 230 of the semiconductor wafer 2 shown in FIG. 1 is cut as shown in FIG. A base wafer 2A having a diameter slightly smaller than the inner diameter of the circular recess 221 formed on the back surface of the implemented semiconductor wafer 2 is prepared. Then, as shown in FIGS. 18A and 18B, the resin layer 250 coated on the back surface 220b corresponding to the device region 230 in the semiconductor wafer 2 in which the resin layer turning process has been performed on the surface 20a of the base wafer 2A. A wafer laminating step is performed in which the wafers 21 face each other and the corresponding streets 21 are aligned and joined to form a laminated wafer. That is, as shown in FIG. 18B, a circular recess 221 formed on the back surface of the semiconductor wafer 2 is fitted into the substrate wafer 2A, and the surface 20a of the substrate wafer 2A and the device region 220 in the semiconductor wafer 2 are formed. The resin layer 250 coated on the corresponding back surface 220b is faced and ultrasonically bonded to cover the bonding pad 23 formed on the surface 20a of the base wafer 2A and the back surface 220b corresponding to the device region 230 on the semiconductor wafer 2. The exposed end surfaces of the electrodes 24 are joined to the surface of the resin layer 250 to form the laminated wafer 2B.

  If the laminated wafer 2 is formed by carrying out the wafer lamination step described above, a wafer division step described later may be carried out, but the semiconductor wafer 2 constituting the laminated wafer 2B for further laminating the semiconductor wafer 2 is also possible. An annular reinforcing portion removing step is performed to remove the annular reinforcing portion 231 so that the diameter is slightly smaller than the inner diameter of the circular concave portion 221. In the illustrated embodiment, this annular reinforcing portion removing step is performed using a laser processing apparatus shown in FIG. A laser processing apparatus 9 shown in FIG. 19A includes a chuck table 91 that holds a workpiece, and a laser beam irradiation unit 92 that irradiates the workpiece held on the chuck table 91 with a laser beam. Yes. The chuck table 91 is configured to suck and hold the workpiece. The chuck table 91 is moved in the machining feed direction indicated by an arrow X in FIG. 19A by a machining feed mechanism (not shown) and an index feed mechanism (not shown). Can be moved in the index feed direction indicated by the arrow Y. The laser beam irradiation means 92 irradiates a pulse laser beam from a condenser 922 attached to the tip of a cylindrical casing 921 arranged substantially horizontally. The illustrated laser processing apparatus 9 includes an imaging unit 93 attached to the tip of a casing 921 that constitutes the laser beam irradiation unit 92. The imaging unit 93 includes an illuminating unit that illuminates the workpiece, an optical system that captures an area illuminated by the illuminating unit, an imaging device (CCD) that captures an image captured by the optical system, and the like. The captured image signal is sent to a control means (not shown).

  In order to carry out the annular reinforcing portion removing step using the laser processing apparatus 9, the base wafer 2A side of the laminated wafer 2B is placed on the chuck table 91 of the laser processing apparatus 9 as shown in FIG. The stacked wafer 2B is sucked and held on the chuck table 91. Therefore, the laminated wafer 2B is held with the surface 20a of the semiconductor wafer 2 facing upward. Then, as shown in FIGS. 19A and 19B, a position slightly inside (for example, 1 mm) from the inner surface of the annular reinforcing portion 231 formed on the semiconductor wafer 2 is a condenser 922 of the laser beam irradiation means 92. Position it so that it is directly below. Then, as shown in FIG. 19B, the laser beam irradiating means 92 is operated, and the chuck table 91 is moved while irradiating a pulsed laser beam having a wavelength (for example, 355 nm) having absorptivity to the silicon substrate from the condenser 922. Rotate. At this time, the condensing point P of the pulsed laser beam irradiated from the condenser 922 is matched with the vicinity of the surface 20a of the semiconductor wafer 2 constituting the laminated wafer 2B. As a result, when the chuck table 91 is rotated once, as shown in FIG. 19B, the semiconductor wafer 2 is formed with the cutting groove 27 at the boundary between the device region 220 and the outer peripheral surplus region 230, and the annular reinforcing portion is formed. 231 is cut off. Accordingly, the outer diameter of the semiconductor wafer 2 is substantially the same as the outer diameter of the base wafer 2A.

  When the annular reinforcing portion removing step described above is performed, the device region 220 in the semiconductor wafer 2 to be next laminated on the surface of the semiconductor wafer 2 in the laminated wafer 2B as shown in FIGS. A second wafer laminating step is performed in which the resin layer 250 covered on the corresponding back surface 220b is faced and the streets corresponding to each other are matched to be joined. This second wafer lamination step is substantially the same as the wafer lamination step shown in FIG.

  When the second wafer laminating step is performed, the annular reinforcing portion removing step shown in FIGS. 19A and 19B is performed. Then, the second wafer laminating step and the annular reinforcing portion removing step are repeatedly performed until the set number of semiconductor wafers 2 are laminated, thereby forming a multilayer laminated wafer.

  Next, a substrate wafer grinding step is performed in which the back surface 20b of the substrate wafer 2A constituting the laminated wafer 2B is ground to a predetermined thickness. This substrate wafer grinding step is performed using a grinding apparatus shown in FIG. A grinding apparatus 10 shown in FIG. 21A includes a grinding table 103 that includes a chuck table 101 that holds a workpiece and a grinding wheel 102 that grinds the workpiece held on the chuck table 101. ing. In order to perform the base wafer grinding process using the grinding apparatus 10 configured as described above, the protective member 3 is provided on the surface of the upper semiconductor wafer 2 constituting the laminated wafer 2B as shown in FIG. After the sticking, as shown in FIG. 21A, the protective member 3 side is placed on the chuck table 101, and the laminated wafer 2B is sucked and held on the chuck table 101. Accordingly, in the laminated wafer 2B, the back surface 20b of the base wafer 2A is on the upper side. When the laminated wafer 2B is held on the chuck table 91 in this way, the grinding wheel 102 of the grinding means 103 is indicated by an arrow 102a while the chuck table 101 is rotated in the direction indicated by the arrow 101a at a rotational speed of, for example, 300 rpm. The substrate wafer 2A is ground by rotating in the direction at a rotation speed of, for example, 6000 rpm, and contacting the back surface 20b of the substrate wafer 2A to form a thickness of the substrate wafer 2A of, for example, 30 μm.

  When the above-described substrate wafer grinding process is performed, the wafer dividing process is performed in which the laminated wafer 2B is cut along the streets and divided into individual laminated devices. Prior to carrying out this dividing step, a wafer supporting step of adhering the back surface 20b of the base wafer 2A constituting the laminated wafer 2B to the surface of the dicing tape T mounted on the annular frame F as shown in FIG. carry out. Then, the protective member 3 attached to the surface of the upper semiconductor wafer 2 constituting the laminated wafer 2B is peeled off (protective member peeling step).

  When the wafer support step and the protective member peeling step are thus performed, the wafer dividing step is performed using a cutting device substantially similar to the cutting device 8 shown in FIG. When the wafer dividing step is performed, the chuck table 81 of the cutting apparatus 8 shown in FIG. That is, as shown in FIG. 23, the dicing tape T on which the laminated wafer 2B is adhered in the wafer support step described above is placed on the chuck table 81 of the cutting device 8. Then, the laminated wafer 2B is held on the chuck table 81 via the dicing tape T by operating a suction means (not shown). Accordingly, in the laminated wafer 2B held by the chuck table 81, the surface 20a of the upper semiconductor wafer 2 is on the upper side. In FIG. 23, the annular frame F to which the dicing tape T is attached is omitted, but the annular frame F is held by an appropriate frame holding means provided on the chuck table 81. Next, an alignment operation for detecting a region to be cut of the laminated wafer 2B is performed in the same manner as the wafer dividing step shown in FIGS. 15 and 16, and the street 21 formed on the semiconductor wafer 2 constituting the laminated wafer 2B. The laminated wafer 2B is cut along As a result, the laminated wafer 2B is divided into individual laminated devices. Then, by separating and picking up the divided laminated devices from the dicing tape F, individual laminated devices 22B are obtained as shown in FIG. In the laminated device 22B, since the resin layer 250 is coated on the back surface of each device 22, no space is generated between the devices 22, and the device is not damaged.

2: Semiconductor wafer 2A: Substrate wafer 2B: Stacked wafer 20: Silicon substrate 21: Street 22: Device 22B: Stacked device 23: Bonding pad 24: Electrode 220: Device region 230: Excess peripheral region 250: Resin layer 3: Protection member 4: Grinding device 5: Plasma etching device 6: Spin coater 7: Turning device 8: Cutting device 9: Laser processing device

Claims (3)

A device region in which devices are formed in a plurality of regions partitioned by a plurality of streets arranged in a lattice pattern on the surface of the substrate, and an outer peripheral surplus region surrounding the device region, and electrodes on the substrate in the device region A method for processing an embedded wafer,
Grinding the back surface corresponding to the device region in the wafer substrate to form a predetermined thickness, and forming an annular reinforcing portion in the region corresponding to the outer peripheral surplus region; and
Etching the back surface of the substrate of the wafer on which the back surface grinding step has been performed, and a back surface etching step of projecting the electrode from the back surface corresponding to the device region of the substrate;
A resin layer coating step in which a resin layer is coated on the back surface corresponding to the device region of the wafer substrate on which the back surface etching step has been performed, and an electrode protruding from the back surface corresponding to the device region on the substrate is buried;
A resin layer turning step of turning the resin layer coated on the back surface corresponding to the device region of the wafer substrate to expose the end face of the electrode,
A method for processing a wafer.   The wafer processing method according to claim 1, wherein after the resin layer turning step is performed, a wafer dividing step is performed in which the wafer is cut along a street and divided into individual devices.   2. The wafer dividing step of forming a laminated wafer by laminating a plurality of wafers after performing the resin layer turning step, and cutting the laminated wafer along a street to divide the wafer into individual laminated devices. Wafer processing method.

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