JP2010212592A - Circuit board and method for manufacturing the same - Google Patents

Circuit board and method for manufacturing the same Download PDF

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JP2010212592A
JP2010212592A JP2009059412A JP2009059412A JP2010212592A JP 2010212592 A JP2010212592 A JP 2010212592A JP 2009059412 A JP2009059412 A JP 2009059412A JP 2009059412 A JP2009059412 A JP 2009059412A JP 2010212592 A JP2010212592 A JP 2010212592A
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resist
insulating substrate
conductor
circuit board
silk
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Takehito Matsuura
猛仁 松浦
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
Sanyo Consumer Electronics Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board for improving yield by preventing solder balls from adhering to a conductor portion around a via portion by blocking the solder balls at a portion where a resist and a silk printing portion are stacked when an insulating substrate is immersed into a solder bath. <P>SOLUTION: The circuit board 1 includes: an insulating substrate 2; conductor portions 4 formed with a predetermined pattern on both surfaces of the insulating substrate 2 and conducting on both the surfaces of the insulating substrate 2 through a via portion 3 penetrating through the insulating substrate 2; a resist 5 for exposing a predetermined portion of each of the conductor portions 4 and covering the conductor portion 4; and a silk printing portion 6 for printing characters on the resist 5. In the circuit board, the resist 5 and the silk printing portion 6 are stacked to cover the conductor portion 4 around the via portion 3. The circuit board having the configuration described above provides significant effects that the yield in production of circuit boards is improved. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、絶縁基板を貫通するビア部を有した回路基板及びその製造方法に関する。   The present invention relates to a circuit board having a via portion penetrating an insulating substrate and a manufacturing method thereof.

図8はビア部を有する従来の回路基板の断面図を示している。回路基板1は絶縁基板2を貫通するビア部3が設けられる。絶縁基板2の両面には所定のパターンで形成される導体部4が形成される。導体部4はビア部3を通って絶縁基板2の両面で導通するとともに、所定位置を露出してレジスト5により覆われる。一部が露出した導体部4が形成された絶縁基板2は半田槽に浸漬される。これにより、露出した導体部4に半田が設けられ、電子部品が半田付けされる。   FIG. 8 shows a cross-sectional view of a conventional circuit board having via portions. The circuit board 1 is provided with a via portion 3 penetrating the insulating substrate 2. Conductor portions 4 formed in a predetermined pattern are formed on both surfaces of the insulating substrate 2. The conductor portion 4 is electrically connected to both surfaces of the insulating substrate 2 through the via portion 3, and a predetermined position is exposed and covered with the resist 5. The insulating substrate 2 on which the conductor part 4 that is partially exposed is formed is immersed in a solder bath. As a result, solder is provided on the exposed conductor 4 and the electronic component is soldered.

特開平7−170068号公報(第2頁−第3頁、第3図)Japanese Patent Laid-Open No. 7-170068 (pages 2 to 3 and FIG. 3)

しかしながら、上記従来の回路基板1によると、電子部品が取り付けられないビア部3の周部はレジスト5で覆われる。この時、レジスト5によるビア部3の閉塞を回避するためにビア部3内の導体部4の内縁に対してレジスト5の内縁が外側に形成される。レジスト5よりも内周側に露出した導体部4には絶縁基板2を半田槽に浸漬して取り出した際に球状の半田ボールBが付着する場合がある。この半田ボールBは付着面積が小さいため、回路基板1の製造工程中に衝撃によって外れ易い。このため、外れた半田ボールBによって回路基板1の短絡が発生し、回路基板1の歩留りが低下する問題があった。   However, according to the conventional circuit board 1, the peripheral portion of the via portion 3 to which the electronic component is not attached is covered with the resist 5. At this time, the inner edge of the resist 5 is formed outside the inner edge of the conductor part 4 in the via part 3 in order to avoid the blockage of the via part 3 by the resist 5. When the insulating substrate 2 is dipped in a solder bath and taken out from the conductor 4 exposed on the inner peripheral side of the resist 5, a spherical solder ball B may adhere. Since the solder ball B has a small adhesion area, it is easily detached by an impact during the manufacturing process of the circuit board 1. For this reason, the short circuit of the circuit board 1 occurs due to the detached solder ball B, and the yield of the circuit board 1 is reduced.

本発明は、歩留りを向上できる回路基板及びその製造方法を提供することを目的とする。   An object of this invention is to provide the circuit board which can improve a yield, and its manufacturing method.

上記目的を達成するために本発明は、絶縁基板と、前記絶縁基板の両面に所定のパターンで形成されるとともに前記絶縁基板を貫通するビア部を通って前記絶縁基板の両面で導通する導体部と、前記導体部の所定部分を露出して前記導体部を覆うレジストと、前記レジスト上に印字するシルク印刷部とを備えた回路基板において、前記レジスト及び前記シルク印刷部を積層して前記ビア部の周囲の前記導体部を覆ったことを特徴としている。   To achieve the above object, the present invention provides an insulating substrate and a conductor portion formed in a predetermined pattern on both surfaces of the insulating substrate and conducting on both surfaces of the insulating substrate through a via portion penetrating the insulating substrate. A circuit board comprising: a resist that exposes a predetermined portion of the conductor portion to cover the conductor portion; and a silk printed portion that prints on the resist; The conductor portion around the portion is covered.

この構成によると、絶縁基板上にはレジストにより覆われて一部が露出する導体部が形成される。絶縁基板は半田槽に浸漬され、露出した導体部に付着した半田により電子部品が半田付けされる。導体部はビア部を介して絶縁基板の両面で導通し、ビア部の周囲の導体部にはレジストとシルク印刷部が積層される。これにより、絶縁基板を半田槽に浸漬した際に半田ボールがレジストとシルク印刷部との積層部分で遮られ、ビア部の周囲の導体部への半田ボールの付着が防止される。   According to this configuration, the conductor portion that is covered with the resist and partially exposed is formed on the insulating substrate. The insulating substrate is immersed in the solder bath, and the electronic component is soldered by the solder attached to the exposed conductor portion. The conductor portion conducts on both surfaces of the insulating substrate through the via portion, and a resist and a silk print portion are laminated on the conductor portion around the via portion. As a result, when the insulating substrate is immersed in the solder bath, the solder balls are blocked by the laminated portion of the resist and the silk print portion, and the adhesion of the solder balls to the conductor portion around the via portion is prevented.

また本発明は、上記構成の回路基板において、前記ビア部に配される前記導体部の内縁が前記レジストまたは前記シルク印刷部で覆われることを特徴としている。   According to the present invention, in the circuit board configured as described above, an inner edge of the conductor portion disposed in the via portion is covered with the resist or the silk print portion.

また本発明は、上記構成の回路基板において、前記レジスト及び前記シルク印刷部を積層して一方の面のみ前記ビア部の周囲の前記導体部を覆ったことを特徴としている。この構成によると、絶縁基板に設けたビア部の周囲には一方の面にレジスト及びシルク印刷部が積層され、他方の面にはレジスト及びシルク印刷部が設けられずに開放される。   According to the present invention, in the circuit board configured as described above, the resist and the silk-printed portion are laminated so that only one surface covers the conductor portion around the via portion. According to this configuration, the resist and the silk print portion are stacked on one surface around the via portion provided on the insulating substrate, and the resist and the silk print portion are not provided on the other surface and are opened.

また本発明は、貫通孔を有する絶縁基板の両面に設けられた導体部の所定部分を露出してレジストで覆うレジスト形成工程と、前記レジスト上に印字するシルク印刷部を形成するシルク印刷工程と、前記導体部の一部を露出するマスクにより覆われた前記絶縁基板を半田槽に浸漬するフロー半田工程とを備えた回路基板の製造方法において、前記貫通孔は前記導体部を配して前記絶縁基板の両面の前記導体部を導通させたビア部を形成し、前記マスクにより露出する位置に配された前記ビア部の周囲に配される前記導体部を前記レジスト及び前記シルク印刷部を積層して覆ったことを特徴としている。   The present invention also includes a resist forming step of exposing a predetermined portion of the conductor portion provided on both surfaces of the insulating substrate having a through hole and covering with a resist, and a silk printing step of forming a silk printing portion to be printed on the resist. A circuit board manufacturing method comprising a flow soldering step of immersing the insulating substrate covered with a mask exposing a part of the conductor portion in a solder bath, wherein the through hole is provided with the conductor portion, A via portion is formed by electrically connecting the conductor portions on both sides of the insulating substrate, and the resist and the silk print portion are laminated on the conductor portion disposed around the via portion disposed at a position exposed by the mask. It is characterized by covering.

本発明によると、レジスト及びシルク印刷部を積層してビア部の周囲の導体部を覆ったので、絶縁基板を半田槽に浸漬した際に半田ボールがレジストとシルク印刷部との積層部分で遮られる。これにより、ビア部の周囲に配された導体部への半田ボールの付着が防止されるため、付着した半田ボールの脱落による回路基板の短絡を防止することができる。従って、回路基板の歩留りを向上することができる。   According to the present invention, since the resist and the silk printed portion are laminated to cover the conductor portion around the via portion, the solder ball is blocked by the laminated portion of the resist and the silk printed portion when the insulating substrate is immersed in the solder bath. It is done. As a result, the solder balls are prevented from adhering to the conductor portions arranged around the via portions, so that it is possible to prevent a short circuit of the circuit board due to the falling off of the adhered solder balls. Therefore, the yield of the circuit board can be improved.

本発明の第1実施形態の回路基板を示す側面断面図Side surface sectional drawing which shows the circuit board of 1st Embodiment of this invention. 本発明の第1実施形態の回路基板の導体部形成工程を示す側面断面図Side surface sectional drawing which shows the conductor part formation process of the circuit board of 1st Embodiment of this invention 本発明の第1実施形態の回路基板のレジスト形成工程を示す側面断面図Side surface sectional drawing which shows the resist formation process of the circuit board of 1st Embodiment of this invention 本発明の第1実施形態の回路基板のシルク印刷工程を示す側面断面図Side surface sectional drawing which shows the silk printing process of the circuit board of 1st Embodiment of this invention. 本発明の第1実施形態の回路基板のフロー半田工程を示す側面断面図Side surface sectional drawing which shows the flow soldering process of the circuit board of 1st Embodiment of this invention 本発明の第1実施形態の回路基板のレジスト及びシルク印刷部のパターンを示す側面断面図Side surface sectional drawing which shows the pattern of the resist of the circuit board of 1st Embodiment of this invention, and a silk printing part 本発明の第2実施形態の回路基板を示す側面断面図Side surface sectional drawing which shows the circuit board of 2nd Embodiment of this invention. 従来の回路基板を示す側面断面図Side sectional view showing a conventional circuit board

以下に本発明の実施形態を図面を参照して説明する。説明の便宜上、前述の図8に示す従来例と同一の部分は同一の符号を付している。図1は第1実施形態の回路基板を示す側面断面図である。回路基板1は絶縁基板2を貫通するビア部3、30が設けられる。絶縁基板2の両面には所定のパターンで形成される導体部4が形成される。導体部4はビア部3、30を通って絶縁基板2の両面で導通する。   Embodiments of the present invention will be described below with reference to the drawings. For convenience of explanation, the same parts as those in the conventional example shown in FIG. FIG. 1 is a side sectional view showing a circuit board according to the first embodiment. The circuit board 1 is provided with via portions 3 and 30 that penetrate the insulating substrate 2. Conductor portions 4 formed in a predetermined pattern are formed on both surfaces of the insulating substrate 2. The conductor portion 4 is electrically connected to both sides of the insulating substrate 2 through the via portions 3 and 30.

導体部4は所定位置を露出してレジスト5により覆われる。一部が露出した導体部4が形成された絶縁基板2は半田槽に浸漬される。これにより、絶縁基板2の一面に露出した導体部4に半田7が設けられ、ビア部30に挿通された電子部品8が半田付けされる。   The conductor portion 4 is exposed at a predetermined position and covered with a resist 5. The insulating substrate 2 on which the conductor part 4 that is partially exposed is formed is immersed in a solder bath. As a result, the solder 7 is provided on the conductor portion 4 exposed on one surface of the insulating substrate 2, and the electronic component 8 inserted through the via portion 30 is soldered.

また、電子部品8が挿通されないビア部3の一方の面には周囲の導体部4がレジスト5により覆われる。また、絶縁基板2のレジスト5上にはシルク印刷部6により所定の印字が設けられる。シルク印刷部6はビア部3の周囲の導体部4上に設けたレジスト5上に積層して設けられる。   In addition, the surrounding conductor portion 4 is covered with a resist 5 on one surface of the via portion 3 through which the electronic component 8 is not inserted. A predetermined printing is provided on the resist 5 of the insulating substrate 2 by the silk printing unit 6. The silk printing portion 6 is provided by being laminated on a resist 5 provided on the conductor portion 4 around the via portion 3.

図2〜図5は回路基板1の製造工程を示している。図2は絶縁基板2に導体部4を形成する導体部形成工程を示している。絶縁基板2には所定位置に貫通孔2aが形成されている。絶縁基板2の両面には銅箔等の金属膜が設けられ、フォトリソグラフィによって所定のパターンの導体部4が形成される。この時、貫通孔2aの内壁に金属膜が配されてビア部3、30を形成し、絶縁基板2の両面の導体部4がビア部3、30を介して導通する。   2 to 5 show the manufacturing process of the circuit board 1. FIG. 2 shows a conductor portion forming step for forming the conductor portion 4 on the insulating substrate 2. A through hole 2a is formed in the insulating substrate 2 at a predetermined position. A metal film such as a copper foil is provided on both surfaces of the insulating substrate 2, and a conductor portion 4 having a predetermined pattern is formed by photolithography. At this time, a metal film is disposed on the inner wall of the through hole 2 a to form the via portions 3 and 30, and the conductor portions 4 on both surfaces of the insulating substrate 2 are conducted through the via portions 3 and 30.

次に、図3は絶縁基板2上にレジスト5を形成するレジスト形成工程を示している。絶縁基板2の両面にはシート状や液状のレジスト5が配され、導体部4が覆われる。そして、フォトリソグラフィによって所望位置の導体部4が露出するようにレジスト5がパターニングされる。   Next, FIG. 3 shows a resist forming process for forming a resist 5 on the insulating substrate 2. Sheet-like or liquid resist 5 is disposed on both surfaces of the insulating substrate 2 to cover the conductor portion 4. Then, the resist 5 is patterned so that the conductor portion 4 at a desired position is exposed by photolithography.

次に、図4は絶縁基板2のレジスト5上に印字を行うシルク印刷工程を示している。レジスト5上にはシルク印刷によって所定位置にシルク印刷部6による印字が行われる。   Next, FIG. 4 shows a silk printing process for printing on the resist 5 of the insulating substrate 2. On the resist 5, printing by the silk printing unit 6 is performed at a predetermined position by silk printing.

レジスト5及びシルク印刷部6はビア部3の一方の面の周囲に配された導体部4を覆って積層されている。この時、図6に示すように、ビア部3に配される導体部4の内径D1(例えば0.35mm)に対して、レジスト5及びシルク印刷部6のパターンの内径D2が大きく形成される(例えば、0、5mm)。そして、流動するレジスト5及びシルク印刷部6によって図4に示すようにビア部3に配される導体部4の内縁がレジスト5またはシルク印刷部6で覆われる。導体部4の内径D1とレジスト5及びシルク印刷部6のパターンの内径D2とは、導体部4の内縁が覆われてビア部3を塞がない寸法に設定される。   The resist 5 and the silk print portion 6 are laminated so as to cover the conductor portion 4 disposed around one surface of the via portion 3. At this time, as shown in FIG. 6, the inner diameter D2 of the pattern of the resist 5 and the silk print portion 6 is formed larger than the inner diameter D1 (for example, 0.35 mm) of the conductor portion 4 disposed in the via portion 3. (For example, 0, 5 mm). Then, the inner edge of the conductor part 4 disposed in the via part 3 is covered with the resist 5 or the silk printing part 6 as shown in FIG. The inner diameter D1 of the conductor part 4 and the inner diameter D2 of the pattern of the resist 5 and the silk print part 6 are set to dimensions that do not block the via part 3 by covering the inner edge of the conductor part 4.

次に、図5は導体部4に半田7を形成するフロー半田工程を示している。レジスト5及びシルク印刷部6が形成された絶縁基板2は電子部品8(図1参照)が挿入されるビア部30を露出する開口部10aを有したマスク10により両面が覆われる。マスク10を配した絶縁基板2は半田槽に浸漬され、ビア部30の周囲の導体部4上に半田7が設けられる。そして、ビア部30に電子部品8が実装され、図1に示す回路基板1が得られる。   Next, FIG. 5 shows a flow soldering process for forming the solder 7 on the conductor portion 4. The insulating substrate 2 on which the resist 5 and the silk print portion 6 are formed is covered on both sides by a mask 10 having an opening 10a that exposes a via portion 30 into which an electronic component 8 (see FIG. 1) is inserted. The insulating substrate 2 provided with the mask 10 is immersed in a solder bath, and solder 7 is provided on the conductor portion 4 around the via portion 30. And the electronic component 8 is mounted in the via | veer part 30, and the circuit board 1 shown in FIG. 1 is obtained.

フロー半田工程でビア部30近傍に配されたビア部3は電子部品8が設けられないが、開口部10aから露出して半田槽中の半田と接触する。しかし、ビア部3の周囲の導体部4上にはレジスト5及びシルク印刷部6が積層して形成される。このため、図1に示すように、半田槽から取り出した絶縁基板2はレジスト5及びシルク印刷部6により球状の半田ボールBが遮られて導体部4との接触が防止される。   The via part 3 arranged in the vicinity of the via part 30 in the flow soldering process is not provided with the electronic component 8, but is exposed from the opening 10a and contacts the solder in the solder bath. However, the resist 5 and the silk print portion 6 are laminated on the conductor portion 4 around the via portion 3. For this reason, as shown in FIG. 1, the insulating substrate 2 taken out from the solder bath is blocked from the spherical solder ball B by the resist 5 and the silk printing portion 6, thereby preventing contact with the conductor portion 4.

尚、チップ状の電子部品を半田付けするリフロー半田工程を設けてもよい。リフロー半田工程ではマスク10が配された部分の所定位置の導体部4にクリーム半田(不図示)が塗布される。そして、クリーム半田上にチップ状の電子部品を設置した絶縁基板2を恒温槽に配して電子部品が半田付けされる。   A reflow soldering process for soldering chip-shaped electronic components may be provided. In the reflow soldering process, cream solder (not shown) is applied to the conductor portion 4 at a predetermined position in the portion where the mask 10 is disposed. Then, the insulating substrate 2 in which chip-shaped electronic components are placed on the cream solder is placed in a thermostatic bath, and the electronic components are soldered.

本実施形態によると、レジスト5及びシルク印刷部6を積層してビア部3の周囲の導体部4を覆ったので、絶縁基板2を半田槽に浸漬して取り出した際に半田ボールBがレジスト5とシルク印刷部6との積層部分で遮られる。これにより、ビア部3の周囲に配された導体部4への半田ボールBの付着が防止されるため、付着した半田ボールBの脱落による回路基板1の短絡を防止することができる。従って、回路基板1の歩留りを向上することができる。   According to the present embodiment, since the resist 5 and the silk printed portion 6 are stacked and the conductor portion 4 around the via portion 3 is covered, the solder ball B is resisted when the insulating substrate 2 is dipped in the solder bath and taken out. 5 and the silk printing portion 6 are blocked. Accordingly, the solder ball B is prevented from adhering to the conductor portion 4 disposed around the via portion 3, so that the circuit board 1 can be prevented from being short-circuited due to the drop of the adhered solder ball B. Therefore, the yield of the circuit board 1 can be improved.

また、ビア部3に配される導体部4の内縁がレジスト5またはシルク印刷部6で覆われるので、ビア部3の周囲に配される導体部4の露出を防止し、半田ボールBの付着をより確実に防止することができる。   Further, since the inner edge of the conductor portion 4 disposed in the via portion 3 is covered with the resist 5 or the silk printing portion 6, the exposure of the conductor portion 4 disposed around the via portion 3 is prevented, and the solder ball B is attached. Can be prevented more reliably.

また、製造時の公差によって導体部4の内縁からレジスト5またはシルク印刷部6がはみ出てビア部3が塞がれる場合がある。この時、レジスト5及びシルク印刷部6を積層して一方の面のみビア部3の周囲の導体部4を覆っているので、ビア部3は他方の面が開放される。このため、リフロー半田工程を有して絶縁基板2を恒温槽に配した際にビア部3内の空気が開放面から抜けるため、空気の膨張による絶縁基板2のクラック等の発生を防止することができる。   Further, the resist 5 or the silk print portion 6 may protrude from the inner edge of the conductor portion 4 due to tolerance at the time of manufacture, and the via portion 3 may be blocked. At this time, since the resist 5 and the silk printed portion 6 are laminated and only one surface covers the conductor portion 4 around the via portion 3, the other surface of the via portion 3 is opened. For this reason, when the insulating substrate 2 is arranged in a thermostat with a reflow soldering process, the air in the via portion 3 escapes from the open surface, thereby preventing the occurrence of cracks in the insulating substrate 2 due to the expansion of air. Can do.

次に、図7は第2実施形態の回路基板を示す側面断面図である。説明の便宜上、前述の図1〜図6に示す第1実施形態と同一の部分は同一の符号を付している。本実施形態はビア部3の周囲のレジスト5及びシルク印刷部6の配置が第1実施形態と異なっている。その他の部分は第1実施形態と同一である。   Next, FIG. 7 is a side sectional view showing a circuit board according to the second embodiment. For convenience of explanation, the same parts as those in the first embodiment shown in FIGS. The present embodiment is different from the first embodiment in the arrangement of the resist 5 and the silk printing portion 6 around the via portion 3. Other parts are the same as those of the first embodiment.

ビア部3の周囲のレジスト5及びシルク印刷部6のパターンの内径D2は第1実施形態よりも大きく、例えば、0、55mmで形成される。これにより、ビア部3に配される導体部4の内縁が若干露出する。ビア部3の周囲の導体部4上にはレジスト5及びシルク印刷部6が積層されるため、半田槽から取り出した絶縁基板2はレジスト5及びシルク印刷部6により球状の半田ボールBが遮られる。   The inner diameter D2 of the pattern of the resist 5 and the silk printing portion 6 around the via portion 3 is larger than that of the first embodiment, and is formed at, for example, 0, 55 mm. Thereby, the inner edge of the conductor part 4 distribute | arranged to the via part 3 is exposed a little. Since the resist 5 and the silk printing part 6 are laminated on the conductor part 4 around the via part 3, the spherical solder ball B is blocked by the resist 5 and the silk printing part 6 in the insulating substrate 2 taken out from the solder bath. .

本実施形態によると、第1実施形態と同様に、レジスト5及びシルク印刷部6を積層してビア部3の周囲の導体部4を覆ったので、絶縁基板2を半田槽に浸漬した際に半田ボールBがレジスト5とシルク印刷部6との積層部分で遮られる。これにより、ビア部3の周囲に露出した導体部4への半田ボールBの付着が防止されるため、付着した半田ボールBの脱落による回路基板1の短絡を防止することができる。従って、回路基板1の歩留りを向上することができる。   According to the present embodiment, as in the first embodiment, since the resist 5 and the silk print portion 6 are stacked and the conductor portion 4 around the via portion 3 is covered, the insulating substrate 2 is immersed in the solder bath. The solder ball B is blocked by the laminated portion of the resist 5 and the silk printing portion 6. Accordingly, the solder ball B is prevented from adhering to the conductor portion 4 exposed around the via portion 3, so that the circuit board 1 can be prevented from being short-circuited due to the dropped solder ball B. Therefore, the yield of the circuit board 1 can be improved.

尚、ビア部3に配される導体部4の内縁が露出するが、積層されたレジスト5及びシルク印刷部6によって導体部4の表面とシルク印刷部6の表面との距離が離れる。これにより、半田ボールBの付着を防止することができる。また、レジスト5及びシルク印刷6によるビア部3の閉塞を防止することができる。   In addition, although the inner edge of the conductor part 4 distribute | arranged to the via part 3 is exposed, the distance of the surface of the conductor part 4 and the surface of the silk printing part 6 leaves | separates by the resist 5 and the silk printing part 6 which were laminated | stacked. Thereby, adhesion of the solder ball B can be prevented. Moreover, blockage of the via part 3 due to the resist 5 and the silk printing 6 can be prevented.

本発明によると、絶縁基板を貫通するビア部を有した回路基板に利用することができる。   The present invention can be used for a circuit board having a via portion penetrating an insulating substrate.

1 回路基板
2 絶縁基板
3、30 ビア部
4 導体部
5 レジスト
6 シルク印刷部
7 半田
8 電子部品
10 マスク
B 半田ボール
DESCRIPTION OF SYMBOLS 1 Circuit board 2 Insulation board 3, 30 Via part 4 Conductor part 5 Resist 6 Silk printing part 7 Solder 8 Electronic component 10 Mask B Solder ball

Claims (4)

絶縁基板と、前記絶縁基板の両面に所定のパターンで形成されるとともに前記絶縁基板を貫通するビア部を通って前記絶縁基板の両面で導通する導体部と、前記導体部の所定部分を露出して前記導体部を覆うレジストと、前記レジスト上に印字するシルク印刷部とを備えた回路基板において、前記レジスト及び前記シルク印刷部を積層して前記ビア部の周囲の前記導体部を覆ったことを特徴とする回路基板。   An insulating substrate, a conductor portion formed in a predetermined pattern on both surfaces of the insulating substrate and conducting on both surfaces of the insulating substrate through a via portion penetrating the insulating substrate, and a predetermined portion of the conductor portion are exposed. In a circuit board comprising a resist covering the conductor part and a silk printed part printed on the resist, the resist and the silk printed part are laminated to cover the conductor part around the via part. A circuit board characterized by. 前記ビア部に配される前記導体部の内縁が前記レジストまたは前記シルク印刷部で覆われることを特徴とする請求項1に記載の回路基板。   The circuit board according to claim 1, wherein an inner edge of the conductor portion disposed in the via portion is covered with the resist or the silk print portion. 前記レジスト及び前記シルク印刷部を積層して一方の面のみ前記ビア部の周囲の前記導体部を覆ったことを特徴とする請求項2に記載の回路基板。   The circuit board according to claim 2, wherein the resist and the silk print portion are laminated to cover the conductor portion around the via portion on only one surface. 貫通孔を有する絶縁基板の両面に設けられた導体部の所定部分を露出してレジストで覆うレジスト形成工程と、前記レジスト上に印字するシルク印刷部を形成するシルク印刷工程と、前記導体部の一部を露出するマスクにより覆われた前記絶縁基板を半田槽に浸漬するフロー半田工程とを備えた回路基板の製造方法において、前記貫通孔は前記導体部を配して前記絶縁基板の両面の前記導体部を導通させたビア部を形成し、前記マスクにより露出する位置に配された前記ビア部の周囲に配される前記導体部を前記レジスト及び前記シルク印刷部を積層して覆ったことを特徴とする回路基板の製造方法。   A resist forming step of exposing a predetermined portion of the conductor portion provided on both surfaces of the insulating substrate having a through hole and covering with a resist; a silk printing step of forming a silk print portion to be printed on the resist; and And a flow soldering step of immersing the insulating substrate covered with a partly exposed mask in a solder bath, wherein the through-holes are disposed on both sides of the insulating substrate with the conductor portion disposed therebetween. Forming a via portion that conducts the conductor portion, and covering the conductor portion disposed around the via portion disposed at a position exposed by the mask by laminating the resist and the silk printing portion. A method of manufacturing a circuit board characterized by the above.
JP2009059412A 2009-03-12 2009-03-12 Circuit board and method for manufacturing the same Pending JP2010212592A (en)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878819A (en) * 1994-09-05 1996-03-22 Matsushita Electric Ind Co Ltd Printed wiring board and manufacture thereof
JP2000312074A (en) * 1999-04-27 2000-11-07 Nippon Seiki Co Ltd Printed board

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878819A (en) * 1994-09-05 1996-03-22 Matsushita Electric Ind Co Ltd Printed wiring board and manufacture thereof
JP2000312074A (en) * 1999-04-27 2000-11-07 Nippon Seiki Co Ltd Printed board

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