JP2006179809A - Electronic circuit unit - Google Patents

Electronic circuit unit Download PDF

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JP2006179809A
JP2006179809A JP2004373617A JP2004373617A JP2006179809A JP 2006179809 A JP2006179809 A JP 2006179809A JP 2004373617 A JP2004373617 A JP 2004373617A JP 2004373617 A JP2004373617 A JP 2004373617A JP 2006179809 A JP2006179809 A JP 2006179809A
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copper foil
wiring pattern
circuit unit
electronic circuit
width dimension
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Hiroya Ouchi
博也 大内
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Priority to JP2004373617A priority Critical patent/JP2006179809A/en
Priority to CN 200510138109 priority patent/CN1794901A/en
Publication of JP2006179809A publication Critical patent/JP2006179809A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide an electric circuit unit that prevents wiring patterns from being peeled off. <P>SOLUTION: This electronic circuit unit is composed of paper phenol resins or paper epoxide resins. The unit is provided with an insulated substrate 1 with a board thickness of 0.8 mm or more, a wiring pattern 2 made of copper films, and electronic components 9a and 9b soldered by a lead-free solder. The wiring pattern 2 has a copper film removal part 8 at any location where the widths B1 and B2 of a signal line 3 and an earth pattern 4 exceed 2 mm respectively, and keeps the width to be 2 mm or below between the outer edge 2a and the copper removal part 8 in the signal line 3 and earth pattern 4. Consequently, air bubble generated for moisture evaporation within the insulated substrate 1 at soldering with the lead-free solder is exhausted via the copper film removal 8, and the peel-off of the wiring pattern 2 can be prevented. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

本発明はＦＭチューナ等に使用して好適な電子回路ユニットに関する。   The present invention relates to an electronic circuit unit suitable for use in an FM tuner or the like.

図４は従来の電子回路ユニットに係る要部の平面図であり、この図４に基づいて従来の電子回路ユニットの構成を説明すると、絶縁基板５１の表面には、配線パターン５２が設けられ、この配線パターン５２は、信号ライン５３と、アースパターン５４と、信号ライン５３の一端に設けられたランド部５５ａと、アースパターン５４に設けられたランド部５５ｂとで形成されている。   FIG. 4 is a plan view of a main part of a conventional electronic circuit unit. The configuration of the conventional electronic circuit unit will be described with reference to FIG. 4. A wiring pattern 52 is provided on the surface of the insulating substrate 51. The wiring pattern 52 is formed of a signal line 53, a ground pattern 54, a land portion 55 a provided at one end of the signal line 53, and a land portion 55 b provided in the ground pattern 54.

また、アースパターン５４のランド部５５ｂの外周近傍には、メッシュ状の導電路除去部５４ａが設けられると共に、ランド部５５ａ、５５ｂ間には、電子部品５６が半田付けされて、従来の電子回路ユニットが形成されると共に、メッシュ状の導電路除去部５４ａの存在によって、半田付けする際の熱応力によって導電路に亀裂が生じた場合でも、導電路が確保できるようにしたものである。（例えば、特許文献１参照）   Further, a mesh-like conductive path removing portion 54a is provided in the vicinity of the outer periphery of the land portion 55b of the ground pattern 54, and an electronic component 56 is soldered between the land portions 55a and 55b, so that a conventional electronic circuit is provided. The unit is formed, and the presence of the mesh-like conductive path removing portion 54a allows the conductive path to be secured even when the conductive path is cracked due to thermal stress during soldering. (For example, see Patent Document 1)

しかし、このような構成を有する従来の電子回路ユニットは、一般に、絶縁基板５１が紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚が０．８ｍｍ以上の厚みを有し、配線パターン５２の信号ライン５３、アースパターン５４、及びランド部５５ａ、５５ｂの幅寸法Ｂが２ｍｍを越えた幅を有し、この状態で、溶融温度の高い鉛フリー半田によって電子部品５６が配線パターン５２に半田付けされるが、この半田付の際、絶縁基板５１内の水分が気化して気泡が発生し、絶縁基板５１から配線パターン５２の一部が剥がれる。   However, in the conventional electronic circuit unit having such a configuration, generally, the insulating substrate 51 is made of paper phenol resin or paper epoxy resin, has a thickness of 0.8 mm or more, and the signal of the wiring pattern 52 The width 53 of the line 53, the ground pattern 54, and the land portions 55a and 55b has a width exceeding 2 mm. In this state, the electronic component 56 is soldered to the wiring pattern 52 by lead-free solder having a high melting temperature. However, during the soldering, moisture in the insulating substrate 51 is vaporized to generate bubbles, and a part of the wiring pattern 52 is peeled off from the insulating substrate 51.

実開昭６１−４６７６６号公報Japanese Utility Model Publication No. 61-46766

従来の電子回路ユニットは、一般に、絶縁基板５１が紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚が０．８ｍｍ以上の厚みを有し、配線パターン５２の信号ライン５３、アースパターン５４、及びランド部５５ａ、５５ｂの幅寸法が２ｍｍを越えた幅を有し、この状態で、溶融温度の高い鉛フリー半田によって電子部品５６が配線パターン５２に半田付けされるが、この半田付の際、絶縁基板５１内の水分が気化して気泡が発生し、絶縁基板５１から配線パターン５２の一部が剥がれるという問題がある。   In the conventional electronic circuit unit, generally, the insulating substrate 51 is made of paper phenol resin or paper epoxy resin, and has a thickness of 0.8 mm or more. The signal line 53 of the wiring pattern 52, the ground pattern 54, and The width dimension of the land portions 55a and 55b has a width exceeding 2 mm, and in this state, the electronic component 56 is soldered to the wiring pattern 52 by lead-free solder having a high melting temperature. There is a problem that moisture in the insulating substrate 51 is vaporized to generate bubbles, and a part of the wiring pattern 52 is peeled off from the insulating substrate 51.

そこで、本発明は配線パターンの剥がれの無い電子回路ユニットを提供することを目的とする。   SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an electronic circuit unit in which a wiring pattern does not peel off.

上記課題を解決するための第１の解決手段として、紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚が０．８ｍｍ以上の厚みを有する絶縁基板と、この絶縁基板の表面に設けられた銅箔からなる配線パターンと、この配線パターン上に鉛フリー半田によって半田付けされた電子部品とを備え、前記配線パターンは、信号ラインとアースパターンを有し、前記信号ラインと前記アースパターンのそれぞれの幅寸法が２ｍｍを越える箇所にあっては、前記配線パターンを形成する前記銅箔が除去された銅箔除去部を有し、前記信号ライン、及び前記アースパターンの外側縁と前記銅箔除去部との間の幅寸法を２ｍｍ以下にすると共に、前記銅箔除去部間の幅寸法を２ｍｍ以下にした構成とした。   As a first means for solving the above problems, an insulating substrate made of paper phenol resin or paper epoxy resin and having a thickness of 0.8 mm or more, and copper provided on the surface of the insulating substrate A wiring pattern made of foil and an electronic component soldered onto the wiring pattern by lead-free solder, the wiring pattern having a signal line and a ground pattern, each of the signal line and the ground pattern In a place where the width dimension exceeds 2 mm, it has a copper foil removing portion from which the copper foil forming the wiring pattern is removed, and the signal line, the outer edge of the ground pattern and the copper foil removing portion And the width dimension between the copper foil removal portions is 2 mm or less.

また、第２の解決手段として、前記配線パターンは、前記電子部品を半田付けするためのランド部有し、前記ランド部の幅寸法が２ｍｍを越える箇所にあっては、前記銅箔除去部が設けられて、前記ランド部の外側縁と前記銅箔除去部との間の幅寸法を２ｍｍ以下にした構成とした。   As a second solving means, the wiring pattern has a land portion for soldering the electronic component, and the copper foil removing portion is provided at a location where the width dimension of the land portion exceeds 2 mm. The width dimension between the outer edge of the land portion and the copper foil removing portion is 2 mm or less.

また、第３の解決手段として、前記鉛フリー半田は、錫、銀、銅を主成分とした構成とした。
また、第４の解決手段として、前記銅箔除去部は、孔、又は／及び切り欠き部によって形成された構成とした。
また、第５の解決手段として、前記孔からなる前記銅箔除去部は、同じ大きさで、規則的に点在して形成された構成とした。 Further, as a third solution, the lead-free solder is composed mainly of tin, silver, and copper.
Further, as a fourth solution, the copper foil removing part is formed by a hole or / and a notch part.
Further, as a fifth solving means, the copper foil removing portions made of the holes have the same size and are regularly scattered.

本発明の電子回路ユニットは、紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚が０．８ｍｍ以上の厚みを有する絶縁基板と、この絶縁基板の表面に設けられた銅箔からなる配線パターンと、この配線パターン上に鉛フリー半田によって半田付けされた電子部品とを備え、配線パターンは、信号ラインとアースパターンを有し、信号ラインとアースパターンのそれぞれの幅寸法が２ｍｍを越える箇所にあっては、配線パターンを形成する銅箔が除去された銅箔除去部を有し、信号ライン、及びアースパターンの外側縁と銅箔除去部との間の幅寸法を２ｍｍ以下にすると共に、銅箔除去部間の幅寸法を２ｍｍ以下にしたため、絶縁基板が安価にできると共に、溶融温度の高い鉛フリー半田による半田付け時、絶縁基板内の水分が気化して気泡が発生しても、気泡が銅箔除去部から抜けるようになって、絶縁基板からの配線パターンの剥がれを無くすることができる。   The electronic circuit unit of the present invention is made of paper phenolic resin or paper epoxy resin, an insulating substrate having a thickness of 0.8 mm or more, and a wiring pattern made of copper foil provided on the surface of the insulating substrate. And an electronic component soldered with lead-free solder on the wiring pattern. The wiring pattern has a signal line and a ground pattern, and each of the signal line and the ground pattern has a width dimension exceeding 2 mm. The copper foil removing portion from which the copper foil forming the wiring pattern is removed has a width dimension between the outer edge of the signal line and the ground pattern and the copper foil removing portion of 2 mm or less, and copper. Since the width between the foil removal parts is 2 mm or less, the insulating substrate can be made inexpensive, and moisture in the insulating substrate is vaporized when soldering with lead-free solder having a high melting temperature. Even bubbles are generated bubbles so escape from the copper foil removed portion, it can be eliminated peeling of the wiring pattern of the insulating substrate.

また、配線パターンは、電子部品を半田付けするためのランド部有し、ランド部の幅寸法が２ｍｍを越える箇所にあっては、銅箔除去部が設けられて、ランド部の外側縁と銅箔除去部との間の幅寸法を２ｍｍ以下にしたため、溶融温度の高い鉛フリー半田による半田付け時、絶縁基板内の水分が気化して気泡が発生しても、気泡が銅箔除去部から抜けるようになって、絶縁基板からのランド部の剥がれを無くすることができ、電子部品の確実な半田付ができる。   In addition, the wiring pattern has a land portion for soldering the electronic component. When the land portion has a width dimension exceeding 2 mm, a copper foil removing portion is provided so that the outer edge of the land portion and the copper Since the width between the foil removal part is 2 mm or less, even when soldering with lead-free solder having a high melting temperature, moisture in the insulating substrate is vaporized and bubbles are generated, the bubbles are removed from the copper foil removal part. As a result, the peeling of the land portion from the insulating substrate can be eliminated, and the electronic component can be reliably soldered.

また、鉛フリー半田は、錫、銀、銅を主成分としたため、この鉛フリ−半田の溶融温度は、２６０度と高く、絶縁基板内の水分が気化して気泡を発生するような溶融温度の高い鉛フリ−半田を使用した場合に、特に有効となる。   In addition, since lead-free solder is mainly composed of tin, silver, and copper, the melting temperature of this lead-free solder is as high as 260 degrees, and the melting temperature at which moisture in the insulating substrate evaporates to generate bubbles. This is particularly effective when high lead-free solder is used.

また、銅箔除去部は、孔、又は／及び切り欠き部によって形成されたため、その構成が簡単で、生産性の良いものが得られる。   Moreover, since the copper foil removal part was formed by the hole or / and the notch part, the structure is simple and a product with good productivity is obtained.

また、孔からなる銅箔除去部は、同じ大きさで、規則的に点在して形成されたため、その構成が簡単で、生産性の良いものが得られる。   Moreover, since the copper foil removal part which consists of a hole is the same magnitude | size and was regularly scattered and formed, the structure is simple and productivity is good.

本発明の電子回路ユニットの図面を説明すると、図１は本発明の電子回路ユニットに係る要部断面図、図２は本発明の電子回路ユニットに係り、カバーを取り除いた状態を示す平面図、図３は本発明の電子回路ユニットに係る絶縁基板の平面図である。   FIG. 1 is a cross-sectional view of an essential part of an electronic circuit unit according to the present invention. FIG. 2 is a plan view showing a state in which a cover is removed according to the electronic circuit unit of the present invention. FIG. 3 is a plan view of an insulating substrate according to the electronic circuit unit of the present invention.

次に、本発明の電子回路ユニットの構成を図１〜図３に基づいて説明すると、絶縁基板１は、紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚Ｔが０．８ｍｍ以上の厚みを有したもので形成されており、絶縁基板１には、多数の貫通孔１ａが設けられている。   Next, the configuration of the electronic circuit unit of the present invention will be described with reference to FIGS. 1 to 3. The insulating substrate 1 is made of paper phenol resin or paper epoxy resin, and the thickness T is 0.8 mm or more. The insulating substrate 1 is provided with a large number of through holes 1a.

また、絶縁基板１の表面には、銅箔からなる配線パターン２が設けられ、この配線パターン２は、信号ライン３と、アースパターン４と、信号ライン３の端部側で、貫通孔１ａの周りに設けられた環状のランド部５と、信号ライン３の端部側で、貫通孔１ａの無い位置に設けられたランド部６と、アースパターン４に設けられたランド部７とで形成されている。   Further, a wiring pattern 2 made of copper foil is provided on the surface of the insulating substrate 1, and this wiring pattern 2 is connected to the signal line 3, the ground pattern 4, and the end of the signal line 3 with the through hole 1 a. It is formed by an annular land portion 5 provided around, a land portion 6 provided at a position without the through hole 1a on the end side of the signal line 3, and a land portion 7 provided in the earth pattern 4. ing.

そして、信号ライン３の幅寸法Ｂ１、アースパターン４の幅寸法Ｂ２、及びランド部５，６，７の幅寸法Ｂ３が２ｍｍを越える箇所にあっては、信号ライン３、アースパターン４、及びランド部５，６，７に銅箔除去部８が設けられ、信号ライン３、アースパターン４、及びランド部５，６，７のそれぞれの幅寸法が２ｍｍ以下になるように形成されている。   If the width dimension B1 of the signal line 3, the width dimension B2 of the ground pattern 4, and the width dimension B3 of the land portions 5, 6, and 7 exceed 2 mm, the signal line 3, the ground pattern 4, and the land Copper foil removing portions 8 are provided in the portions 5, 6, and 7, and the signal line 3, the ground pattern 4, and the land portions 5, 6, and 7 are formed to have a width dimension of 2 mm or less.

即ち、銅箔除去部８は、丸型孔や角形孔からなる孔、或いは切り欠き部によって形成され、信号ライン３、アースパターン４、及びランド部５，６，７における配線パターン２の外側縁２ａと銅箔除去部８との間の幅寸法Ｄ１が２ｍｍ以下にすると共に、銅箔除去部８間における幅寸法Ｄ２を２ｍｍ以下にして、信号ライン３、アースパターン４、及びランド部５，６，７における各箇所の銅箔の幅寸法を２ｍｍ以下にすることによって、絶縁基板１内の水分が気化して発生する気泡の抜けを容易にしている。   That is, the copper foil removing portion 8 is formed by a hole formed by a round hole or a square hole, or a notch, and the outer edge of the wiring pattern 2 in the signal line 3, the ground pattern 4, and the land portions 5, 6, 7. The width dimension D1 between 2a and the copper foil removal part 8 is 2 mm or less, and the width dimension D2 between the copper foil removal parts 8 is 2 mm or less, so that the signal line 3, the ground pattern 4, and the land part 5, By making the width dimension of the copper foil of each place in 6 and 7 into 2 mm or less, the bubble in the insulating substrate 1 is easily removed due to vaporization of moisture.

なお、この実施例では、孔からなる銅箔除去部８が同じ孔の大きさで、規則的に点在したものとなっているが、異なる大きさや不規則な状態で点在させても良い。   In this embodiment, the copper foil removing portions 8 made of holes have the same hole size and are regularly scattered, but may be scattered in different sizes and irregular states. .

コンデンサや抵抗器等からなり、リード線を有した電子部品９ａやチップ型の電子部品９ｂを有し、リード線を電子部品９ａは、リード線が絶縁基板１の貫通孔１ａに挿通された状態で、ランド部５，７に鉛フリー半田（図示せず）によって半田付けされると共に、チップ型の電子部品９ｂは、ランド部６に鉛フリー半田によって半田付けされて、所望の電気回路が形成されている。   It is composed of a capacitor, a resistor, etc., and has an electronic component 9a having a lead wire and a chip-type electronic component 9b. The lead wire is an electronic component 9a, and the lead wire is inserted into the through hole 1a of the insulating substrate 1. The land portions 5 and 7 are soldered with lead-free solder (not shown), and the chip-type electronic component 9b is soldered to the land portion 6 with lead-free solder to form a desired electric circuit. Has been.

また、電子部品９ａ、９ｂを半田付けするための鉛フリー半田は、錫、銀、銅を主成分として構成され、この鉛フリ−半田の溶融温度は、２６０度と高く、絶縁基板１内の水分が気化して気泡を発生するような溶融温度となっている。   The lead-free solder for soldering the electronic components 9a and 9b is mainly composed of tin, silver, and copper, and the melting temperature of the lead-free solder is as high as 260 degrees. The melting temperature is such that moisture evaporates and bubbles are generated.

金属板からなる箱形のカバー１０は、電子部品９ａ、９ｂを覆った状態で、絶縁基板１に取り付けられ、このカバー１０によって、電気的なシールド行うようになっており、カバー１０は、配線パターン２に半田付けされる等の適宜手段によって、絶縁基板１に取り付けられて、本発明の電子回路ユニットが形成されている。   A box-shaped cover 10 made of a metal plate is attached to the insulating substrate 1 so as to cover the electronic components 9a and 9b, and is electrically shielded by the cover 10. The electronic circuit unit of the present invention is formed by being attached to the insulating substrate 1 by appropriate means such as soldering to the pattern 2.

このような電子回路ユニットにおける電子部品９ａ、９ｂの半田付は、先ず、鉛フリーからなるクリーム半田がランド部５，６，７に塗布された後、電子部品９ａ、９ｂがランド部５，６，７に載置、或いは挿通され、しかる後、リフロー炉内に搬送されて、絶縁基板１やクリーム半田等が加熱され、そして、クリーム半田が溶融され、これによって、電子部品９ａ、９ｂがランド部５，６，７に半田付されるようになっている。   Soldering of the electronic components 9a, 9b in such an electronic circuit unit is performed by first applying a lead-free cream solder to the land portions 5, 6, 7 and then the electronic components 9a, 9b to the land portions 5, 6 , 7 is inserted into or inserted into the reflow furnace, and the insulating substrate 1 or cream solder is heated, and the cream solder is melted, whereby the electronic components 9a and 9b are landed. The parts 5, 6 and 7 are soldered.

そして、配線パターン２への電子部品９ａ、９ｂの半田付工程を種々実験した結果、紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚Ｔが０．８ｍｍ未満の厚みを有した絶縁基板１を使用し、配線パターン２の信号ライン３の幅寸法Ｂ１、アースパターン４の幅寸法Ｂ２、及びランド部５，６，７の幅寸法Ｂ３が２ｍｍを越えた箇所を有した状態で、溶融温度の高い鉛フリ−半田によって半田付を行った場合は、絶縁基板１内の水分が気化して発生した気泡が配線パターン２の存在しない絶縁基板１の裏面側から抜け出て、配線パターン２が剥がれ無いことが判明した。   As a result of various experiments on the soldering process of the electronic components 9a and 9b to the wiring pattern 2, the insulating substrate 1 made of paper phenol resin or paper epoxy resin and having a thickness T of less than 0.8 mm is obtained. In a state where the width dimension B1 of the signal line 3 of the wiring pattern 2, the width dimension B2 of the ground pattern 4, and the width dimension B3 of the land portions 5, 6, and 7 have a portion exceeding 2 mm, When soldering is performed with high lead-free solder, bubbles generated by evaporation of moisture in the insulating substrate 1 escape from the back side of the insulating substrate 1 where the wiring pattern 2 does not exist, and the wiring pattern 2 does not peel off. It has been found.

また、紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚Ｔが０．８ｍｍ以上の厚みを有した絶縁基板１を使用し、配線パターン２の信号ライン３の幅寸法Ｂ１、アースパターン４の幅寸法Ｂ２、及びランド部５，６，７の幅寸法Ｂ３が２ｍｍを越えた箇所を有した状態で、溶融温度の高い鉛フリ−半田によって半田付を行った場合は、絶縁基板１内の水分が気化して発生した気泡によって、配線パターン２が絶縁基板１から剥がれることが判明した。   Further, the insulating substrate 1 made of paper phenol resin or paper epoxy resin and having a thickness T of 0.8 mm or more is used, the width B1 of the signal line 3 of the wiring pattern 2, and the width of the ground pattern 4 When soldering is performed with lead-free solder having a high melting temperature in a state where the dimension B2 and the width dimension B3 of the land portions 5, 6, and 7 exceed 2 mm, moisture in the insulating substrate 1 It was found that the wiring pattern 2 was peeled off from the insulating substrate 1 due to bubbles generated by vaporization.

そこで、種々実験した結果、本発明のように、紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚Ｔが０．８ｍｍ以上の厚みを有した絶縁基板１を使用し、配線パターン２の信号ライン３の幅寸法Ｂ１、アースパターン４の幅寸法Ｂ２、及びランド部５，６，７の幅寸法Ｂ３が２ｍｍを越えた箇所では、銅箔除去部８を設けた状態で、溶融温度の高い鉛フリ−半田によって半田付を行った場合は、絶縁基板１内の水分が気化して発生した気泡が銅箔除去部８から抜け出て、配線パターン２が剥がれ無いことが判明した。   Therefore, as a result of various experiments, as in the present invention, the signal line of the wiring pattern 2 is formed by using the insulating substrate 1 made of paper phenol resin or paper epoxy resin and having a thickness T of 0.8 mm or more. 3 where the width dimension B1 of the ground pattern 4, the width dimension B2 of the ground pattern 4 and the width dimension B3 of the land portions 5, 6 and 7 exceed 2 mm, lead having a high melting temperature with the copper foil removal portion 8 provided. When soldering was performed using free solder, it was found that bubbles generated by evaporation of moisture in the insulating substrate 1 escaped from the copper foil removing portion 8 and the wiring pattern 2 was not peeled off.

本発明の電子回路ユニットに係る要部断面図。Sectional drawing of the principal part which concerns on the electronic circuit unit of this invention. 本発明の電子回路ユニットに係り、カバーを取り除いた状態を示す平面図。The top view which concerns on the electronic circuit unit of this invention, and shows the state which removed the cover. 本発明の電子回路ユニットに係る絶縁基板の平面図。The top view of the insulated substrate which concerns on the electronic circuit unit of this invention. 従来の電子回路ユニットに係る要部の平面図。The top view of the principal part which concerns on the conventional electronic circuit unit.

符号の説明Explanation of symbols

１：絶縁基板
１ａ：貫通孔
２：配線パターン
２ａ：外側縁
３：信号ライン
４：アースパターン
５、６，７：ランド部
８：銅箔除去部
９ａ、９ｂ：電子部品
１０：カバー
Ｔ：板厚
Ｂ１：信号ラインの幅寸法
Ｂ２：アースパターンの幅寸法
Ｂ３：ランド部の幅寸法
Ｄ１：外側縁と銅箔除去部との間の幅寸法
Ｄ２：銅箔除去部間の幅寸法
1: Insulating substrate 1a: Through hole 2: Wiring pattern 2a: Outer edge 3: Signal line 4: Ground pattern 5, 6, 7: Land portion 8: Copper foil removing portion 9a, 9b: Electronic component 10: Cover T: Board Thickness B1: Width dimension of signal line B2: Width dimension of ground pattern B3: Width dimension of land part D1: Width dimension between outer edge and copper foil removal part D2: Width dimension between copper foil removal part

Claims (5)

紙フェノール樹脂、或いは紙エポキシ樹脂からなり、板厚が０．８ｍｍ以上の厚みを有する絶縁基板と、この絶縁基板の表面に設けられた銅箔からなる配線パターンと、この配線パターン上に鉛フリー半田によって半田付けされた電子部品とを備え、前記配線パターンは、信号ラインとアースパターンを有し、前記信号ラインと前記アースパターンのそれぞれの幅寸法が２ｍｍを越える箇所にあっては、前記配線パターンを形成する前記銅箔が除去された銅箔除去部を有し、前記信号ライン、及び前記アースパターンの外側縁と前記銅箔除去部との間の幅寸法を２ｍｍ以下にすると共に、前記銅箔除去部間の幅寸法を２ｍｍ以下にしたことを特徴とする電子回路ユニット。 An insulating substrate made of paper phenolic resin or paper epoxy resin and having a thickness of 0.8 mm or more, a wiring pattern made of copper foil provided on the surface of the insulating substrate, and lead-free on this wiring pattern An electronic component soldered by solder, and the wiring pattern has a signal line and a ground pattern, and the wiring pattern is located at a location where the width dimension of each of the signal line and the ground pattern exceeds 2 mm. The copper foil removing portion from which the copper foil forming the pattern is removed has a width dimension between the signal line and the outer edge of the ground pattern and the copper foil removing portion of 2 mm or less, and An electronic circuit unit characterized in that a width dimension between the copper foil removal portions is 2 mm or less. 前記配線パターンは、前記電子部品を半田付けするためのランド部有し、前記ランド部の幅寸法が２ｍｍを越える箇所にあっては、前記銅箔除去部が設けられて、前記ランド部の外側縁と前記銅箔除去部との間の幅寸法を２ｍｍ以下にしたことを特徴とする請求項１記載の電子回路ユニット。 The wiring pattern has a land portion for soldering the electronic component, and the copper foil removing portion is provided outside the land portion when the land portion has a width dimension exceeding 2 mm. 2. The electronic circuit unit according to claim 1, wherein a width dimension between an edge and the copper foil removing portion is 2 mm or less. 前記鉛フリー半田は、錫、銀、銅を主成分としたことを特徴とする請求項１、又は２記載の電子回路ユニット。 The electronic circuit unit according to claim 1, wherein the lead-free solder is mainly composed of tin, silver, and copper. 前記銅箔除去部は、孔、又は／及び切り欠き部によって形成されたことを特徴とする請求項１から３の何れかに記載の電子回路ユニット。 The electronic circuit unit according to claim 1, wherein the copper foil removing portion is formed by a hole or / and a cutout portion. 前記孔からなる前記銅箔除去部は、同じ大きさで、規則的に点在して形成されたことを特徴とする請求項４記載の電子回路ユニット。
5. The electronic circuit unit according to claim 4, wherein the copper foil removing portions made of the holes are formed in the same size and regularly scattered.
JP2004373617A 2004-12-24 2004-12-24 Electronic circuit unit Pending JP2006179809A (en)

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Cited By (3)

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Publication number Priority date Publication date Assignee Title
JP2008016725A (en) * 2006-07-07 2008-01-24 Sharp Corp Printed wiring board, method for mounting components thereof, and the board for mounting the electronic components
CN109725756A (en) * 2017-10-27 2019-05-07 东友精细化工有限公司 Electrode connecting structure and electronic device including the electrode connecting structure
WO2019159521A1 (en) * 2018-02-15 2019-08-22 株式会社村田製作所 Multilayer substrate and electric element

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JP2021048272A (en) * 2019-09-19 2021-03-25 株式会社東芝 Disk device

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008016725A (en) * 2006-07-07 2008-01-24 Sharp Corp Printed wiring board, method for mounting components thereof, and the board for mounting the electronic components
CN109725756A (en) * 2017-10-27 2019-05-07 东友精细化工有限公司 Electrode connecting structure and electronic device including the electrode connecting structure
US11392241B2 (en) 2017-10-27 2022-07-19 Dongwoo Fine-Chem Co., Ltd. Electrode connection structure and electronic device including the same
WO2019159521A1 (en) * 2018-02-15 2019-08-22 株式会社村田製作所 Multilayer substrate and electric element
JPWO2019159521A1 (en) * 2018-02-15 2020-08-27 株式会社村田製作所 Multilayer substrate and electric element
US11064606B2 (en) 2018-02-15 2021-07-13 Murata Manufacturing Co., Ltd. Multilayer substrate and electric element

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