JP2004079872A - Soldering structure for electronic circuit unit - Google Patents

Soldering structure for electronic circuit unit Download PDF

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Publication number
JP2004079872A
JP2004079872A JP2002240145A JP2002240145A JP2004079872A JP 2004079872 A JP2004079872 A JP 2004079872A JP 2002240145 A JP2002240145 A JP 2002240145A JP 2002240145 A JP2002240145 A JP 2002240145A JP 2004079872 A JP2004079872 A JP 2004079872A
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Japan
Prior art keywords
electronic circuit
circuit unit
land
soldering structure
solder
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Pending
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JP2002240145A
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Japanese (ja)
Inventor
Shuichi Takeda
武田　秀一
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Alps Alpine Co Ltd
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Alps Electric Co Ltd
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Publication date
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Priority to JP2002240145A priority Critical patent/JP2004079872A/en
Publication of JP2004079872A publication Critical patent/JP2004079872A/en
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a highly reliable soldering structure for electronic circuit unit without causing short-circuitting of an electronic circuit. <P>SOLUTION: In the soldering structure for electronic circuit unit, wall sections 7 and 13 for preventing flowing-out of solder composed of an insulating material are provided between first and second resist layers 6 and 12 provided in the vicinities of first and second land sections 4 and 11 to surround the land sections 4 and 11. Consequently, molten solder 14 does not flow out of a region surrounded by the first and second resist layers 6 and 12 and wall sections 7 and 13 and, accordingly, no solder ball occurs separately from the solder 14. Therefore, a highly reliable soldering structure can be provided without causing short-circuitting in electronic equipment. <P>COPYRIGHT: (C)2004,JPO

Description

【０００１】
【発明の属する技術分野】
本発明は電話機の送受信ユニット等に使用して好適な電子回路ユニットの半田付け構造に関する。
【０００２】
【従来の技術】
従来の電子回路ユニットの半田付け構造の図面を説明すると、図６は従来の電子回路ユニットの半田付け構造に係り、カバーを切断した状態を示す正面図、図７は従来の電子回路ユニットの半田付け構造を示す要部の拡大断面図、図８は従来の電子回路ユニットの半田付け構造を示し、電子回路ユニットの要部の拡大下面図である。
【０００３】
次に、従来の電子回路ユニットの半田付け構造の構成を図６〜図８に基づいて説明すると、一枚、或いは複数枚が積層されて構成されたプリント基板からなる回路基板５１の上面には、銅箔から成る配線パターン５２が設けられると共に、この配線パターン５２上には、種々の電気部品５３が搭載されて、所望の電気回路が形成されている。
【０００４】
また、回路基板５１の下面には、配線パターン５２に電気的に接続された複数個の第１のランド部５４と、この第１のランド部５４を除く箇所に設けられた接地用パターン５５が設けられている。
そして、第１のランド部５４の表面を露出した状態で、接地用パターン５５の表面を覆うと共に、回路基板５１の下面を覆うように形成された絶縁材からなる第１のレジスト層５６が設けられている。
【０００５】
また、回路基板５１の上面には、電気部品５３を覆うように、金属板から成る箱形のカバー５７が配置されている。
このような構成によって、従来の電子回路ユニットが形成されている。
【０００６】
プリント基板からなるマザー基板５８の上面には、導電パターン５９と、この導電パターン５９の一部で構成される複数個の第２のランド部６０と、第２のランド部６０の表面を露出した状態で、導電パターン５９の表面を覆うと共に、マザー基板５８の上面を覆うように形成された絶縁材からなる第２のレジスト層６１が設けられている。
【０００７】
そして、電子回路ユニットのマザー基板５８への半田付は、先ず、第１のランド部５４にクリーム半田（図示せず）を設けた後、第１のランド部５４と第２のランド部６０とを対向させた状態で、クリーム半田を第２のランド部６０上に接触させて、マザー基板５８上に電子回路ユニットを重ね合わせる。
【０００８】
次に、これをリフロー炉内に搬送して、クリーム半田を溶かし、第１，第２のランド部５４，６０を半田６２で接続すると、電子回路ユニットのマザー基板５８への半田付が完了する。
【０００９】
しかしながら、この半田付け時、図７に示すように、第１，第２のレジスト層５６，６１間の隙間Ｓが大きく、このため、溶けた半田６２は、この隙間Ｓ間に広がる。
そして、半田６２が固まると、広がった裾に位置する半田６２は、第１，第２のランド部５４，６０側に引き寄せられることなく、裾の位置でボール状に固まる。
【００１０】
その結果、図７に示すように、裾の位置で固まったものが半田ボール６３となって、半田６２から離れた状態で存在し、そして、この半田ボール６３は、電子機器の振動や衝撃等によって他の電気回路部に移動して、ショート等の問題を誘発するものであった。
【００１１】
【発明が解決しようとする課題】
従来の電子回路ユニットの半田付け構造は、第１，第２のランド部５４，６０が半田６２付けされた際、電子回路ユニット側の第１のレジスト層５６とマザー基板５８側の第２のレジスト層６１との間の隙間Ｓが大きいため、半田６２から離れた半田ボール６３が発生して、電気回路のショート等が発生するという問題がある。
【００１２】
そこで、本発明は電気回路のショート等の発生が無く、信頼性の高い電子回路ユニットの半田付け構造を提供することを目的とする。
【００１３】
【課題を解決するための手段】
上記課題を解決するための第１の解決手段として、配線パターン上に電気部品が搭載されて、所望の電気回路が形成された回路基板と、この回路基板の下面に設けられた第１のランド部と、この第１のランド部の外周を囲んだ状態で、前記回路基板の下面に設けられた第１のレジスト層と、前記第１のランド部と対向した第２のランド部を有するマザー基板と、前記第２のランド部の外周を囲んだ状態で、前記マザー基板の上面に設けられた第２のレジスト層と、前記第１，第２のランド部同士を電気的に接続する半田とを備え、前記第１，第２のランド部の近傍の前記第１，第２のレジスト層間には、前記第１，第２のランド部を囲むように配置された絶縁材からなる半田流出防止用の壁部が設けられた構成とした。
【００１４】
また、第２の解決手段として、前記第１，第２のレジスト層上のそれぞれに前記壁部が設けられた構成とした。
また、第３の解決手段として、前記第１，第２のレジスト層上の何れか一方に前記壁部が設けられた構成とした。
また、第４の解決手段として、前記壁部がシルク材で形成された構成とした。
【００１５】
【発明の実施の形態】
本発明の電子回路ユニットの半田付け構造図面を説明すると、図１は本発明の電子回路ユニットの半田付け構造の第１実施例に係り、カバーを切断した状態を示す正面図、図２は本発明の電子回路ユニットの半田付け構造の第１実施例に係り、要部の拡大断面図、図３は本発明の電子回路ユニットの半田付け構造の第１実施例に係り、電子回路ユニットの要部の拡大下面図である。
【００１６】
また、図４は本発明の電子回路ユニットの半田付け構造の第２実施例に係り、要部の拡大断面図、図５は本発明の電子回路ユニットの半田付け構造の第３実施例に係り、要部の拡大断面図である。
【００１７】
次に、本発明の電子回路ユニットの半田付け構造の第１実施例の構成を図１〜図３に基づいて説明すると、一枚、或いは複数枚が積層されて構成されたプリント基板からなる回路基板１の上面には、銅箔から成る配線パターン２が設けられると共に、この配線パターン２上には、種々の電気部品３が搭載されて、所望の電気回路が形成されている。
【００１８】
また、回路基板１の下面には、配線パターン２に電気的に接続された複数個の第１のランド部４と、この第１のランド部４を除く箇所に設けられた接地用パターン５が設けられている。
更に、回路基板１の下面には、第１のランド部４の表面を露出した状態で、接地用パターン５の表面を覆うと共に、回路基板１の下面を覆うように形成された絶縁材からなる第１のレジスト層６が設けられている。
【００１９】
また、第１のレジスト層６の表面には、第１のランド部４を露出した状態で第１のランド部４を囲むように配置され、絶縁材からなるシルク材を印刷形成された壁部７が設けられ、この壁部７の端部は、第１のランド部４の近傍に位置した状態となっている。
【００２０】
また、回路基板１の上面には、電気部品３を覆うように、金属板から成る箱形のカバー８が配置されている。
このような構成によって、本発明の電子回路ユニットが形成されている。
【００２１】
なお、前記第１のランド部４は、円形状のもので説明したが、楕円形状、矩形状等の円形状以外のものを使用しても良い。
【００２２】
プリント基板からなるマザー基板９の上面には、導電パターン１０と、この導電パターン１０の一部で構成される複数個の第２のランド部１１と、第２のランド部１１の表面を露出した状態で、導電パターン１０の表面を覆うと共に、マザー基板９の上面を覆うように形成された絶縁材からなる第２のレジスト層１２が設けられている。
【００２３】
また、第２のレジスト層１２の表面には、第２のランド部１１を露出した状態で第２のランド部１１を囲むように配置され、絶縁材からなるシルク材を印刷形成された壁部１３が設けられ、この壁部１３の端部は、第２のランド部１１の近傍に位置した状態となっている。
【００２４】
なお、前記第２のランド部１１は、円形状のもので説明したが、楕円形状、矩形状等の円形状以外のものを使用しても良い。
【００２５】
そして、電子回路ユニットのマザー基板９への半田付は、先ず、第１のランド部４にクリーム半田（図示せず）を設けた後、第１のランド部４と第２のランド部１１とを対向させた状態で、クリーム半田を第２のランド部１１上に接触させて、マザー基板９上に電子回路ユニットを重ね合わせる。
【００２６】
この時、図２に示すように、第１，第２のレンジスト層６，１２間は、壁部７，１３によって塞がれるか、或いは、その間の隙間Ｓは、極めて小さいものとなっており、この極めて小さい隙間Ｓは、クリーム半田が溶けた場合のガス抜き用としての機能を果たしている。
【００２７】
次に、これをリフロー炉内に搬送して、クリーム半田を溶かし、第１，第２のランド部４，１１を半田１４で接続すると、電子回路ユニットのマザー基板９への半田付が完了する。
【００２８】
そして、この半田付け時、図２に示すように、第１，第２のランド部４，１１の近傍に位置する第１，第２のレジスト層６，１２間は、壁部７，１３とで塞がれ、或いは、極めて小さい隙間Ｓとなった構成のため、溶けた半田１４は、第１，第２のレンジスト層６，１２と壁部７，１３とで囲まれた範囲以外に流出することが無い。
【００２９】
即ち、壁部７，１３が半田流出防止用の手段となり、その結果、半田１４から離れた状態での半田ボールが発生せず、このため、電子機器においてショート等が発生することが無い。
【００３０】
また、図４は、本発明の電子回路ユニットの半田付け構造の第２実施例を示し、この第２実施例は、壁部７，１３の幅を狭くしたものである。
その他の構成は前記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。
【００３１】
また、図５は、本発明の電子回路ユニットの半田付け構造の第３実施例を示し、この第３実施例は、第１，第２のレジスト層６，１２の何れか一方に壁部７，或いは壁部１３を設けたものである。
その他の構成は前記第１実施例と同様の構成を有し、同一部品に同一番号を付し、ここではその説明を省略する。
【００３２】
なお、上記実施例では壁部がシルク材で形成されたもので説明したが、壁部はシルク材以外の絶縁材で形成しても良い。
【００３３】
【発明の効果】
本発明の電子回路ユニットの半田付け構造は、配線パターン上に電気部品が搭載されて、所望の電気回路が形成された回路基板と、この回路基板の下面に設けられた第１のランド部と、この第１のランド部の外周を囲んだ状態で、回路基板の下面に設けられた第１のレジスト層と、第１のランド部と対向した第２のランド部を有するマザー基板と、第２のランド部の外周を囲んだ状態で、マザー基板の上面に設けられた第２のレジスト層と、第１，第２のランド部同士を電気的に接続する半田とを備え、第１，第２のランド部の近傍の第１，第２のレジスト層間には、第１，第２のランド部を囲むように配置された絶縁材からなる半田流出防止用の壁部が設けられた構成とした。
このように、第１，第２のランド部の近傍の第１，第２のレジスト層間には、第１，第２のランド部を囲むように配置された絶縁材からなる半田流出防止用の壁部が設けられることによって、溶けた半田は、第１，第２のレンジスト層と壁部とで囲まれた範囲以外に流出することが無く、従って、壁部が半田流出防止用の手段となり、半田から離れた状態での半田ボールが発生せず、このため、電子機器においてショート等の発生が無く、信頼性の高い半田付け構造を提供できる。
【００３４】
また、第１，第２のレジスト層上のそれぞれに壁部が設けられたため、壁部の高さの高いものが容易に得られる。
【００３５】
また、第１，第２のレジスト層上の何れか一方に壁部が設けられたため、壁部の製造の容易なものが得られる。
【００３６】
また、壁部がシルク材で形成されたため、壁部の高さの高いものが容易に得られる。
【図面の簡単な説明】
【図１】本発明の電子回路ユニットの半田付け構造の第１実施例に係り、カバーを切断した状態を示す正面図。
【図２】本発明の電子回路ユニットの半田付け構造の第１実施例に係り、要部の拡大断面図。
【図３】本発明の電子回路ユニットの半田付け構造の第１実施例に係り、電子回路ユニットの要部の拡大下面図。
【図４】本発明の電子回路ユニットの半田付け構造の第２実施例に係り、要部の拡大断面図。
【図５】本発明の電子回路ユニットの半田付け構造の第３実施例に係り、要部の拡大断面図。
【図６】従来の電子回路ユニットの半田付け構造に係り、カバーを切断した状態を示す正面図。
【図７】従来の電子回路ユニットの半田付け構造を示す要部の拡大断面図。
【図８】従来の電子回路ユニットの半田付け構造を示し、電子回路ユニットの要部の拡大下面図。
【符号の説明】
１　回路基板
２　配線パターン
３　電気部品
４　第１のランド部
５　接地用パターン
６　第１のレジスト層
７　壁部
８　カバー
９　マザー基板
１０　導電パターン
１１　第２のランド部
１２　第２のレジスト層
１３　壁部
１４　半田
Ｓ　隙間[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a soldering structure for an electronic circuit unit suitable for use in a transmitting / receiving unit of a telephone.
[0002]
[Prior art]
FIG. 6 relates to the soldering structure of a conventional electronic circuit unit, and FIG. 6 is a front view showing a state in which a cover is cut off, and FIG. 7 is a view showing a soldering structure of the conventional electronic circuit unit. FIG. 8 is an enlarged cross-sectional view of a main part showing a mounting structure, and FIG. 8 is a magnified bottom view of a main part of the electronic circuit unit, showing a soldering structure of a conventional electronic circuit unit.
[0003]
Next, the configuration of a conventional soldering structure of an electronic circuit unit will be described with reference to FIGS. 6 to 8. One or more of the circuit boards 51 are formed by laminating a printed circuit board. A wiring pattern 52 made of copper foil is provided, and various electric components 53 are mounted on the wiring pattern 52 to form a desired electric circuit.
[0004]
On the lower surface of the circuit board 51, a plurality of first lands 54 electrically connected to the wiring pattern 52 and a grounding pattern 55 provided at a location other than the first lands 54 are provided. Is provided.
Then, in a state where the surface of the first land portion 54 is exposed, a first resist layer 56 made of an insulating material is formed to cover the surface of the ground pattern 55 and to cover the lower surface of the circuit board 51. Have been.
[0005]
Further, a box-shaped cover 57 made of a metal plate is arranged on the upper surface of the circuit board 51 so as to cover the electric component 53.
With such a configuration, a conventional electronic circuit unit is formed.
[0006]
A conductive pattern 59, a plurality of second lands 60 formed by a part of the conductive pattern 59, and a surface of the second land 60 are exposed on an upper surface of a mother board 58 made of a printed board. In this state, a second resist layer 61 made of an insulating material and provided so as to cover the surface of the conductive pattern 59 and the upper surface of the mother substrate 58 is provided.
[0007]
Then, the soldering of the electronic circuit unit to the mother board 58 is performed by first providing cream solder (not shown) on the first land 54 and then connecting the first land 54 and the second land 60 with each other. The electronic circuit unit is superimposed on the mother board 58 by bringing the cream solder into contact with the second land portion 60 in a state where the electronic circuit units face each other.
[0008]
Next, this is transported into a reflow furnace to melt the cream solder, and the first and second lands 54 and 60 are connected by the solder 62, so that the soldering of the electronic circuit unit to the mother board 58 is completed. .
[0009]
However, at the time of this soldering, as shown in FIG. 7, the gap S between the first and second resist layers 56 and 61 is large, so that the melted solder 62 spreads between the gaps S.
When the solder 62 is solidified, the solder 62 located on the spread skirt is hardened in a ball shape at the skirt without being drawn to the first and second land portions 54 and 60.
[0010]
As a result, as shown in FIG. 7, what solidifies at the skirt position becomes a solder ball 63, which is present in a state separated from the solder 62. As a result, it moves to another electric circuit part, and causes a problem such as a short circuit.
[0011]
[Problems to be solved by the invention]
In the conventional soldering structure of an electronic circuit unit, when the first and second lands 54 and 60 are soldered, the first resist layer 56 on the electronic circuit unit side and the second resist layer 56 on the mother board 58 side are used. Since the gap S between the resist layer 61 and the resist layer 61 is large, there is a problem that a solder ball 63 separated from the solder 62 is generated and a short circuit or the like of an electric circuit occurs.
[0012]
Therefore, an object of the present invention is to provide a highly reliable soldering structure for an electronic circuit unit without occurrence of a short circuit or the like in an electric circuit.
[0013]
[Means for Solving the Problems]
As a first means for solving the above problems, a circuit board on which an electric component is mounted on a wiring pattern and a desired electric circuit is formed, and a first land provided on the lower surface of the circuit board A first resist layer provided on the lower surface of the circuit board in a state surrounding the outer periphery of the first land portion, and a second land portion facing the first land portion. A second resist layer provided on an upper surface of the mother substrate and a solder for electrically connecting the first and second land portions to each other while surrounding a substrate and an outer periphery of the second land portion; A solder outflow made of an insulating material disposed so as to surround the first and second land portions between the first and second resist layers in the vicinity of the first and second land portions. The configuration is such that a wall for prevention is provided.
[0014]
As a second solution, the wall portion is provided on each of the first and second resist layers.
As a third solution, the wall portion is provided on one of the first and second resist layers.
As a fourth solution, the wall portion is formed of a silk material.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Referring to the drawings of the soldering structure of the electronic circuit unit of the present invention, FIG. 1 relates to a first embodiment of the soldering structure of the electronic circuit unit of the present invention. FIG. FIG. 3 is an enlarged sectional view of a main part of the soldering structure of the electronic circuit unit according to the first embodiment of the present invention, and FIG. It is an enlarged bottom view of a part.
[0016]
FIG. 4 relates to a second embodiment of the soldering structure of the electronic circuit unit of the present invention, and is an enlarged cross-sectional view of a main part, and FIG. 5 relates to a third embodiment of the soldering structure of the electronic circuit unit of the present invention. It is an expanded sectional view of an important section.
[0017]
Next, the configuration of the first embodiment of the soldering structure of the electronic circuit unit according to the present invention will be described with reference to FIGS. 1 to 3. A circuit composed of a printed circuit board formed by laminating one or more sheets A wiring pattern 2 made of copper foil is provided on the upper surface of the substrate 1, and various electric components 3 are mounted on the wiring pattern 2 to form a desired electric circuit.
[0018]
On the lower surface of the circuit board 1, a plurality of first lands 4 electrically connected to the wiring pattern 2 and a grounding pattern 5 provided at a location other than the first lands 4 are provided. Is provided.
Further, the lower surface of the circuit board 1 is made of an insulating material formed so as to cover the surface of the grounding pattern 5 and to cover the lower surface of the circuit board 1 with the surface of the first land portion 4 exposed. A first resist layer 6 is provided.
[0019]
On the surface of the first resist layer 6, a wall portion is disposed so as to surround the first land portion 4 with the first land portion 4 being exposed, and is formed by printing a silk material made of an insulating material. 7 is provided, and the end of the wall 7 is located near the first land 4.
[0020]
A box-shaped cover 8 made of a metal plate is arranged on the upper surface of the circuit board 1 so as to cover the electric components 3.
With such a configuration, the electronic circuit unit of the present invention is formed.
[0021]
Although the first land portion 4 has been described as having a circular shape, a shape other than a circular shape such as an elliptical shape or a rectangular shape may be used.
[0022]
On the upper surface of a mother board 9 made of a printed board, a conductive pattern 10, a plurality of second lands 11 formed by a part of the conductive pattern 10, and a surface of the second land 11 are exposed. In this state, a second resist layer 12 made of an insulating material and provided so as to cover the surface of the conductive pattern 10 and the upper surface of the mother substrate 9 is provided.
[0023]
On the surface of the second resist layer 12, a wall portion is disposed so as to surround the second land portion 11 with the second land portion 11 exposed, and is formed by printing a silk material made of an insulating material. 13 is provided, and an end of the wall portion 13 is located near the second land portion 11.
[0024]
The second land portion 11 has been described as having a circular shape, but may have a shape other than a circular shape such as an elliptical shape or a rectangular shape.
[0025]
Then, soldering of the electronic circuit unit to the mother board 9 is performed by first providing cream solder (not shown) on the first land portion 4 and then bonding the first land portion 4 and the second land portion 11 to each other. The electronic circuit unit is superimposed on the mother board 9 by bringing cream solder into contact with the second land portion 11 in a state where the electronic circuit units are opposed to each other.
[0026]
At this time, as shown in FIG. 2, the space between the first and second range strike layers 6 and 12 is closed by the wall portions 7 and 13 or the gap S between them is extremely small. The extremely small gap S functions as a gas vent when the cream solder is melted.
[0027]
Next, this is transported into a reflow furnace, the cream solder is melted, and the first and second lands 4, 11 are connected by solder 14, so that the soldering of the electronic circuit unit to the mother board 9 is completed. .
[0028]
At the time of this soldering, as shown in FIG. 2, between the first and second resist layers 6 and 12 located near the first and second land portions 4 and 11, the wall portions 7 and 13 The molten solder 14 flows out of the area surrounded by the first and second range strike layers 6 and 12 and the walls 7 and 13 due to the configuration in which the gap S is closed or the gap S is extremely small. Nothing to do.
[0029]
That is, the wall portions 7 and 13 serve as means for preventing the solder from flowing out. As a result, no solder ball is generated apart from the solder 14, so that a short circuit or the like does not occur in the electronic device.
[0030]
FIG. 4 shows a second embodiment of the soldering structure of the electronic circuit unit according to the present invention. In the second embodiment, the width of the walls 7 and 13 is reduced.
The other configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and description thereof is omitted here.
[0031]
FIG. 5 shows a third embodiment of the soldering structure of the electronic circuit unit according to the present invention. In the third embodiment, the wall portion 7 is provided on one of the first and second resist layers 6 and 12. Alternatively, a wall 13 is provided.
The other configuration is the same as that of the first embodiment, the same components are denoted by the same reference numerals, and description thereof is omitted here.
[0032]
In the above embodiment, the wall portion is formed of a silk material, but the wall portion may be formed of an insulating material other than the silk material.
[0033]
【The invention's effect】
The soldering structure of the electronic circuit unit according to the present invention includes a circuit board on which an electric component is mounted on a wiring pattern and on which a desired electric circuit is formed, and a first land portion provided on a lower surface of the circuit board. A first resist layer provided on the lower surface of the circuit board in a state surrounding the outer periphery of the first land, a mother substrate having a second land opposed to the first land, A second resist layer provided on the upper surface of the mother substrate in a state surrounding the outer periphery of the second land portion, and a solder for electrically connecting the first and second land portions to each other; A configuration in which a wall for preventing solder outflow made of an insulating material disposed so as to surround the first and second land portions is provided between the first and second resist layers near the second land portion. And
As described above, between the first and second resist layers in the vicinity of the first and second lands, the solder outflow preventing material made of the insulating material disposed so as to surround the first and second lands is provided. By providing the wall portion, the melted solder does not flow out of the area surrounded by the first and second rangenst layers and the wall portion. Therefore, the wall portion serves as a means for preventing the solder from flowing out. In addition, no solder balls are generated in a state separated from the solder, so that a short-circuit or the like does not occur in the electronic device, and a highly reliable soldering structure can be provided.
[0034]
In addition, since the walls are provided on the first and second resist layers, a high wall can be easily obtained.
[0035]
In addition, since the wall is provided on one of the first and second resist layers, an easily manufactured wall can be obtained.
[0036]
In addition, since the wall is formed of a silk material, a high wall can be easily obtained.
[Brief description of the drawings]
FIG. 1 is a front view showing a state in which a cover is cut off according to a first embodiment of a soldering structure of an electronic circuit unit of the present invention.
FIG. 2 is an enlarged sectional view of a main part according to the first embodiment of the soldering structure of the electronic circuit unit of the present invention.
FIG. 3 is an enlarged bottom view of a main part of the electronic circuit unit according to the first embodiment of the soldering structure of the electronic circuit unit of the present invention.
FIG. 4 is an enlarged sectional view of a main part according to a second embodiment of the soldering structure of the electronic circuit unit of the present invention.
FIG. 5 is an enlarged sectional view of a main part according to a third embodiment of the soldering structure of the electronic circuit unit of the present invention.
FIG. 6 is a front view showing a state in which a cover is cut in a conventional soldering structure of an electronic circuit unit.
FIG. 7 is an enlarged sectional view of a main part showing a soldering structure of a conventional electronic circuit unit.
FIG. 8 is an enlarged bottom view of a main part of the electronic circuit unit, showing a soldering structure of the conventional electronic circuit unit.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Circuit board 2 Wiring pattern 3 Electric component 4 First land part 5 Grounding pattern 6 First resist layer 7 Wall part 8 Cover 9 Mother substrate 10 Conductive pattern 11 Second land part 12 Second resist layer 13 Wall Part 14 Solder S gap

Claims (4)

配線パターン上に電気部品が搭載されて、所望の電気回路が形成された回路基板と、この回路基板の下面に設けられた第１のランド部と、この第１のランド部の外周を囲んだ状態で、前記回路基板の下面に設けられた第１のレジスト層と、前記第１のランド部と対向した第２のランド部を有するマザー基板と、前記第２のランド部の外周を囲んだ状態で、前記マザー基板の上面に設けられた第２のレジスト層と、前記第１，第２のランド部同士を電気的に接続する半田とを備え、前記第１，第２のランド部の近傍の前記第１，第２のレジスト層間には、前記第１，第２のランド部を囲むように配置された絶縁材からなる半田流出防止用の壁部が設けられたことを特徴とする電子回路ユニットの半田付け構造。A circuit board on which an electric component is mounted on the wiring pattern to form a desired electric circuit; a first land provided on a lower surface of the circuit board; and an outer periphery of the first land. In this state, a first resist layer provided on the lower surface of the circuit board, a mother board having a second land opposed to the first land, and an outer periphery of the second land are surrounded. A second resist layer provided on an upper surface of the mother substrate, and a solder for electrically connecting the first and second land portions to each other; A wall portion for preventing solder outflow made of an insulating material is provided between the first and second resist layers in the vicinity so as to surround the first and second land portions. Soldering structure of electronic circuit unit. 前記第１，第２のレジスト層上のそれぞれに前記壁部が設けられたことを特徴とする請求項１記載の電子回路ユニットの半田付け構造。2. The soldering structure for an electronic circuit unit according to claim 1, wherein said wall portion is provided on each of said first and second resist layers. 前記第１，第２のレジスト層上の何れか一方に前記壁部が設けられたことを特徴とする請求項１記載の電子回路ユニットの半田付け構造。2. The soldering structure for an electronic circuit unit according to claim 1, wherein said wall portion is provided on one of said first and second resist layers. 前記壁部がシルク材で形成されたことを特徴とする請求項１から３の何れかに記載の電子回路ユニットの半田付け構造。4. The soldering structure for an electronic circuit unit according to claim 1, wherein the wall is formed of a silk material.
JP2002240145A 2002-08-21 2002-08-21 Soldering structure for electronic circuit unit Pending JP2004079872A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7866800B2 (en) 2007-10-16 2011-01-11 Brother Kogyo Kabushiki Kaisha Liquid droplet jetting apparatus and method for manufacturing liquid droplet jetting apparatus
US8330277B2 (en) 2009-12-24 2012-12-11 Shinko Electric Industries Co., Ltd. Semiconductor element built-in device
JP2012256672A (en) * 2011-06-08 2012-12-27 Panasonic Corp Mounting structure of semiconductor component
CN114501792A (en) * 2021-07-09 2022-05-13 荣耀终端有限公司 Circuit board assembly and electronic equipment

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7866800B2 (en) 2007-10-16 2011-01-11 Brother Kogyo Kabushiki Kaisha Liquid droplet jetting apparatus and method for manufacturing liquid droplet jetting apparatus
US8330277B2 (en) 2009-12-24 2012-12-11 Shinko Electric Industries Co., Ltd. Semiconductor element built-in device
JP2012256672A (en) * 2011-06-08 2012-12-27 Panasonic Corp Mounting structure of semiconductor component
CN114501792A (en) * 2021-07-09 2022-05-13 荣耀终端有限公司 Circuit board assembly and electronic equipment

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