JP2010212591A - Circuit board and method for manufacturing the same - Google Patents

Circuit board and method for manufacturing the same Download PDF

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JP2010212591A
JP2010212591A JP2009059411A JP2009059411A JP2010212591A JP 2010212591 A JP2010212591 A JP 2010212591A JP 2009059411 A JP2009059411 A JP 2009059411A JP 2009059411 A JP2009059411 A JP 2009059411A JP 2010212591 A JP2010212591 A JP 2010212591A
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solder
land portion
circuit board
insulating substrate
land
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Takehito Matsuura
猛仁 松浦
Koshi Kobayashi
皇士 小林
Makoto Tabuchi
誠 田渕
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Sanyo Electric Co Ltd
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Sanyo Electric Co Ltd
Sanyo Consumer Electronics Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board for improving yield by covering a through-hole with a mask to prevent the through-hole from being closed by first solder in a reflow soldering. <P>SOLUTION: The method for manufacturing a circuit board 1 includes: providing first and second land portions 11, 21 by exposing a part of a conductor portion 4 formed on an insulating substrate 2, soldering a chip component 10 on the first land portion 11, and soldering an insertion component 20 to the second land portion 21 having the through-hole 21a. The manufacturing method further includes: a reflow soldering step of covering a predetermined position with a mask 6 and applying a paste-like first solder 12 on the first and second land portions 11, 21, a chip component mounting step of soldering the chip component 10 to the first land portion 11, a flow soldering step of providing a second solder 22 on the second land portion 21 by immersing the insulating substrate 2 into a solder bath, and an insertion component mounting step of soldering an insertion component 20 inserted into the through-hole 21a to the second land portion 21. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、チップ部品と挿入部品を実装した回路基板及びその製造方法に関する。   The present invention relates to a circuit board on which a chip part and an insertion part are mounted, and a manufacturing method thereof.

従来の回路基板は特許文献1に開示される。この回路基板は絶縁基板に設けられた導体部の一部を露出したランド部にリフロー半田工程及びフロー半田工程によって半田が設けられる。リフロー半田工程はクリーム半田等のペースト状の半田がランド部に塗布される。IC等のチップ部品はリフロー半田工程で設けられた半田上に設置され、恒温槽で所定温度に昇温して半田付けされる。   A conventional circuit board is disclosed in Patent Document 1. In this circuit board, solder is provided by a reflow soldering process and a flow soldering process on a land part where a part of a conductor part provided on an insulating substrate is exposed. In the reflow soldering process, paste solder such as cream solder is applied to the land portion. A chip component such as an IC is placed on the solder provided in the reflow soldering process, and is heated to a predetermined temperature in a constant temperature bath and soldered.

フロー工程は半田槽内に絶縁基板を浸漬して貫通孔を有するランド部に半田が設けられる。コンデンサ等の挿入部品は貫通孔に挿入され、貫通孔の周囲のランド部に設けた半田により半田付けされる。   In the flow process, the insulating substrate is immersed in a solder bath and solder is provided on the land portion having a through hole. An insertion component such as a capacitor is inserted into the through hole and soldered by solder provided on a land portion around the through hole.

特開2008−60327号公報(第4頁−第5頁、第5図)JP 2008-60327 A (pages 4-5, FIG. 5)

しかしながら、上記従来の回路基板によると、リフロー半田工程で絶縁基板を恒温槽に入れるため、挿入部品が配されるランド部が酸化し易くなる。このため、フロー半田工程で該ランド部に半田が付きにくく、挿入部品の半田付け不良が生じて回路基板の歩留りが低下する問題があった。   However, according to the conventional circuit board, since the insulating substrate is placed in the thermostatic bath in the reflow soldering process, the land portion on which the insertion component is arranged is easily oxidized. For this reason, there is a problem that the solder is difficult to be attached to the land portion in the flow soldering process, the soldering failure of the inserted component occurs, and the yield of the circuit board is lowered.

本発明は、歩留りを向上できる回路基板及びその製造方法を提供することを目的とする。   An object of this invention is to provide the circuit board which can improve a yield, and its manufacturing method.

上記目的を達成するために本発明は、絶縁基板上に形成される導体部の一部を露出した第1、第2ランド部を設け、第1ランド部にチップ部品を半田付けするとともに貫通孔を有する第2ランド部に挿入部品を半田付けする回路基板の製造方法において、マスクにより所定位置を覆って第1、第2ランド部にペースト状の第1半田を塗布するリフロー半田工程と、第1ランド部に前記チップ部品を半田付けするチップ部品実装工程と、前記絶縁基板を半田槽に浸漬して第2半田を第2ランド部に設けるフロー半田工程と、前記貫通孔に挿入した前記挿入部品を第2ランド部に半田付けする挿入部品実装工程とを備えたことを特徴としている。   In order to achieve the above object, the present invention provides first and second land portions exposing a part of a conductor portion formed on an insulating substrate, soldering a chip component to the first land portion, and through holes A reflow soldering process in which a paste-like first solder is applied to the first and second land portions so as to cover a predetermined position with a mask; A chip component mounting step of soldering the chip component to one land portion, a flow soldering step of immersing the insulating substrate in a solder bath to provide a second solder in the second land portion, and the insertion inserted into the through hole And an insertion component mounting step of soldering the component to the second land portion.

この構成によると、絶縁基板上には所定のパターンの導体部が形成され、導体部の一部を露出して第1、第2ランド部が設けられる。リフロー半田工程では第1、第2ランド部を露出してマスクにより絶縁基板が覆われ、第1、第2ランド部上にクリーム半田等のペースト状の第1半田が塗布される。チップ部品実装工程では第1ランド部の第1半田上にチップ部品が設置され、絶縁基板を恒温槽に入れてチップ部品が半田付けされる。フロー半田工程では絶縁基板が半田槽に浸漬され、第2ランド部の第1半田上に第2半田が付着する。この時、チップ部品を覆って絶縁基板を半田槽に浸漬してもよい。挿入部品実装工程では第2ランド部の貫通孔に挿入部品が挿入され、第2半田によって挿入部品が半田付けされる。   According to this configuration, the conductor portion having a predetermined pattern is formed on the insulating substrate, and the first and second land portions are provided by exposing a part of the conductor portion. In the reflow soldering process, the first and second land portions are exposed, the insulating substrate is covered with a mask, and paste-like first solder such as cream solder is applied on the first and second land portions. In the chip component mounting step, the chip component is placed on the first solder of the first land portion, and the chip component is soldered by placing the insulating substrate in a constant temperature bath. In the flow soldering process, the insulating substrate is immersed in the solder bath, and the second solder adheres to the first solder on the second land portion. At this time, the insulating substrate may be immersed in a solder bath covering the chip component. In the insertion component mounting step, the insertion component is inserted into the through hole of the second land portion, and the insertion component is soldered by the second solder.

また本発明は、上記構成の回路基板の製造方法において、前記マスクにより前記貫通孔を覆うことを特徴としている。この構成によると、リフロー半田工程で貫通孔がマスクにより覆われ、第1半田による貫通孔の閉塞が防止される。   According to the present invention, in the method for manufacturing a circuit board having the above configuration, the through hole is covered with the mask. According to this configuration, the through hole is covered with the mask in the reflow soldering process, and the blocking of the through hole by the first solder is prevented.

また本発明は、上記構成の回路基板の製造方法において、前記絶縁基板の両面に第1ランド部を設けて前記チップ部品が実装されるとともに一方の面の第2ランド部に第2半田を設け、一方の面の前記リフロー半田工程を他方の面の前記チップ部品実装工程の前に行うことを特徴としている。   According to the present invention, in the method for manufacturing a circuit board having the above-described configuration, the chip component is mounted by providing the first land portions on both surfaces of the insulating substrate, and the second solder is provided on the second land portion on one surface. The reflow soldering process on one surface is performed before the chip component mounting process on the other surface.

この構成によると、例えば、絶縁基板の表面の第1ランド部にリフロー半田工程によって第1半田が塗布され、次に裏面の第1、第2ランド部にリフロー半田工程によって第1半田が塗布される。そして、チップ部品実装工程によって両面の第1ランド部にチップ部品が実装された後に、フロー半田工程によって裏面の第2ランド部に第2半田が設けられる。裏面の第1ランド部にチップ部品を実装した後に表面の第1ランド部のリフロー半田工程を行ってもよい。   According to this configuration, for example, the first solder is applied to the first land portion on the surface of the insulating substrate by the reflow solder process, and then the first solder is applied to the first and second land portions on the back surface by the reflow solder process. The Then, after the chip components are mounted on the first land portions on both sides by the chip component mounting step, the second solder is provided on the second land portions on the back surface by the flow solder process. After the chip component is mounted on the first land portion on the back surface, a reflow soldering process for the first land portion on the front surface may be performed.

また本発明は、絶縁基板上に第1ランド部と貫通孔を有する第2ランド部とが露出し、第1ランド部にペースト状の第1半田を塗布してチップ部品が半田付けされるとともに、前記絶縁基板を半田槽に浸漬することによって第2ランド部に第2半田を設けて挿入部品が半田付けされる回路基板において、第2ランド部に第1半田を塗布した後に第2半田を設けたことを特徴としている。   According to the present invention, the first land portion and the second land portion having the through hole are exposed on the insulating substrate, and the chip component is soldered by applying the paste-like first solder to the first land portion. In the circuit board in which the second land is provided in the second land portion by immersing the insulating substrate in the solder bath and the inserted component is soldered, the second solder is applied after the first solder is applied to the second land portion. It is characterized by providing.

この構成によると、第1半田が塗布された第1ランド部上にチップ部品が半田付けされる。第2ランド部には第1、第2半田が積層され、第2ランド部の貫通孔に挿入された挿入部品が半田付けされる。   According to this configuration, the chip component is soldered on the first land portion to which the first solder is applied. First and second solders are stacked on the second land portion, and an insertion component inserted into the through hole of the second land portion is soldered.

本発明によると、挿入部品が取り付けられる第2ランド部にペースト状の第1半田を塗布し、絶縁基板を半田槽に浸漬して第2ランド部の第1半田上に第2半田を設けるので、高価なメッキ処理等を必要とせず第2ランド部の酸化を防止することができる。従って、挿入部品の半田付け不良を低減して回路基板の歩留りを向上することができる。加えて、第1半田に含まれるフラックス成分によって第2半田が付きやすくなり、半田付け時間を短縮して電子部品への熱ストレスを低減することができる。   According to the present invention, the paste-like first solder is applied to the second land portion to which the insert component is attached, and the second solder is provided on the first solder of the second land portion by immersing the insulating substrate in the solder bath. Further, oxidation of the second land portion can be prevented without requiring an expensive plating process or the like. Therefore, it is possible to reduce the soldering failure of the inserted part and improve the yield of the circuit board. In addition, the second solder is easily attached by the flux component contained in the first solder, and the soldering time can be shortened to reduce the thermal stress on the electronic component.

本発明の実施形態の回路基板を示す側面断面図Side surface sectional drawing which shows the circuit board of embodiment of this invention 本発明の実施形態の回路基板の表面リフロー半田工程を示す側面断面図Side surface sectional drawing which shows the surface reflow soldering process of the circuit board of embodiment of this invention 本発明の実施形態の回路基板の表面チップ部品実装工程を示す側面断面図Side surface sectional drawing which shows the surface chip component mounting process of the circuit board of embodiment of this invention 本発明の実施形態の回路基板の裏面リフロー半田工程を示す側面断面図Side surface sectional drawing which shows the back surface reflow soldering process of the circuit board of embodiment of this invention 本発明の実施形態の回路基板の裏面リフロー半田工程のマスクを示す平面図The top view which shows the mask of the back surface reflow soldering process of the circuit board of embodiment of this invention 図5のA部及びB部拡大図Part A and part B enlarged view of FIG. 本発明の実施形態の回路基板の裏面リフロー半田工程の第2ランド部を示す平面図The top view which shows the 2nd land part of the back surface reflow soldering process of the circuit board of embodiment of this invention 本発明の実施形態の回路基板の裏面チップ部品実装工程を示す側面断面図Side surface sectional drawing which shows the back surface chip component mounting process of the circuit board of embodiment of this invention 本発明の実施形態の回路基板のフロー半田工程を示す側面断面図Side surface sectional drawing which shows the flow soldering process of the circuit board of embodiment of this invention

以下に本発明の実施形態を図面を参照して説明する。図1は一実施形態の回路基板を示す側面断面図である。回路基板1は絶縁基板2上に銅箔等によって所定のパターンの導体部4が形成される。導体部4はレジスト5により覆われて一部が露出し、第1、第2ランド部11、21が形成される。第2ランド部21は絶縁基板2を貫通する貫通孔21aの周囲に設けられる。   Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a side sectional view showing a circuit board according to an embodiment. In the circuit board 1, a conductor portion 4 having a predetermined pattern is formed on an insulating substrate 2 by a copper foil or the like. The conductor portion 4 is covered with a resist 5 and a part thereof is exposed, and first and second land portions 11 and 21 are formed. The second land portion 21 is provided around a through hole 21 a that penetrates the insulating substrate 2.

第1ランド部11上にはクリーム半田等のペースト状の第1半田12が塗布され、IC等のチップ部品10の脚部10aが半田付けされる。第2ランド部12上には半田槽に絶縁基板2を浸漬して第2半田22が設けられ、コンデンサ等の挿入部品20の脚部20aが貫通孔21aに挿入して半田付けされる。   A paste-like first solder 12 such as cream solder is applied on the first land portion 11, and the leg portion 10a of the chip component 10 such as an IC is soldered. A second solder 22 is provided on the second land portion 12 by dipping the insulating substrate 2 in a solder bath, and a leg portion 20a of an insertion component 20 such as a capacitor is inserted into the through hole 21a and soldered.

図2〜図9は回路基板1の製造工程を示している。図2は絶縁基板2の一方の面(表面)の第1ランド部11に第1半田を塗布する表面リフロー半田工程の側面断面図を示している。絶縁基板2には導体部4の一部を露出した第1、第2ランド部11、21が形成され、表面の第1ランド部11にクリーム半田等のペースト状の第1半田12が塗布される。この時、貫通孔21aを有する表面の第2ランド部21はマスク等により覆われる。   2 to 9 show the manufacturing process of the circuit board 1. FIG. 2 shows a side cross-sectional view of a surface reflow soldering process in which the first solder is applied to the first land portion 11 on one surface (front surface) of the insulating substrate 2. The insulating substrate 2 is formed with first and second land portions 11 and 21 in which a part of the conductor portion 4 is exposed, and paste-like first solder 12 such as cream solder is applied to the first land portion 11 on the surface. The At this time, the second land portion 21 on the surface having the through hole 21a is covered with a mask or the like.

次に、図3は絶縁基板2の表面にチップ部品10を実装する表面チップ部品実装工程の側面断面図を示している。絶縁基板2の表面の第1ランド部11の第1半田12上にはIC等のチップ部品10の脚部10aが設置される。そして、絶縁基板2が恒温槽に入れられ、溶融した第1半田12によってチップ部品10が半田付けされる。   Next, FIG. 3 shows a side sectional view of a surface chip component mounting process for mounting the chip component 10 on the surface of the insulating substrate 2. On the first solder 12 of the first land portion 11 on the surface of the insulating substrate 2, a leg portion 10 a of a chip component 10 such as an IC is installed. Then, the insulating substrate 2 is placed in a constant temperature bath, and the chip component 10 is soldered by the melted first solder 12.

次に、図4は絶縁基板2の他方の面(裏面)の第1ランド部11に第1半田12を塗布する裏面リフロー半田工程の側面断面図を示している。絶縁基板2の裏面上には図5に示すようなマスク6が設置される。マスク6によって第1半田12を塗布する第1、第2ランド部11、21を露出して絶縁基板2が覆われる。そして、クリーム半田等のペースト状の第1半田12が第1、第2ランド部11、21に塗布される。   Next, FIG. 4 shows a side cross-sectional view of a back surface reflow soldering process in which the first solder 12 is applied to the first land portion 11 on the other surface (back surface) of the insulating substrate 2. On the back surface of the insulating substrate 2, a mask 6 as shown in FIG. The insulating substrate 2 is covered by exposing the first and second land portions 11 and 21 to which the first solder 12 is applied by the mask 6. Then, paste-like first solder 12 such as cream solder is applied to the first and second land portions 11 and 21.

図6は図5のA部及びB部の詳細を示している。マスク6は第2ランド部21に対向する複数のアーチ状の孔部6aが環状に配置される。これにより、孔部6aの内縁の内側には第2ランド部21の貫通孔21aを覆う円形の遮蔽部6bが形成される。絶縁基板2をマスク6で覆って第1半田12を塗布すると、図7に示すように第2ランド部21上にアーチ状の第1半田12が形成される。   FIG. 6 shows details of part A and part B of FIG. In the mask 6, a plurality of arch-shaped holes 6 a facing the second land portion 21 are annularly arranged. Thereby, the circular shielding part 6b which covers the through-hole 21a of the 2nd land part 21 is formed inside the inner edge of the hole 6a. When the insulating substrate 2 is covered with the mask 6 and the first solder 12 is applied, the arch-shaped first solder 12 is formed on the second land portion 21 as shown in FIG.

次に、図8は絶縁基板2の裏面にチップ部品10を実装する裏面チップ部品実装工程の側面断面図を示している。絶縁基板2の裏面の第1ランド部11の第1半田12上にはチップ部品10の脚部10aが設置される。そして、絶縁基板2が恒温槽に入れられ、溶融した第1半田12によってチップ部品10が半田付けされる。   Next, FIG. 8 shows a side cross-sectional view of a back surface chip component mounting process for mounting the chip component 10 on the back surface of the insulating substrate 2. A leg portion 10 a of the chip component 10 is installed on the first solder 12 of the first land portion 11 on the back surface of the insulating substrate 2. Then, the insulating substrate 2 is placed in a constant temperature bath, and the chip component 10 is soldered by the melted first solder 12.

次に、図9は絶縁基板2の裏面の第2ランド部21に第2半田22を設けるフロー半田工程の側面断面図を示している。絶縁基板2は両面のチップ部品10や表面の第2ランド部21をマスク(不図示)により覆われ、半田槽に浸漬される。これにより、裏面の第2ランド部21に第2半田22が設けられる。この時、第2半田22は第2ランド部21に塗布された第1半田12上に付着するため、第1半田12に含まれるフラックス成分により第2半田22を容易に付着させることができる。   Next, FIG. 9 shows a side sectional view of a flow soldering process in which the second solder 22 is provided on the second land portion 21 on the back surface of the insulating substrate 2. The insulating substrate 2 covers the chip component 10 on both sides and the second land portion 21 on the surface with a mask (not shown) and is immersed in a solder bath. Thereby, the second solder 22 is provided on the second land portion 21 on the back surface. At this time, since the second solder 22 adheres on the first solder 12 applied to the second land portion 21, the second solder 22 can be easily attached by the flux component contained in the first solder 12.

そして、挿入部品実装工程で貫通孔21aに挿入部品20の脚部20aが挿入されて挿入部品20が半田付けされ、前述の図1に示す回路基板1が得られる。   Then, in the insertion component mounting step, the leg 20a of the insertion component 20 is inserted into the through hole 21a and the insertion component 20 is soldered, whereby the circuit board 1 shown in FIG. 1 is obtained.

本実施形態によると、裏面リフロー半田工程(リフロー半田工程)で挿入部品20が取り付けられる第2ランド部21にペースト状の第1半田12を塗布し、フロー半田工程で絶縁基板2を半田槽に浸漬して第2ランド部21の第1半田上12に第2半田22を設けるので、高価なメッキ処理等を必要とせず第2ランド部21の酸化を防止することができる。従って、挿入部品20の半田付け不良を低減して回路基板1の歩留りを向上することができる。加えて、第1半田12に含まれるフラックス成分によって第2半田22が付きやすくなり、半田付け時間を短縮して電子部品への熱ストレスを低減することができる。   According to the present embodiment, the paste-like first solder 12 is applied to the second land portion 21 to which the insertion component 20 is attached in the back surface reflow soldering process (reflow soldering process), and the insulating substrate 2 is placed in the solder bath in the flow soldering process. Since the second solder 22 is provided on the first solder 12 of the second land portion 21 by immersion, oxidation of the second land portion 21 can be prevented without requiring an expensive plating process or the like. Therefore, the soldering failure of the insertion component 20 can be reduced and the yield of the circuit board 1 can be improved. In addition, the second solder 22 is easily attached by the flux component contained in the first solder 12, and the soldering time can be shortened to reduce the thermal stress on the electronic component.

また、裏面リフロー半田工程でマスク6により貫通孔21aを覆うので、貫通孔21aの第1半田12による閉塞を防止することができる。   Further, since the through hole 21a is covered with the mask 6 in the back surface reflow soldering process, the through hole 21a can be prevented from being blocked by the first solder 12.

本実施形態において、裏面リフロー半田工程を表面チップ部品実装工程の後に行っているが、表面チップ部品実装工程の前に行ってもよい。これにより、表面チップ部品実装工程で絶縁基板2を恒温槽に入れる前に第2半田22が設けられる裏面の第2ランド部21に第1半田12が塗布される。従って、第2ランド部21の酸化をより確実に防止することができる。尚、裏面チップ部品実装工程の後に表面リフロー半田工程及び表面チップ部品実装工程を行ってもよい。   In the present embodiment, the back surface reflow soldering process is performed after the front surface chip component mounting process, but may be performed before the front surface chip component mounting process. Thus, the first solder 12 is applied to the second land portion 21 on the back surface on which the second solder 22 is provided before the insulating substrate 2 is placed in the thermostatic chamber in the surface chip component mounting process. Therefore, the oxidation of the second land portion 21 can be prevented more reliably. In addition, you may perform a surface reflow soldering process and a surface chip component mounting process after a back surface chip component mounting process.

本発明によると、チップ部品と挿入部品を実装した回路基板に利用することができる。   The present invention can be used for a circuit board on which a chip component and an insertion component are mounted.

1 回路基板
2 絶縁基板
4 導体部
5 レジスト
6 マスク
6a 孔部
10 チップ部品
11 第1ランド部
12 第1半田
20 挿入部品
21 第2ランド部
21a 貫通孔
22 第2半田
DESCRIPTION OF SYMBOLS 1 Circuit board 2 Insulating board 4 Conductor part 5 Resist 6 Mask 6a Hole part 10 Chip component 11 1st land part 12 1st solder 20 Insertion part 21 2nd land part 21a Through-hole 22 2nd solder

Claims (4)

絶縁基板上に形成される導体部の一部を露出した第1、第2ランド部を設け、第1ランド部にチップ部品を半田付けするとともに貫通孔を有する第2ランド部に挿入部品を半田付けする回路基板の製造方法において、マスクにより所定位置を覆って第1、第2ランド部にペースト状の第1半田を塗布するリフロー半田工程と、第1ランド部に前記チップ部品を半田付けするチップ部品実装工程と、前記絶縁基板を半田槽に浸漬して第2半田を第2ランド部に設けるフロー半田工程と、前記貫通孔に挿入した前記挿入部品を第2ランド部に半田付けする挿入部品実装工程とを備えたことを特徴とする回路基板の製造方法。   Provided are first and second land portions exposing a part of the conductor portion formed on the insulating substrate, soldering the chip component to the first land portion, and soldering the insertion component to the second land portion having a through hole. In a method of manufacturing a circuit board to be attached, a reflow soldering process in which a predetermined position is covered with a mask and paste-like first solder is applied to first and second land portions, and the chip component is soldered to the first land portions. Chip component mounting step, flow soldering step of immersing the insulating substrate in a solder bath to provide second solder on the second land portion, and insertion for soldering the inserted component inserted into the through hole to the second land portion A circuit board manufacturing method comprising: a component mounting step. 前記マスクにより前記貫通孔を覆うことを特徴とする請求項1に記載の回路基板の製造方法。   The method for manufacturing a circuit board according to claim 1, wherein the through hole is covered with the mask. 前記絶縁基板の両面に第1ランド部を設けて前記チップ部品が実装されるとともに一方の面の第2ランド部に第2半田を設け、一方の面の前記リフロー半田工程を他方の面の前記チップ部品実装工程の前に行うことを特徴とする請求項1または請求項2に記載の回路基板の製造方法。   The first land portions are provided on both surfaces of the insulating substrate to mount the chip component, the second solder is provided on the second land portion on one surface, and the reflow soldering process on one surface is performed on the other surface. The method for manufacturing a circuit board according to claim 1 or 2, wherein the method is performed before the chip component mounting step. 絶縁基板上に第1ランド部と貫通孔を有する第2ランド部とが露出し、第1ランド部にペースト状の第1半田を塗布してチップ部品が半田付けされるとともに、前記絶縁基板を半田槽に浸漬することによって第2ランド部に第2半田を設けて挿入部品が半田付けされる回路基板において、第2ランド部に第1半田を塗布した後に第2半田を設けたことを特徴とする回路基板。   A first land portion and a second land portion having a through hole are exposed on the insulating substrate, and a paste-like first solder is applied to the first land portion to solder a chip component. In the circuit board in which the second solder is provided in the second land portion by being immersed in the solder bath and the insertion component is soldered, the second solder is provided after the first solder is applied to the second land portion. A circuit board.
JP2009059411A 2009-03-12 2009-03-12 Circuit board and method for manufacturing the same Pending JP2010212591A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014138065A (en) * 2013-01-16 2014-07-28 Senju Metal Ind Co Ltd Method of soldering printed board

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62136097A (en) * 1985-12-10 1987-06-19 松下電器産業株式会社 Method of attaching parts to printed wiring board
JPS63155689A (en) * 1986-12-18 1988-06-28 富士通株式会社 Method of solder-coating of printed board
JPH0357295A (en) * 1989-07-26 1991-03-12 Fujitsu Ltd Method of mounting electronic components on double-sided mounting board

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62136097A (en) * 1985-12-10 1987-06-19 松下電器産業株式会社 Method of attaching parts to printed wiring board
JPS63155689A (en) * 1986-12-18 1988-06-28 富士通株式会社 Method of solder-coating of printed board
JPH0357295A (en) * 1989-07-26 1991-03-12 Fujitsu Ltd Method of mounting electronic components on double-sided mounting board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014138065A (en) * 2013-01-16 2014-07-28 Senju Metal Ind Co Ltd Method of soldering printed board

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