JP2010200290A - Pulse width modulation circuit, and switching amplifier using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a pulse width modulation circuit that can output a normal PWM waveform even when the frequency of a clock signal is changed. <P>SOLUTION: A voltage switching circuit 36 switches a voltage from a voltage source 35 according to the frequency of a reference clock when the frequency of the reference clock is switched. A VI converter circuit 32 generates a current 2Ic (Ic is a DC bias current of a charging current Ij) based on the voltage from the voltage source 35, and a VI converter circuit 31 generates a discharging current Id (=2Ic) based on the voltage from the voltage source 35. Therefore, even when the frequency of the reference clock is switched and the charging time periods of capacitors C1 and C2 are changed, the maximum charging voltages of the capacitors C1 and C2 can be set at a half of a chargeable voltage, so that the normal PWM waveform can be outputted. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pulse width modulation circuit and a switching amplifier using the same.

  FIG. 9 is a block diagram showing a conventional pulse width modulation circuit (see Patent Document 1). The pulse width modulation circuit 901 charges the first capacitor C1 in the first period T1 of the clock signal MCLK based on the current Ic + Δi based on the audio signal eS, and the first capacitor C1 in the second period T2 based on the discharge current Id. And the second capacitor C2 is charged, and the voltage of the second capacitor C2 is discharged in the third period T3 based on the discharge current Id.

  The time from the start of the second period T2 until the voltage of the first capacitor C1 reaches the threshold voltage Vref is detected, and the voltage of the second capacitor C2 reaches the threshold voltage Vref after the start of the third period T3. Detect the time until The voltage of the first capacitor C1 is maintained until the third period T3 starts after the voltage of the first capacitor C1 reaches the threshold voltage Vref, and the second voltage after the voltage of the second capacitor C2 reaches the threshold voltage Vref. The voltage of the second capacitor C2 is maintained until the four period T4 is started. Based on the time until the voltages of the first and second capacitors C1 and C2 reach the threshold voltage Vref, a pulse signal having a pulse width of the time is generated.

  Here, the pulse width modulation circuit 901 is applied to an audio switching amplifier, but the switching amplifier amplifies the power of the pulse waveform, and in principle, an unnecessary radiation problem is likely to occur. An example is radio reception interference. One possible countermeasure is to switch the carrier frequency. In the above-described pulse width modulation circuit 901, the modulation carrier frequency is twice the frequency of the clock signal, so that the problem of unnecessary radiation can be solved by switching the frequency of the reference clock.

  However, if the frequency of the reference clock is changed, as shown in FIG. 10, the maximum charging voltage (voltage at the end of charging) of the first and second capacitors C1 and C2 that perform charging and discharging changes, and the following problems occur: Occurs. FIG. 10 is a diagram illustrating a charging voltage waveform of the first capacitor C1 when the frequency of the reference clock MCLK is changed. FIG. 10A illustrates a case where the reference clock MCLK is a second frequency that is a reference frequency. ) Shows the case where the reference clock MCLK is a first frequency which is lower than the reference frequency, and (c) shows the case where the reference clock MCLK is a third frequency which is higher than the reference frequency. Waveform (1) is when the audio signal eS is no signal, waveform (2) is when the amplitude value of the audio signal eS is positive, and waveform (3) is when the amplitude value of the audio signal eS is negative. Show the case. Further, the signal φ1 is synchronized with the reference clock, and when it is high level, the switch SW1 is turned on to charge the first capacitor C1, and when it is low level, the switch SW1 is turned off to not charge the first capacitor C1. It is.

  As shown in FIG. 10A, when the frequency of the reference clock MCLK is the second frequency (reference frequency), the maximum charging voltage Va of the first capacitor C1 when the audio signal eS is no signal is the first capacitor. The voltage is ½ of the chargeable voltage of C1 (that is, (VCC−Vref) / 2). Therefore, the voltage range that can be charged when the amplitude value is positive is the same as the voltage range that can be charged when the amplitude value is negative. That is, the amplitude value at which the charging voltage is clipped on the positive side and the amplitude value at which the charging voltage is clipped on the negative side are the same. As a result, even if the charging voltage is clipped, it is symmetrical on the positive side and the negative side, so that a normal PWM waveform can be output. That is, the distortion rate when a large signal is input can be reduced, and malfunction due to positive and negative unbalanced clips can be prevented.

  Next, as shown in FIG. 10B, when the frequency of the reference clock MCLK is the first frequency (low frequency), the charging time for the first capacitor C1 becomes long, so that the audio signal eS is a non-signal. In this case, the maximum charging voltage Va of the first capacitor C1 is larger than ½ (that is, (VCC−Vref) / 2) of the chargeable voltage of the first capacitor C1. Therefore, the voltage range that can be charged when the amplitude value is positive is smaller than the voltage range that can be charged when the amplitude value is negative, and the amplitude value that the charging voltage clips on the positive side is negative. The charging voltage becomes smaller than the clipping amplitude value. As a result, when the amplitude value of the audio signal eS is positive and large, the charging voltage is limited and clipped. However, when the amplitude value of the audio signal eS is negative and large, the charging voltage is not clipped and the audio signal eS is clipped. The PWM waveform becomes unbalanced between the case where the amplitude value of the signal eS is positive and the case where it is negative, and a normal PWM waveform cannot be output.

  Next, as shown in FIG. 10C, when the frequency of the reference clock MCLK is the third frequency (high frequency), the charging time for the first capacitor C1 is shortened, so that the audio signal eS is a non-signal. In this case, the maximum charging voltage Va of the first capacitor C1 is smaller than ½ of the chargeable voltage of the first capacitor C1 (that is, (VCC−Vref) / 2). Therefore, the voltage range that can be charged when the amplitude value is positive is larger than the voltage range that can be charged when the amplitude value is negative, and the amplitude value that the charging voltage clips on the positive side is negative. The charging voltage becomes larger than the amplitude value to be clipped. As a result, when the amplitude value of the audio signal eS is positive and large, the charging voltage is not clipped. However, when the amplitude value of the audio signal eS is negative and large, the charging voltage is limited and clipped. The PWM waveform becomes unbalanced depending on whether the amplitude value of eS is positive or negative, and a normal PWM waveform cannot be output.

JP 2008-206128 A

  The present invention has been made to solve the above-described problems, and an object of the present invention is to output a normal PWM waveform even when the frequency of the clock signal is changed in the pulse width modulation circuit. It is to provide a pulse width modulation circuit that can.

  A pulse width modulation circuit according to a preferred embodiment of the present invention has a first charge accumulation unit that accumulates charges, a second charge accumulation unit that accumulates charges, and a current value that changes according to the amplitude of an input AC voltage. Current generating means for generating a first current and generating a second current; and a voltage in the first charge storage means in a first period which is a half cycle of a clock signal based on the first current. Based on the second current, the voltage in the first charge storage means is opposite to the increase / decrease direction in the first period in the second period following the first period shifted from the first period by a half cycle. And the voltage in the second charge storage means is changed based on the first current, and the second period following the second period shifted from the second period by a half cycle based on the second current. In 3 periods Voltage control means for changing the voltage in the second charge storage means in the direction opposite to the increase / decrease direction in the second period, and the voltage in the first charge storage means reaches the threshold voltage after the second period is started. First detection means for detecting a time until the second detection means, second detection means for detecting a time from when the third period starts until the voltage in the second charge storage means reaches the threshold voltage, A pulse signal generating means for generating a pulse signal having a pulse width of the time based on a time alternately output from the first detecting means and the second detecting means every half cycle of the clock signal; and the clock Frequency control means for switching the frequency of the signal to one frequency selected from a plurality of frequencies, wherein the current generation means includes a voltage source for supplying a voltage, The voltage switching means for switching the voltage supplied by the voltage source according to the frequency of the clock signal selected by the frequency control means, the voltage supplied from the voltage source, and the first voltage based on the AC voltage. First current generating means for generating current and second current generating means for generating the second current based on the voltage supplied from the voltage source.

  The voltage switching means switches the voltage supplied by the voltage source according to the frequency of the clock signal when the frequency of the clock signal is switched. The first current generation unit generates a first current based on the voltage from the voltage source, and the second current generation unit generates a second current based on the voltage from the same voltage source. The maximum charge voltage of the first charge storage means and the second charge storage means can be charged even when the frequency of the first clock signal is switched and the charging time of the first charge storage means and the second charge storage means changes. The voltage can be set to ½ of the voltage. As a result, the voltage range that can be charged when the amplitude value is positive can be made the same as the voltage range that can be charged when the amplitude value is negative, and the amplitude value that the charging voltage clips on the positive side The amplitude value at which the charging voltage is clipped on the negative side can be made the same. As a result, even if the voltage is clipped, it is symmetrical between the positive side and the negative side, so that a normal PWM waveform can be output. In addition, since the first current generation unit and the second current generation unit generate the first current and the second current from the voltage of the same voltage source, the voltage switching unit only switches the voltage of the voltage source. Both the current and the second current can be changed, and the circuit configuration can be simplified.

  In a preferred embodiment, when the frequency of the clock signal is switched to a frequency lower than the current frequency, the voltage switching means is configured so that the first current and the second current are smaller than the current current. , When the voltage from the voltage source is switched to be lower than the current voltage and the frequency of the clock signal is switched to a frequency higher than the current frequency, the first current and the second current are The voltage switching means switches so that the voltage from the voltage source becomes larger than the current voltage so as to be larger than the current.

  When the frequency of the clock signal is switched to a low frequency and the charging time of the first charge storage means and the second charge storage means becomes long, the first current and the second current are reduced, so the first charge The slope of the voltage change of the storage means and the second charge storage means becomes gradual, and the maximum charge voltage of the first charge storage means and the second charge storage means can be set to ½ of the chargeable voltage. On the other hand, when the frequency of the clock signal is switched to a high frequency and the charging time of the first charge storage means and the second charge storage means is shortened, the first current and the second current are increased. The slope of the voltage change of the charge storage means and the second charge storage means becomes steep, and the maximum charge voltage of the first charge storage means and the second charge storage means can be set to ½ of the chargeable voltage. .

  In a preferred embodiment, the first current generating unit generates a third current having the same current value as the second current based on the voltage supplied from the voltage source, and A differential circuit that generates a fourth current obtained by adding a current based on the AC voltage to a current that is ½ of the third current, and the first current that has the same current value as the fourth current. A current mirror circuit to be generated.

  Even when the current values of the first current and the second current are changed by switching the frequency of the clock signal, the ratio of the direct current bias current to the second current of the first current is always 1: 2. Can be maintained.

In a preferred embodiment, when the voltage switching means includes a plurality of switch elements that switch connection or disconnection of a resistance element included in the voltage source to or from the voltage source, and the number of the switch elements is n, Except for the case where all the switch elements are turned off, the voltage is switched to any one of 2 ⁿ −1 voltages depending on the frequency of the clock signal.

only comprises a set of the n-number of switching elements and the resistance element, it is possible to generate a first current and a second current pattern of 2 n ^-1, the frequency of the 2 n ^-1 pattern of the clock signal On the other hand, the maximum charge voltage of the first charge storage means and the second charge storage means can be set to ½ of the chargeable voltage. Therefore, it is possible to reduce the number of circuit components and the cost.

  In a preferred embodiment, a charging start voltage in the first charge storage unit and the second charge storage unit is the threshold voltage Vref, and a chargeable voltage in the first charge storage unit and the second charge storage unit When the upper limit is the power supply voltage VCC and the frequency of the clock signal is switched to any frequency, the first charge storage means and the second charge storage when the amplitude of the AC voltage is zero The voltage supplied by the voltage source switched by the voltage switching means is determined so that the maximum charging voltage Va of the means becomes (VCC-Vref) / 2.

  The range of voltages that can be charged when the amplitude value is positive is the same as the range of voltages that can be charged when the amplitude value is negative, and the amplitude value that the charging voltage clips on the positive side and the charging voltage on the negative side Can be made the same as the amplitude value to be clipped. As a result, even if the voltage is clipped, it is symmetrical between the positive side and the negative side, so that a normal PWM waveform can be output.

  A switching amplifier according to a preferred embodiment of the present invention includes any one of the pulse width modulation circuits described above and a switching circuit that switches a power supply voltage based on a modulation signal output from the pulse width modulation circuit.

  Even when the frequency of the clock signal is changed, a normal PWM waveform can be output.

1 is a block diagram illustrating a switching amplifier to which a pulse width modulation circuit according to a preferred embodiment of the present invention is applied. 1 is a block diagram illustrating a pulse width modulation circuit according to a preferred embodiment of the present invention. It is a circuit diagram which shows a current generation circuit. It is a circuit diagram which shows another electric current generation circuit. It is a circuit diagram which shows another electric current generation circuit. It is a circuit diagram which shows another electric current generation circuit. It is a table | surface which shows the relationship between the frequency of a reference clock, and the state of a current generation circuit. It is a figure which shows the time chart which shows operation | movement when the amplitude of an audio signal is 0. It is a figure which shows the time chart which shows operation | movement when the amplitude of an audio signal is positive. It is a time chart which shows the voltage waveform of a capacitor in case a reference clock is a reference frequency. It is a time chart which shows the voltage waveform of a capacitor when a reference clock is a low frequency. It is a time chart which shows the voltage waveform of a capacitor when a reference clock is a high frequency. It is a block diagram which shows the pulse width modulation circuit by other embodiment. It is a block diagram which shows the conventional pulse width modulation circuit. It is a time chart which shows the voltage waveform of the capacitor | condenser in the conventional pulse width modulation circuit.

  FIG. 1 is a configuration diagram illustrating a switching amplifier to which a pulse width modulation (PWM) circuit according to a preferred embodiment of the present invention is applied. FIG. 2 is a block circuit diagram showing the pulse width modulation circuit shown in FIG.

[Configuration of switching amplifier]
The switching amplifier includes a pulse width modulation circuit 1 connected to the audio signal generation source AU, a switching circuit 2, a low-pass filter circuit 3, a first power supply 4 that supplies positive and negative power supply voltages + EB and -EB, and a second power supply. And 5. A speaker (not shown) as a load RL is connected to the output of the low-pass filter circuit 3.

  The pulse width modulation circuit 1 converts the audio signal eS as an input signal output from the audio signal generation source AU into a pulse width modulation signal PWMout and outputs it. The pulse width modulation signal PWMout output from the pulse width modulation circuit 1 is input to the switching circuit 2.

  The switching circuit 2 includes a switch element SW-A whose on / off operation is controlled by the pulse width modulation signal PWMout, an inverter 2a for inverting the phase of the pulse width modulation signal PWMout output from the pulse width modulation circuit 1, and The switch element SW-B whose on / off operation is controlled by the pulse width modulation signal PWMout ′ whose phase is inverted output from the inverter 2a is connected to both ends of the switch elements SW-A and SW-B. Reverse-current preventing diodes DA and DB are provided.

  In the switching circuit 2, positive and negative power supply voltages + EB and -EB are supplied from the first power supply 4 and the second power supply 5 to the load RL via the switch element SW-A and the switch element SW-B, respectively. Since the SW-A and the switch element SW-B are alternately turned on and off by the pulse width modulation signal PWMout and the pulse width modulation signal PWMout ′, respectively, the power supply voltage + EB is applied to the low-pass filter circuit 3 and the load RL. The power supply voltage -EB is supplied alternately. That is, the load RL is supplied with a rectangular wave voltage having the same duty ratio as that of the pulse width modulation signal PWMout through the low-pass filter circuit 3 while the level changes between + EB and -EB.

  The low-pass filter circuit 3 is configured by an LC circuit including a coil L0 and a capacitor C0. The low-pass filter circuit 3 is a circuit that removes a high-frequency component of the rectangular wave voltage input from the switching circuit 2 and has a cutoff frequency of 60 kHz, for example. The low-pass filter circuit 3 outputs an AC voltage signal (AC voltage signal having substantially the same waveform as that of the audio signal eS) obtained by demodulating the pulse width modulation signal PWMout, and the AC signal is supplied to the load RL. Is output as audio.

[Configuration of pulse width modulation circuit]
As shown in FIG. 2, the pulse width modulation circuit 1 includes a clock frequency control unit 10, a reference clock generation circuit 11, a dead time generation circuit 12, a falling edge detection circuit 13, and a charge current / discharge current generation circuit. (Hereinafter referred to as a current generation circuit) 14, first to fourth switches SW1 to SW4, first and second capacitors C1 and C2, a current bypass circuit 16, first and second RS flip-flop circuits 17, 18 and a signal output circuit 19.

The pulse width modulation circuit 1
(1) The charging current Ij for charging the first and second capacitors C1 and C2 is generated by the current generating circuit 14 from the audio signal eS input from the outside.
(2) Of the one cycle of the reference clock MCLK, for example, the first half cycle of the first capacitor C1 is a charging period, the latter half cycle is a discharging period, and the first half cycle of the second capacitor C2 is a discharging period. When the second half cycle is a charging period, the first and second capacitors C1 and C2 are charged with the charging current Ij in each charging period, and the accumulated charges of the first and second capacitors C1 and C2 are discharged in each discharging period. Discharge with current Id.
(3) For each discharge period of the first and second capacitors C1 and C2, from the start of discharge (at the end of charging) until the voltage of the first and second capacitors C1 and C2 changes to a predetermined threshold voltage Vref. Pulse signals having the same pulse width as the discharge time are generated.
(4) A pulse width modulation signal PWMout is generated by synthesizing pulse signals generated alternately every half cycle of the reference clock MCLK.
The audio signal eS is converted into the pulse width modulation signal PWMout by the operation principle described above.

  The reference clock generation circuit 11 is a circuit that generates the reference clock MCLK. The reference clock MCLK is a clock signal having a constant cycle and a duty ratio of approximately 50%, and first and second switching signals φ1 and φ2 for controlling on / off operations of the first and second switches SW1 and SW2. This is the reference signal. The reference clock MCLK is also a reference signal that defines the period of the pulse width modulation signal PWMout. The reference clock generation circuit 11 outputs the reference clock MCLK to the dead time generation circuit 12. The reference clock generation circuit 11 may be provided outside the pulse width modulation circuit 1 and configured to supply the reference clock MCLK to the pulse width modulation circuit 1 as an external clock signal.

  The clock frequency control unit 10 controls the reference clock generation circuit 11 to change the frequency of the reference clock MCLK. The clock frequency control unit 10 changes the frequency of the reference clock MCLK from the second frequency that is the reference frequency to the first frequency that is lower than the second frequency or the third frequency that is higher than the second frequency. The reference clock generation circuit 11 is controlled to change to As a result, the reference clock generation circuit 11 outputs the reference clock MCLK whose frequency is changed according to the control signal from the clock frequency control unit 10. Note that the frequency of the reference clock MCLK may be switched to four or more frequencies.

  Further, the clock frequency control unit 10 outputs the fifth switching signal φ5 and the sixth switching signal φ6 to the current generation circuit 14. The fifth switching signal φ5 and the sixth switching signal φ6 control the current generation circuit 14 so as to change the charging current Ij and the discharging current Id when the frequency of the reference clock MCLK is switched from the first frequency to the third frequency. Signal.

  The dead time generation circuit 12 is a circuit that generates the first switching signal φ1 and the second switching signal φ2 based on the reference clock MCLK from the reference clock generation circuit 11. The second switching signal φ2 has an opposite phase relationship to the first switching signal φ1, but the falling timing and rising timing of the second switching signal φ2 coincide with the rising timing and falling timing of the first switching signal φ1, respectively. As a result, the level inversion timing of the second switching signal φ2 is shifted by a predetermined time ΔT (dead time) with respect to the level inversion timing of the first switching signal φ1.

  That is, as shown in FIGS. 5A and 5B, the first switching signal φ1 changes from the low level to the high level after a predetermined period ΔT from the time when the reference clock MCLK is inverted from the low level to the high level. The signal is inverted, and the reference clock MCLK is inverted from the high level to the low level, and at the same time is inverted from the high level to the low level. On the other hand, as shown in FIGS. 5A and 5C, the second switching signal φ2 is inverted from the high level to the low level at the same time as the reference clock MCLK is inverted from the low level to the high level. This signal is inverted from the low level to the high level after a predetermined period ΔT from when the high level is inverted to the low level.

  By providing a dead time between the first switching signal φ1 and the second switching signal φ2, as shown in FIGS. 5B and 5C, the high level inversion and the second switching of the first switching signal φ1 are performed. Since the low level inversion of the signal φ2 does not occur at the same time and the low level inversion of the first switching signal φ1 and the high level inversion of the second switching signal φ2 do not occur at the same time, the first switch SW1 is turned on by the first switching signal φ1. When switching from the off state to the on state (when the node supplying the charging current Ij of the current generation circuit 14 is connected to the first capacitor C1), the second switch SW2 is already switched to the off state by the second switching signal φ2. (The node supplying the charging current Ij of the current generation circuit 14 is already disconnected from the second capacitor C2) and supplies the charging current Ij of the current generation circuit 14 Are not simultaneously connected to the first and second capacitors C1 and C2. Also, when the second switch SW2 is switched from the off state to the on state by the second switching signal φ2 (when the node supplying the charging current Ij of the current generation circuit 14 is connected to the second capacitor C2), the first switch SW1 has already been switched to the OFF state by the first switching signal φ1 (the node supplying the charging current Ij of the current generation circuit 14 has already been disconnected from the first capacitor C1), and the charging current Ij of the current generation circuit 14 Are not simultaneously connected to the first and second capacitors C1 and C2.

  As a result, the charging current Ij supplied from the current generation circuit 14 to the first capacitor C1 during the charging of the first capacitor C1 is also supplied to the second capacitor C2, and conversely the current during the charging of the second capacitor C2. Since the charging current Ij supplied from the generation circuit 14 to the second capacitor C2 is not supplied to the first capacitor C1, the pulse signals output from the first and second RS flip-flop circuits 17 and 18, respectively. It is possible to prevent an inconvenience that an error occurs in the pulse width of the signal and, as a result, an error occurs in the pulse width of the pulse width modulation signal PWMout. The first and second switching signals φ1 and φ2 are output to the first and second switches SW1 and SW2, respectively, and also output to the falling edge detection circuit 13.

  Note that the dead time provided in the dead time generation circuit 12 is extremely small, and the first switch SW1 is substantially controlled to be turned on and off by the reference clock MCLK, and the second switch SW2 inverts the phase of the reference clock MCLK. It can be said that ON / OFF is controlled by the clock.

  The falling edge detection circuit 13 is a circuit that outputs first and second set signals set1 and set2 supplied to first and second RS flip-flop circuits 17 and 18, which will be described later. That is, the falling edge detection circuit 13 detects the timing at which the first switching signal φ1 falls from the high level to the low level, and as shown in FIG. 5D, the signal that falls to the low level for a moment at the detection timing. Is output to the first RS flip-flop circuit 17 as the first set signal set1. Further, the falling edge detection circuit 13 detects the timing at which the second switching signal φ2 falls from the high level to the low level, and as shown in FIG. 5 (e), the signal that falls to the low level for a moment at the detection timing. Is output to the second RS flip-flop circuit 18 as the second set signal set2.

  The current generation circuit 14 performs voltage-current conversion on the audio signal eS supplied from the audio signal generation source AU (see FIG. 3) to the pulse width modulation circuit 1 and charges the converted current Δi with the DC bias current Ic. It is a circuit that generates a current Ij. The node that outputs the charging current Ij of the current generation circuit 14 is connected to the first and second capacitors C1 and C2 via the first and second switches SW1 and SW2, respectively. When the first switch SW1 is in the on state, The first capacitor C1 is connected to the first capacitor C1 and charged with the charging current Ij. When the second switch SW2 is in the ON state, the second capacitor C2 is connected to charge the second capacitor C2 with the charging current Ij.

  The current generation circuit 14 generates a discharge current Id, and discharges the accumulated charges of the first and second capacitors C1 and C2 with the discharge current Id. That is, the node from which the discharge current Id of the current generation circuit 14 is output is connected to the first and second capacitors C1 and C2 via the third and fourth switches SW3 and SW4, respectively, and the third switch SW3 is When the first capacitor C1 is turned on and connected to the first capacitor C1, the charge accumulated in the first capacitor C1 is discharged by the discharge current Id. When the fourth switch SW4 is turned on and connected to the second capacitor C2, the second capacitor C2 is turned on. The accumulated charge in the capacitor C2 is discharged with the discharge current Id. Details of the current generation circuit 14 will be described later.

  The current bypass circuit 16 includes a diode D2 and a voltage source 23. The current bypass circuit 16 discharges even when the node that outputs the discharge current Id of the current generation circuit 14 is not electrically connected to the first and second capacitors C1 and C2 by the third and fourth switches SW3 and SW4. This is for flowing the current Id. That is, when the node that outputs the discharge current Id of the current generation circuit 14 is not electrically connected to the first and second capacitors C1 and C2 by the third and fourth switches SW3 and SW4, the diode D2 is turned on. The voltage source 23 is connected to the node that outputs the discharge current Id of the current generation circuit 14.

  In this state, for example, when the third switch SW3 is turned on and the first capacitor C1 is connected to the node that outputs the discharge current Id of the current generation circuit 14, the voltage of the first capacitor C1 is the cathode side of the diode D2. Therefore, the diode D2 is turned off, and the path through which the discharge current Id flows is switched from the voltage source 23 to the first capacitor C1. That is, at the same time as the third switch SW3 is turned on, the discharge operation with the discharge current Id of the charge accumulated in the first capacitor C1 is started. The same operation is performed when the fourth switch SW4 is turned on, and at the same time when the fourth switch SW4 is turned on, the discharge operation with the discharge current Id of the charge accumulated in the second capacitor C2 is started.

  The first and second switches SW1 and SW2 are switches for controlling the charging operation by the charging current Ij from the current generation circuit 14 of the first and second capacitors C1 and C2. One end of the first switch SW1 is connected to a node that outputs the charging current Ij of the current generation circuit 14, and the other end of the first switch SW1 is connected to one end of the first capacitor C1 (see point A in FIG. 2). Yes. When the first switch SW1 is turned on (closed), a charging path for the first capacitor C1 is formed. Further, one end of the second switch SW2 is also connected to a node that outputs the charging current Ij of the current generation circuit 14, and the other end of the second switch SW2 is connected to one end of the second capacitor C2 (see point A ′ in FIG. 2). It is connected. When the second switch SW2 is turned on (closed), a charging path for the second capacitor C2 is formed.

  The first and second switches SW1 and SW2 are turned on and off by first and second switching signals φ1 and φ2 output from the dead time generation circuit 12. That is, as shown in FIG. 5B, the first switch SW1 is turned on when the first switching signal φ1 is at a high level, and is turned off when the first switching signal φ1 is at a low level. Further, as shown in FIG. 5C, the second switch SW2 is turned on when the second switching signal φ2 is at a high level, and is turned off when the second switching signal φ2 is at a low level.

  The third and fourth switches SW3 and SW4 are switches for controlling the discharge operation by the discharge current Id from the current generation circuit 14 of the first and second capacitors C1 and C2. One end of the third switch SW3 is connected to a node that outputs the discharge current Id of the current generation circuit 14, and the other end of the third switch SW3 is connected to one end of the first capacitor C1 (see point A in FIG. 2). Yes. When the third switch SW3 is turned on (becomes closed), a discharge path for the first capacitor C1 is formed. Further, one end of the fourth switch SW4 is also connected to a node that outputs the discharge current Id of the current generation circuit 14, and the other end of the fourth switch SW4 is connected to one end of the second capacitor C2 (see point A ′ in FIG. 2). It is connected. When the fourth switch SW4 is turned on (becomes closed), a discharge path for the second capacitor C2 is formed.

  The third and fourth switches SW3 and SW4 are turned on and off by third and fourth switching signals φ3 and φ4 from first and second RS flip-flop circuits 17 and 18, which will be described later. That is, as shown in FIG. 5H, the third switch SW3 is turned on when the third switching signal φ3 is at a high level, and is turned off when it is at a low level. Further, as shown in FIG. 5I, the fourth switch SW4 is turned on when the fourth switching signal φ4 is at a high level, and is turned off when it is at a low level.

  The first and second capacitors C1 and C2 are for generating time according to the amplitude (instantaneous voltage value) of the audio signal eS. Specifically, the first capacitor C1 generates a current when the first switch SW1 is turned on (the third switch SW3 is turned off at this time) during the on period (a certain period) of the first switching signal φ1. By charging with a charging current Ij (= Ic ± Δi, current corresponding to the amplitude (instantaneous voltage value) of the audio signal eS) from the circuit 14, a voltage corresponding to the amplitude of the audio signal eS from the threshold voltage Vref (charging end) Voltage). After the charging operation is completed, the third switch SW3 is turned on (at this time, the first switch SW1 is turned off), so that the accumulated charge is discharged with a constant discharge current Id. In this discharge operation, the discharge time until the voltage of the first capacitor C1 drops from the charge end voltage to the predetermined threshold voltage Vref is generated as a time corresponding to the amplitude (instantaneous voltage value) of the audio signal eS.

  The predetermined threshold voltage Vref is a logic level threshold voltage in the first and second RS flip-flop circuits 17 and 18, and is approximately 1 / V of the power supply voltage + Vcc supplied to the first and second RS flip-flop circuits 17 and 18. 2 voltage. For example, if the drive voltage of the first and second RS flip-flop circuits 17 and 18 is +5 [v], the threshold voltage Vref is approximately +2.5 [v].

  The second capacitor C2 is charged from the current generation circuit 14 when the second switch SW2 is turned on (the fourth switch SW4 is turned off at this time) during the on period (a certain period) of the second switching signal φ2. By charging with the current Ij, the charge start voltage Vref is raised to a voltage (charge end voltage) corresponding to the amplitude of the audio signal eS. After the charging operation is completed, the fourth switch SW4 is turned on (at this time, the second switch SW2 is turned off), so that the accumulated charge is discharged with a constant discharge current Id. In this discharge operation, a discharge time until the voltage of the second capacitor C2 decreases from the charge end voltage to the predetermined threshold voltage Vref is generated as a time corresponding to the amplitude (instantaneous voltage value) of the audio signal eS.

  The first RS flip-flop circuit 17 generates a pulse signal having the same pulse width as the discharge time of the first capacitor C1 during each discharge period of the first capacitor C1, and also generates a third switching signal φ3. is there.

  The first RS flip-flop circuit 17 is an RS flip-flop circuit configured by two NAND gates (first NAND circuit NA1 and second NAND circuit NA2). The voltage of the first capacitor C1 is input to the first NAND circuit NA1 as the first reset signal res1, and the output rsout1 is output from the first NAND circuit NA1. The first set signal set1 (a signal that instantaneously falls to a level lower than the threshold voltage Vref) output from the falling edge detection circuit 13 is input to the second NAND circuit NA2, and the third NAND circuit NA2 to the third A switching signal φ3 is output.

  When the first set signal set1 is input, the first RS flip-flop circuit 17 inverts the output rsout1 and the third switching signal φ3 to high level, and the voltage of the first capacitor C1 is low level (threshold voltage Vref or lower). In other words, when the first reset signal res1 is input, the output rsout1 is inverted to the high level and the third switching signal φ3 is inverted to the low level. Since the input timing of the first set signal set1 corresponds to the discharge start timing of the first capacitor C1, and the input timing of the first reset signal res1 is the timing when the voltage of the first capacitor C1 is reduced to the threshold voltage Vref, the output rsout1 The low level period corresponds to the discharge time of the first capacitor C1.

  Therefore, from the output terminal of the first NAND circuit NA1 of the first RS flip-flop circuit 17, a pulse signal having the same pulse width as the discharge time of the first capacitor C1 is output as an output rsout1 during each discharge period of the first capacitor C1. Is done.

  The second RS flip-flop circuit 18 generates a pulse signal having the same pulse width as the discharge time of the second capacitor C2 during each discharge period of the second capacitor C2, and generates a fourth switching signal φ4. is there.

  Similarly to the first RS flip-flop circuit 17, the second RS flip-flop circuit 18 is also an RS flip-flop circuit configured by two NAND gates (a third NAND circuit NA3 and a fourth NAND circuit NA4). The voltage of the second capacitor C2 is input to the third NAND circuit NA3 as the second reset signal res2, and the output rsout2 is output from the third NAND circuit NA3. The second set signal set2 (a signal that instantaneously falls to a level lower than the threshold voltage Vref) output from the falling edge detection circuit 13 is input to the fourth NAND circuit NA4, and the fourth NAND circuit NA4 to the fourth A switching signal φ4 is output.

  When the second set signal set2 is input, the second RS flip-flop circuit 18 inverts the output rsout2 to the low level and the fourth switching signal φ4 to the high level, and the voltage of the second capacitor C2 is the low level (threshold voltage Vref or lower). In other words, when the second reset signal res2 is input, the output rsout2 is inverted to the high level and the fourth switching signal φ4 is inverted to the low level. Since the input timing of the second set signal set2 corresponds to the discharge start timing of the second capacitor C2, and the input timing of the second reset signal res2 is the timing when the voltage of the second capacitor C2 is reduced to the threshold voltage Vref, the output rsout2 The low level period corresponds to the discharge time of the second capacitor C2.

  Accordingly, a pulse signal having the same pulse width as the discharge time of the second capacitor C2 is output as an output rsout2 during each discharge period of the second capacitor C2 from the output terminal of the third NAND circuit NA3 of the second RS flip-flop circuit 18. Is done.

  The signal output circuit 19 is a circuit that combines the output rsout1 output from the first RS flip-flop circuit 17 and the output rsout2 output from the second RS flip-flop circuit 18. The signal output circuit 19 includes a NAND gate (fifth NAND circuit NA5). The output rsout1 is a signal that generates a pulse signal (a pulse signal having the same pulse width as the discharge time of the first capacitor C1) only during the low level period of the reference clock MCLK, while the output rsout2 is the high level of the reference clock MCLK. Since the pulse signal (the pulse signal having the same pulse width as the discharge time of the second capacitor C2) is generated only during the period, the signal output circuit 19 outputs the pulse signal of the output rsout1 and the pulse signal of the output rsout2. Is a pulse signal (a pulse train signal having a pulse width corresponding to the amplitude (instantaneous voltage value) of eS of the audio signal in the same cycle as the half cycle of the reference clock MCLK) as the pulse width modulation signal PMWout. Is output.

[Operation of pulse width modulation circuit]
Next, the operation of the pulse width modulation circuit 1 will be described using the time charts of FIGS. FIG. 5 is a time chart when the amplitude of the audio signal is 0 (that is, charging current Ij = DC bias current Ic).

  A high level period and a low level period of the first switching signal φ1 are a charging period and a discharging period of the first capacitor C1, respectively. When the first switching signal φ1 is inverted to the high level, the first switch SW1 connects the output node of the charging current Ij of the current generation circuit 14 to the first capacitor C1, and the first capacitor by the charging current Ij from the current generation circuit 14 is connected. Charging of C1 is started. The charging operation is continued until the first switching signal φ1 is inverted to the low level and the first switch SW1 disconnects the current generation circuit 14 (see FIGS. 5B and 5F).

  When the first switching signal φ1 is inverted to a low level and shifts to the discharge period, the third switching signal φ3 output from the first RS flip-flop circuit 17 is set to a high level by the first set signal set1 that detects the low level inversion. As a result, the third switch SW3 connects the output node of the discharge current Id of the current generation circuit 14 to the first capacitor C1, and the discharge of the first capacitor C1 by the discharge current Id from the current generation circuit 14 is started. . The discharging operation continues until the voltage of the first capacitor C1 drops to the threshold voltage Vref, whereby the third switching signal φ3 is inverted to a low level and the third switch SW3 disconnects the current generating circuit 14 (FIG. 5). (See (b), (d), (f)).

  During the discharging period, the first set signal set1 is input from the first RS flip-flop circuit 17 and at the same time the level is inverted to a low level, and the voltage of the first capacitor C1 input as the first reset signal res1 decreases to the threshold voltage Vref. At the same time, a pulse signal that is inverted to a high level is output as an output rsout1. That is, a pulse signal having a pulse width corresponding to the amplitude of the audio signal eS is generated (see (j) in FIG. 5).

  Further, the high-level period and the low-level period of the second switching signal φ2 are a charging period and a discharging period of the second capacitor C2, respectively. If the dead time is ignored, the second switching signal φ2 is a signal obtained by inverting the phase of the first switching signal φ1, so that the second capacitor C2 is similar to the charge / discharge operation in the first capacitor C1 described above. The charging / discharging operation is performed while being shifted by a half cycle of the first switching signal φ1 (see (c), (e), (g), (i) in FIG. 5).

  Therefore, during the discharge period of the second capacitor C2, the second set signal set2 is input from the second RS flip-flop circuit 18 and at the same time inverted to a low level, and the second capacitor C2 input as the second reset signal res2 A pulse signal that is inverted to a high level at the same time as the voltage drops to the threshold voltage Vref is output as the output rsout2. That is, a pulse signal having a pulse width corresponding to the amplitude of the audio signal eS is generated (see (k) in FIG. 5).

  The output rsout1 and the output rsout2 output from the first and second flip-flop circuits 17 and 18 are synthesized by the signal output circuit 19 to be a pulse width modulation signal PWMout (a signal obtained by synthesizing the waveform of the output rsout1 and the waveform of the output rsout2). (See (l) of FIG. 5).

  As shown in FIG. 6, when the amplitude of the audio signal eS is positive, the magnitude of the charging current Ij = Ic + Δi is large, and the slope of the charging voltage waveform at one end of the first and second capacitors C1 and C2 is increased. Also, the amplitude of the audio signal eS becomes larger than when the amplitude is zero. Therefore, the terminal voltage of the first and second capacitors C1 and C2 at the time when the level of the first or second switching signal φ1 or φ2 is inverted from the high level to the low level is higher than that when the audio signal eS is no signal. When these are discharged by the discharge current Id, the time to reach the threshold voltage Vref after the start of discharge becomes longer than when the audio signal eS is no signal. Therefore, as shown in FIG. 6 (l), the pulse width modulation signal PWMout having a long high level time is output compared to the case where the audio signal eS shown in FIG. Thus, the pulse width modulation signal PWMout corresponding to the amplitude of the audio signal eS is output.

  Although not shown, similarly, when the audio signal eS is negative, the magnitude of the charging current Ij = Ic + Δi is small, and the slope of the charging voltage waveform at one end of the first and second capacitors C1, C2 is also small. . Therefore, the terminal voltage of the first and second capacitors C1 and C2 at the time when the level of the first or second switching signal φ1 or φ2 is inverted from the high level to the low level is higher than that when the audio signal eS is no signal. When these are discharged by the discharge current Id, the time to reach the threshold voltage Vref after the start of discharge becomes shorter than when the audio signal eS is no signal. Accordingly, the pulse width modulation signal PWMout is output with a shorter high level time than when the audio signal eS is not a signal.

[Configuration of Current Generation Circuit 14]
FIG. 3 is a circuit diagram showing the current generation circuit 14. The current generation circuit 14 includes voltage-current conversion circuits (hereinafter referred to as VI conversion circuits) 31 and 32, a differential circuit 33, a current mirror circuit 34, a voltage source 35, and a voltage switching circuit 36. Yes. The VI conversion circuit 31 constitutes a discharge current generation circuit, and the VI conversion circuit 32, the differential circuit 33, and the current mirror circuit 34 constitute a charging current generation circuit.

  The current generation circuit 14 generates a discharge current Id and a DC bias current Ic of the charging current Ij based on the voltage Vb generated by the common voltage source 35. Further, the current generation circuit 14 changes the voltage Vb generated by the voltage source 35 in accordance with the fifth switching signal φ5 and the sixth switching signal φ6 from the clock frequency control unit 10. As a result, the DC bias current Ic of the charging current Ij and the discharging current Id vary at the same ratio.

  When the frequency of the reference clock MCLK is changed to a low frequency (that is, from the third frequency toward the first frequency), the voltage Vb of the voltage source 35 is decreased, and the current values of the DC bias current Ic and the discharge current Id are reduced. Will be reduced. Therefore, the voltage change amount of the first capacitor C1 and the second capacitor C2 decreases. On the other hand, when the frequency of the reference clock MCLK is changed to a high frequency (that is, from the first frequency to the third frequency), the voltage Vb of the voltage source 35 is increased, and the DC bias current Ic and the discharge current Id are currents. The value is increased. Therefore, the voltage change amount of the first capacitor C1 and the second capacitor C2 increases. As a result, the maximum charge voltage (voltage at the end of charging) of the first capacitor C1 and the second capacitor C2 when the audio signal is no signal (no modulation) is always set to the chargeable voltage regardless of the frequency of the reference clock MCLK. The voltage can be set to 1/2 of the voltage (VCC-Vref) / 2.

  Even when the amounts of the DC bias current Ic and the discharge current Id are changed, the ratio of the current values of the DC bias current Ic and the discharge current Id is always a constant ratio (for example, Ic: Id = 1: 2). Maintained.

  The VI conversion circuit 31 is supplied with the voltage Vb from the voltage source 35, and generates a discharge current Id by converting the voltage Vb into voltage-current. The VI conversion circuit 31 includes a transistor Q1 and a resistor R1. The transistor Q1 has a base connected to the output terminal of the voltage source 35, an emitter connected to the negative power supply line V2 via the resistor R1, and a collector serving as a node that outputs the discharge current Id. In other words, the collector of the transistor Q1 is connected to the first capacitor C1 through the third switch SW3, and is connected to the second capacitor C2 through the fourth switch SW4.

The current Id generated by the VI conversion circuit 31 is represented by the following formula 1. VBE is a base-emitter voltage (conduction start voltage) of the transistor Q1.

  The VI conversion circuit 32 is supplied with the voltage Vb from the voltage source 35, and generates a reference current 2Ic by converting the voltage Vb into voltage-current. The reference current 2Ic is a current that serves as a reference for the discharge current Id and the DC bias current Ic. The VI conversion circuit 32 includes a transistor Q2 and a resistor R2. The transistor Q2 has a base connected to the output terminal of the voltage source 35, an emitter connected to the negative power supply line V2 via the resistor R2, and a collector connected to the differential circuit 33 (resistors R3 and R4).

The current 2Ic generated by the VI conversion circuit 32 is expressed by the following formula 2. VBE is the base-emitter voltage of the transistor Q2, and is the same as the base-emitter voltage of the transistor Q1.

  Resistors R1 and R2 have the same resistance, and transistors Q1 and Q2 have the same characteristics (for example, base-emitter voltage and internal resistance). As a result, the discharge current Id generated by the VI conversion circuit 31 is equal to the reference current 2Ic generated by the VI conversion circuit 32.

  The differential circuit 33 is connected to the VI conversion circuit 32 and generates a DC bias current Ic that is a half current of the reference current 2Ic supplied from the VI conversion circuit 32. Specifically, the differential circuit 33 adds a current Δi obtained by converting the audio signal eS from the audio signal source AU to a direct current bias current Ic to generate a current Ic + Δi. Differential circuit 33 includes transistors Q3 and Q4 and resistors R3 to R5. The transistor Q3 has an emitter connected to the collector of the transistor Q2 via the resistor R3, a collector connected to the collector of the transistor Q5 of the current mirror circuit 34, and a base connected to the audio signal source AU. The transistor Q4 has an emitter connected to the collector of the transistor Q2 via the resistor R4, a collector connected to the positive power supply line V1 via the resistor R5, and a base connected to the ground potential.

  In differential circuit 33, current 2Ic from VI conversion circuit 32 is received, current Ic + Δi flows from the collector of transistor Q3 to the emitter, and current Ic−Δi flows from the collector of transistor Q4 to the emitter. Therefore, when the amplitude value of the audio signal eS is 0 (no signal is present), Δi is 0, so that the current Ic flows from the collector of the transistor Q3 to the emitter, and from the collector of the transistor Q4 to the emitter. Current Ic flows.

  The current mirror circuit 34 supplies a current having the same current value as the current Ic + Δi flowing through the transistor Q3 of the differential circuit 33 to the capacitors C1 and C2 as the charging current Ij. Current mirror circuit 34 includes transistors Q5 and Q6 and resistors R6 and R7. Transistor Q5 has a collector connected to the collector of transistor Q3, an emitter connected to positive power supply line V1 via resistor R6, and a base connected to the base of transistor Q6. The transistor Q6 has an emitter connected to the positive power supply line V1 via a resistor R7, and a collector serving as a node that outputs a charging current Ij. That is, the collector of the transistor Q6 is connected to the first capacitor C1 through the first switch SW1, and is connected to the second capacitor C2 through the second switch SW2.

  As described above, since the DC bias current Ic and the discharge current Id are generated from the voltage Vb of the same voltage source 35, the relationship of DC bias current Ic: discharge current Id = 1: 2 can be maintained. This relationship can be maintained even when the voltage V2 of the voltage source 35 is varied by the voltage switching circuit 36.

  The voltage source 35 generates a voltage Vb for generating a DC bias current Ic and a discharge current Id. Voltage source 35 includes a transistor Q7 and resistors R9 to R11. The transistor Q7 has an emitter connected to the negative power supply line V2, a collector connected to the output terminal of the voltage source 35, a base connected to the positive power supply line V1 via resistors R9 and R8, and a resistor R10. And R11 are connected to respective one ends. The other end of the resistor R10 is connected to the negative power supply line V2 via the switch element Q8 of the voltage switching circuit 36. The other end of the resistor R11 is connected to the negative power supply line V2 via the switch element Q9 of the voltage switching circuit 36.

The voltage generated by the voltage source 35 is shown in the following formula 3.

  VBE is the base-emitter voltage of the transistor Q7 and is the same as the base-emitter voltage of the transistors Q1 and Q2. Rb is a resistance value based on the resistors R10 and R11, and is set by the voltage switching circuit 36 to either R10, R11, or a combined resistor R10 · R11 / (R10 + R11) of R10 and R11.

  When the frequency of the reference clock MCLK is switched, the voltage switching circuit 36 receives the fifth switching signal φ5 and the sixth switching signal φ6 and switches the voltage value of the voltage Vb generated by the voltage source 35. The voltage switching circuit 36 includes a switch element (eg, FET) Q8 connected between the resistor R10 and the negative power supply line V2, and a switch element (eg, FET) connected between the resistor R11 and the negative power supply line V2. ) Q9.

  The switch element Q8 is supplied with the fifth switching signal φ5 and is turned on or off based on the fifth switching signal φ5, and the resistor R10 is connected to the bases of the resistor R9 and the transistor Q7, or the resistor R10. Is switched to one of the states not connected to the resistor R9 and the base of the transistor Q7. For example, the switch element Q8 is turned on when the fifth switching signal φ5 is at a high level, and is turned off when it is at a low level.

  The switch element Q9 is supplied with the sixth switching signal φ6 and is turned on or off based on the sixth switching signal φ6. The resistor R11 is connected to the base of the resistor R9 and the transistor Q7, or the resistor R11. Is switched to one of the states not connected to the resistor R9 and the base of the transistor Q7. For example, the switch element Q9 is turned on when the sixth switching signal φ6 is at a high level, and is turned off when it is at a low level.

  4 shows that when R10> R11, the fifth switching signal φ5 (switch element Q8), the sixth switching signal φ6 (switch element Q9) when the reference clock MCLK is in the first to third frequencies, And the relationship of resistance Rb is shown. For example, when R10 = 1 kΩ and R11 = 0.5 kΩ, Rb = 1 kΩ at the first frequency, Rb = 0.5 kΩ at the second frequency, and Rb = 0.33 kΩ at the third frequency. Rb decreases as the frequency of the clock MCLK increases. Therefore, since the voltage Vb generated by the voltage source 35 is expressed by the above equation 3, the voltage Vb increases as the frequency of the reference clock MCLK increases. Accordingly, since the DC bias current Ic and the discharge current Id are expressed by the above formulas 1 and 2, the higher the frequency of the reference clock MCLK, the larger the voltage change amount of the first capacitor C1 and the second capacitor C2.

  Similarly, Rb increases as the frequency of the reference clock MCLK decreases. Therefore, the voltage Vb generated by the voltage source 35 decreases as the frequency of the reference clock MCLK decreases. Accordingly, the DC bias current Ic and the discharge current Id become smaller as the frequency of the reference clock MCLK becomes lower, and the voltage change amount of the first capacitor C1 and the second capacitor C2 becomes smaller.

In voltage switching circuit 36, the switch elements Q8 and Q9 cannot both be off. Therefore, if the combination of the resistor and the switch element connected in parallel to the resistor R9 and the base of the transistor Q7 is two pairs (a pair of R10 and Q8 and a pair of R11 and Q9) as shown in FIG. The voltage Vb can be switched to “2 ² −1 = 3” values. As a result, the DC bias current Ic and discharging current Id can also be switched to a value of "2 ² -1 = 3" as the frequency of the reference clock MCLK can be switched in three ways.

Similarly, as in the current generation circuit shown in FIG. 3B, there are three combinations of resistors and switch elements (R10 and Q8, R11 and Q9) that are connected in parallel to the resistor R9 and the base of the transistor Q7. , And a set of R12 and Q10), the voltage Vb can be switched to “2 ³ −1 = 7” values. As a result, the DC bias current Ic and discharging current Id can also be switched to a value of "2 ³ -1 = 7" through the frequency of the reference clock MCLK can be switched to seven patterns.

In general, if the combination of the resistor and the switch element connected in parallel to the resistor R9 and the base of the transistor Q7 is n sets, the voltage Vb can be switched to “2 ⁿ −1” values. As a result, the DC bias current Ic and the discharge current Id can be switched to “2 ⁿ −1” values, and the frequency of the reference clock MCLK can be switched to “2 ⁿ −1”. Thus, according to the voltage switching circuit 36, the voltage Vb can be switched to a large number of values according to the frequency of the reference clock MCLK by a combination of a small resistance and a switching element, and the DC bias current Ic and the discharge current Id can be switched. Can be switched to multiple values.

Here, when the frequency of the reference clock MCLK is switched, the charging voltage (voltage at the end of charging) of the first capacitor C1 and the second capacitor C2 when the audio signal is no signal (no modulation) is expressed as the reference clock MCLK. The condition of the resistor Rb for always setting the voltage (VCC−Vref) / 2 to ½ of the chargeable voltage regardless of the frequency is shown in the following formula 4.

  VBE is the base-emitter voltage of the transistor Q7, and is the same as the base-emitter voltage of the transistors Q1 and Q2. C is the capacitance of the first capacitor C1 and the second capacitor C2, and f is the frequency of the reference clock MCLK. Therefore, the resistance values of the resistors R10 and R11, the fifth switching signal φ5, and the sixth switching signal φ6 may be set so that the resistor Rb can be set to an appropriate value according to the frequency of the reference clock MCLK.

  Hereinafter, the operation when the frequency of the reference clock MCLK is switched will be described with reference to FIGS. 7A to 7C. In each FIG. 7, only the waveforms of (f) and (b) in FIG. 5 are shown. 7A and 7B, (1) shows the case where the audio signal is no signal, (2) shows the case where the amplitude value of the audio signal is positive, and (3) shows the case where the amplitude value of the audio signal is negative. . FIG. 7A shows a case where the frequency of the reference clock MCLK is the second frequency that is the reference frequency. FIG. 7B shows a case where the frequency of the reference clock MCLK is the first frequency which is a low frequency. FIG. 7C shows a case where the frequency of the reference clock MCLK is the third frequency, which is a high frequency.

  When the reference clock MCLK is at the second frequency, as shown in FIG. 4, since the fifth switching signal φ5 is at the low level and the sixth switching signal φ6 is at the high level, the switching element Q8 is in the off state and the switching element Q + is in the on state. State. Therefore, only the resistor R11 is connected to the resistor R9 and the base of the transistor Q7, and Rb = R11 (for example, 0.5 kΩ). As a result, the current amounts of the DC bias current Ic and the discharge current Id become an intermediate value among the set three current amounts. As a result, as shown in FIG. 7A, the voltage change amount (slope) during charging and discharging of the first capacitor C1 is at an intermediate level. Since the frequency of the reference clock MCLK is the reference frequency and the charging time of the capacitor C1 is also at an intermediate level, the charging voltage Va of the capacitor C1 becomes (VCC−Vref) / 2. As a result, the voltage value from Va to VCC and the voltage value from Va to Vref are the same, so that the positive amplitude value and the negative amplitude value of the audio signal when the voltage is clipped in the capacitor C1 Becomes the same, and a normal PWM waveform can be output.

  When the reference clock MCLK is at the first frequency, as shown in FIG. 4, since the fifth switching signal φ5 is at the high level and the sixth switching signal φ6 is at the low level, the switching element Q8 is in the on state and the switching element Q9 is in the off state State. Therefore, only the resistor R10 is connected to the resistor R9 and the base of the transistor Q7, and Rb = R10 (for example, 1 kΩ). Thereby, the current amount of the DC bias current Ic and the discharge current Id becomes the minimum value among the set three current amounts. As a result, as shown in FIG. 7B, the voltage change amount (slope) during charging and discharging of the first capacitor C1 is minimized. Since the frequency of the reference clock MCLK is low and the charging time of the capacitor C1 is long, the charging voltage Va of the capacitor C1 becomes (VCC-Vref) / 2. As a result, the voltage value from Va to VCC and the voltage value from Va to Vref are the same, so that the positive amplitude value and the negative amplitude value of the audio signal when the voltage is clipped in the capacitor C1 Becomes the same, and a normal PWM waveform can be output.

  When the reference clock MCLK is at the third frequency, as shown in FIG. 4, since the fifth switching signal φ5 is at the high level and the sixth switching signal φ6 is at the high level, the switching element Q8 is in the on state and the switching element Q9 is in the on state. State. Accordingly, the resistors R10 and R11 are connected in parallel to the resistor R9 and the base of the transistor Q7, and Rb = R10R11 / (R10 + R11) (for example, 0.33 kΩ). Thereby, the current amount of the DC bias current Ic and the discharge current Id becomes the maximum value among the set three current amounts. As a result, as shown in FIG. 7C, the voltage change amount (slope) when the first capacitor C1 is charged and discharged is maximized. Since the frequency of the reference clock MCLK is high and the charging time of the capacitor C1 is short, the charging voltage Va of the capacitor C1 becomes (VCC-Vref) / 2. As a result, the voltage value from Va to VCC and the voltage value from Va to Vref are the same, so that the positive amplitude value and the negative amplitude value of the audio signal when the voltage is clipped in the capacitor C1 Becomes the same, and a normal PWM waveform can be output.

  Next, a pulse width modulation circuit 1 'according to another embodiment of the present invention will be described. FIG. 8 is a block circuit diagram showing the main part of the pulse width modulation circuit 1 '. In FIG. 8, only the parts different from FIG. 2 are described, and the clock frequency control unit 10, the reference clock generation circuit 11, the dead time generation circuit 12, the falling edge circuit 13, the first RS flip-flop circuit 17, the first The 2RS flip-flop circuit 18 and the signal output circuit 19 are omitted. The pulse width modulation circuit 1 'reverses the voltage change direction of the first and second capacitors C1 and C2 during the charge / discharge period. That is, the directions of the charging current Ij (= Ic + Δi) and the discharging current Id are opposite to those of the pulse width modulation circuit 1 of FIG. Is discharged (that is, charged in the negative direction with respect to the ground potential), and the first capacitor C1 is charged with the discharge current Id while the first switching signal φ1 is at the low level (that is, discharged in the positive direction with respect to the ground potential). ) Further, the pulse width modulation circuit 1 'is provided with comparison circuits 27 and 28 for comparing the charging voltages of the first and second capacitors C1 and C2 with the threshold voltage Vref instead of the threshold voltage. Details of the pulse width modulation circuit 1 ′ are disclosed in Patent Document 1.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment. The constant ratio between the DC bias current Ic and the discharge current Id is not limited to 1: 2, but may be 1: 1 or 2: 3 depending on the circuit configuration. As shown in FIGS. 3C and 3D, in the circuit diagrams of FIGS. 3 and 3B, a transistor Q11 may be provided between the transistor Q4 and the resistor R5. The transistor Q11 has a base connected to the bases of the transistors Q5 and Q6, a collector connected to the collector of the transistor Q4, and an emitter connected to the resistor R5.

  The present invention can be suitably applied to a pulse width modulation circuit of an audio switching amplifier.

DESCRIPTION OF SYMBOLS 1,1 'Pulse width modulation circuit 2 Switching circuit 3 Low pass filter circuit 4 1st power supply 5 2nd power supply 10 Clock frequency control part 11 Reference clock generation circuit 12 Dead time generation circuit 13 Falling edge detection circuit 14 Current generation circuit 16 Current Bypass circuit 17 First RS flip-flop circuit 18 Second RS flip-flop circuit 19 Signal output circuit 23 Voltage source 31 VI conversion circuit 32 VI conversion circuit 33 Differential circuit 34 Current mirror circuit 35 Voltage source 36 Voltage switching circuit C1 First capacitor C2 First 2 capacitor eS audio signal Ic DC bias current Id discharge current res1 first reset signal res2 second reset signal set1 first set signal set2 second set signal SW1 first switch SW2 second switch SW3 third switch SW4 fourth switch Vref threshold voltage φ1 first switching signal φ2 second switching signal φ3 third switching signal φ4 fourth switching signal φ5 fifth switching signal φ6 sixth switching signal

Claims (6)

First charge storage means for storing charge;
Second charge storage means for storing charge;
Current generating means for generating a first current whose current value changes according to the amplitude of the input AC voltage and generating a second current;
The voltage in the first charge storage means is changed in a first period which is a half cycle of the clock signal based on the first current, and the half period is shifted from the first period based on the second current. In the second period following the first period, the voltage in the first charge storage means is changed in the direction opposite to the increase / decrease direction in the first period, and the voltage in the second charge storage means is changed based on the first current. Based on the second current, the voltage in the second charge accumulating means is opposite to the increase / decrease direction in the second period in the third period following the second period that is shifted from the second period by a half cycle. Voltage control means for changing to
First detection means for detecting a time from when the second period starts until the voltage in the first charge storage means reaches a threshold voltage;
Second detection means for detecting a time from when the third period starts until the voltage in the second charge storage means reaches the threshold voltage;
A pulse signal generating unit that generates a pulse signal having a pulse width of the time based on a time alternately output from the first detecting unit and the second detecting unit alternately every half cycle of the clock signal;
Frequency control means for switching the frequency of the clock signal to one frequency selected from a plurality of frequencies,
The current generating means is
A voltage source for supplying voltage;
Voltage switching means for switching the voltage supplied by the voltage source according to the frequency of the clock signal selected by the frequency control means;
First current generating means for generating the first current based on the voltage supplied from the voltage source and the AC voltage;
A pulse width modulation circuit comprising: a second current generation unit configured to generate the second current based on the voltage supplied from the voltage source. When the frequency of the clock signal is switched to a frequency lower than the current frequency, the voltage switching means is connected to the voltage source so that the first current and the second current are smaller than the current current. Switch so that the voltage is lower than the current voltage,
When the frequency of the clock signal is switched to a frequency higher than the current frequency, the voltage switching means is connected to the voltage source so that the first current and the second current are larger than the current current. The pulse width modulation circuit according to claim 1, wherein the voltage is switched so that the voltage is larger than the current voltage. The first current generating means is
Voltage-current conversion means for generating a third current having the same current value as the second current based on the voltage supplied from the voltage source;
A differential circuit that generates a fourth current obtained by adding a current based on the AC voltage to a current that is ½ of the third current;
The pulse width modulation circuit according to claim 1, further comprising: a current mirror circuit that generates the first current having the same current value as the fourth current. When the voltage switching means includes a plurality of switch elements for switching connection or non-connection of the resistance elements of the voltage source to or from the voltage source, and when the number of the switch elements is n, all the switch elements are turned off. 4. The pulse width modulation circuit according to claim 1, wherein the voltage is switched to any one of 2 ⁿ −1 voltages excluding the case where the state is reached, according to the frequency of the clock signal. 5.   The charging start voltage in the first charge storage means and the second charge storage means is the threshold voltage Vref, and the upper limit of the chargeable voltage in the first charge storage means and the second charge storage means is the power supply voltage VCC. In some cases, even when the frequency of the clock signal is switched to any frequency, the maximum charge voltage Va of the first charge storage means and the second charge storage means when the amplitude of the AC voltage is zero. 5. The pulse width modulation circuit according to claim 1, wherein a voltage supplied from the voltage source switched by the voltage switching means is determined so that becomes (VCC−Vref) / 2. The pulse width modulation circuit according to any one of claims 1 to 5,
A switching amplifier comprising: a switching circuit that switches a power supply voltage based on a modulation signal output from the pulse width modulation circuit.