JP2010199262A - Tape carrier for semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a tape carrier for semiconductor device, capable of accurately, stably and uniforming forming various conductor patterns including a wiring pattern. <P>SOLUTION: The tape carrier for semiconductor device has conductor patterns 3 including a wiring pattern, formed by patterning a metal material layer provided on an insulating substrate 1 by a subtractive method. The dimension of pattern-to-pattern spaces 4 of all the conductor patterns 3 in the taper carrier are set to the same as a minimum space dimension Ws on pattern design of the conductor patterns 3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a tape carrier for a semiconductor device suitable for a tape carrier for a liquid crystal display device used for mounting a liquid crystal driving IC, for example, and a method for manufacturing the same.

  FIG. 6 is a diagram showing an example of a copper-clad film substrate used for a TAB tape carrier having a COF (Chip On Film) structure, which is one type of tape carrier for semiconductor devices according to this type of prior art. FIG. 7 is a diagram illustrating an example of a tape carrier for a semiconductor device manufactured using the copper-clad film substrate.

  The copper-clad film substrate includes an insulating film base 101, a metal material layer 102, and a reinforcing film 103. That is, a metal material layer 102 is formed on the surface of an insulating film substrate 101 such as a polyimide resin film by copper (Cu) plating, for example, via a Cr layer or the like (not shown). In order to reinforce the mechanical strength of the copper-clad film substrate on the surface opposite to the surface on which the material layer 102 is provided, and to facilitate transport operations and handling in a series of manufacturing processes. The reinforcing film 103 is attached via an adhesive layer (not shown).

Although not shown in the drawing, after forming the transport hole by a press (punching) punching method, resist coating, exposure and development are performed to form a resist pattern, which is used as an etching mask, and is subtractive. By patterning the metal material layer 102 by a method (wet etching process or the like), a conductor pattern 106 including the wiring pattern 104 and the connection pad 105 is formed, and the resist is peeled off. Thereafter, a mounting transport hole (not shown) is formed by press punching, and tin (Sn) plating for connection to a semiconductor device such as an external IC chip, a liquid crystal display device, or the like is applied (both shown) (Omitted).
Subsequently, after the reinforcing film 103 is peeled off, a solder resist (not shown) for enhancing electrical insulation and mechanical strength is formed. Then, slitting, inspection, etc. are performed before shipment.

In recent years, with further advancement of liquid crystal display devices such as higher definition and higher gradation color, tape patterns for liquid crystal display devices (for LCD driver ICs) have further refined wiring patterns 104, that is, wiring widths. (B2 in FIG. 7) and the space between adjacent wiring patterns 104 (Ws-2, Ws-3, Ws-4 in FIG. 7) have been demanded. In addition to the wiring pattern 104, for example, the connection pad 105 is required to be further miniaturized in its outer dimensions (B1 in FIG. 7) and the inter-pattern space 107 (Ws-1 in FIG. 7). ing.
The COF technology is considered promising as being adaptable to such demands. Here, the space between wirings and the space between other patterns are collectively referred to as “inter-pattern space” (the same applies hereinafter). Further, the wiring patterns and other patterns such as connection pads are collectively referred to as “conductor patterns” (the same applies hereinafter).

Further, in general, tape carriers for semiconductor devices other than those for liquid crystal display devices have been developed and attracted attention because COF technology that does not require hollow wiring can be applied to fine wiring. Realization of the formation of wiring is greatly expected.
The entire conductor pattern 106 including the miniaturized wiring pattern 104, connection pad 105, and the like is not simply formed in a fine dimension, but the wiring width (B2), the external dimension (B1), and the like. Therefore, it is required that the variation in the above can be stably formed with high accuracy and a high yield of a predetermined level or higher.

  As a technique for stably achieving further miniaturization of the wiring pattern of such a semiconductor device tape carrier, for example, a wide portion of the inter-pattern space 107 between adjacent wiring patterns 104 (for example, Ws− in FIG. 7). 2 and Ws-4) are provided with dummy patterns (not shown) to uniformize the etching conditions of the wiring pattern 104, so that the conductor pattern 106 such as the wiring pattern 104 has the outer dimensions and shape as intended. As described above, there has been proposed a technique that is intended to form with high accuracy and stability (see, for example, Patent Document 1).

JP 2007-53237 A

In general, when the conductor pattern 106 such as the wiring pattern 104 is formed by a subtractive method such as a wet etching process, the inter-pattern space 107 has a rough portion (for example, Ws-2 or Ws-4 in FIG. 7) and a dense pattern. (For example, Ws-1 in FIG. 7), but in the sparse part, the wrapping of the etching solution (the flow of the etching solution to and from the portion to be etched; the same applies hereinafter) becomes favorable, and the reverse In addition, the wraparound of the etching solution becomes worse in dense areas. For this reason, the dimensions of the finished conductor pattern 106 may vary or may differ from the intended dimensions depending on the sparse / dense difference in the inter-pattern space 107 between the adjacent conductor patterns 106. There is a problem.
Further, since the etching solution wraps around the sparse part as described above, there is a high possibility that the cross-sectional shape of the completed wiring pattern 104 is reversely tapered.
In order to solve such a problem, a method of using the above-described dummy pattern was proposed in Patent Document 1.

However, the technique of adding a dummy pattern proposed in Patent Document 1 can be applied to a tape carrier having an inter-pattern space 107 that is larger than the dummy pattern can be placed. If it has only a small inter-pattern space 107 that is practically impossible to do, it is impossible to apply.
For this reason, the method of using a dummy pattern is practically inapplicable to a tape carrier that requires further miniaturization of the wiring width and outer dimensions of the conductor pattern 106 and the inter-pattern space 107.
In addition to the technique of adding a dummy pattern proposed in Patent Document 1, the above-described inter-pattern space 107 is caused by non-uniform etching progress rates in a rough portion and a dense portion. As a technique intended to suppress the variation in the size and shape of the conductive pattern 106 that occurs, a technique is known in which an appropriate correction is made to the outer dimension of the etching resist pattern.
However, in order to suppress variations in the size and shape of the conductor pattern 106 by such a method, it is required to perform extremely accurate correction. In this case, it is inevitable that a series of processes from the pattern design stage to the etching resist pattern exposure / development stage is greatly complicated. Moreover, since it takes a long time to perform such a series of accurate corrections, it is a fatal inconvenience as a technique applied to a so-called commercial line.

The present invention has been made in view of such problems, and its purpose is to further reduce the fineness of the inter-pattern space between the conductor patterns as the conductor patterns including the wiring patterns are further refined. Provided are tape carriers for semiconductor devices and methods of manufacturing the same that can form various conductor patterns including wiring patterns stably and uniformly in semiconductor tape carriers that are becoming increasingly popular There is to do.

The tape carrier for a semiconductor device of the present invention is a tape carrier for a semiconductor device having a conductor pattern including a wiring pattern formed by patterning a metal material layer provided on an insulating substrate by a subtractive method, In the tape carrier for a semiconductor device, the dimension of the space between all the conductor patterns is set to be the same as the dimension of the minimum space in the pattern design of the conductor pattern.
The method for producing a tape carrier for a semiconductor device according to the present invention includes forming a resist pattern on the surface of a metal material layer provided on a film substrate made of an insulating material, and performing the above-described process by a wet etching process using the resist pattern as a mask. A method of manufacturing a tape carrier for a semiconductor device, which forms a conductor pattern including a wiring pattern by performing pattern processing on a metal material layer, wherein the dimension between the patterns of all the conductor patterns in the tape carrier for a semiconductor device is The conductor pattern is formed by setting the same size as the minimum space dimension in the pattern design of the conductor pattern.

  According to the present invention, the size of the inter-pattern space of all the conductor patterns in the tape carrier for a semiconductor device is set to be the same as the size of the minimum space on the pattern design of the conductor pattern (all unified). In the tape carrier for a semiconductor device, the conditions for the wraparound of the etching solution in the inter-pattern space between all the conductor patterns are equal. That is, the progress of etching in all the inter-pattern spaces is performed under the same conditions. As a result, it is possible to form a conductor pattern in which various different shapes and external dimensions including a wiring pattern are mixed with high accuracy and stably at a high yield.

It is a figure which shows the structure of the principal part of the tape carrier for semiconductor devices which concerns on embodiment of this invention. It is a figure which shows the flow of the main manufacturing processes of the tape carrier for semiconductor devices which concerns on embodiment of this invention. It is a figure which shows a more specific example of the planar structure of the wiring pattern part in the tape carrier for semiconductor devices which concerns on embodiment of this invention. It is AA sectional drawing in the tape carrier for semiconductor devices shown in FIG. In the tape carrier for a semiconductor device according to the embodiment of the present invention, a more specific example of a planar configuration of a portion where wiring patterns with different wiring widths, conductor patterns with different outer dimensions, etc. are mixed is shown. FIG. It is a figure which shows an example of the copper clad film board | substrate used for the TAB tape carrier etc. of the conventional general COF (Chip On Film) structure. It is a figure which shows an example of the tape carrier for semiconductor devices manufactured using the copper clad film board | substrate shown in FIG.

  Hereinafter, a tape carrier for a semiconductor device and a manufacturing method thereof according to embodiments of the present invention will be described with reference to the drawings.

As shown in FIGS. 1 and 2, the tape carrier for a semiconductor device is obtained by applying a metal foil layer or a metal thin plate-like metal material layer 2 provided on the surface of an insulating substrate 1 by, for example, a wet etching method. This is a tape carrier for a semiconductor device having a conductor pattern 3 including a wiring pattern formed by patterning by such a subtractive method, and the inter-pattern space 4 between all the conductor patterns 3 has the same dimension (design) Of the smallest space (Ws). Almost the entire surface of the insulating substrate 1 including the surface of the conductor pattern 3 (excluding the surface of a portion requiring contact with the outside such as an external connection pad) is covered with a solder resist 5. ing.

  The insulating substrate 1 is made of an insulating film substrate such as polyimide. However, the material of the insulating substrate 1 is not limited to the polyimide film. In addition, any material that can be used as a base material for a tape carrier can be suitably used as the insulating substrate 1.

  The metal material layer 2 is made of a thin conductive material such as a metal foil such as a copper foil or other highly conductive metal thin plate. More specifically, for example, an ultrathin copper foil having a thickness of about 10 μm may be laminated on the surface of the insulating substrate 1 or desired on the surface of the insulating substrate 1 by, for example, electroless copper plating. It may be formed to a thickness of. In addition to copper, it is also possible to make a precise pattern by a wet etching method and to be made of a metal material having good conductivity.

  The conductor pattern 3 is formed by patterning the metal material layer 2 into a desired pattern by a wet etching method, and mainly includes a wiring pattern and other patterns such as connection pads and various lands. Various sizes and shapes of the conductor patterns 3 are mixed in one semiconductor device tape carrier, but the inter-pattern spaces 4 between all the conductor patterns 3 are exactly the same size (Ws ). And the dimension Ws is the dimension of the minimum space in the pattern design of the conductor pattern 3 in this tape carrier for semiconductor devices.

  However, the dimension Ws of the inter-pattern space 4 is desirably 10 μm or more. This is because even when an ultrathin copper foil having a thickness of about 10 μm as described above is used, if the dimension of the inter-pattern space 4 is less than 10 μm, the so-called aspect ratio in the wet etching process exceeds 1. For this reason, there is a high possibility that a short-circuit defect or the like will occur during the pattern processing, and it may be difficult to ensure insulation reliability in the completed tape carrier for a semiconductor device. However, the thickness is desirably 10 μm or more, but it is needless to say that the thickness is not limited to only 10 μm or more.

Further, the total area of the conductor pattern 3 is the total area of the metal material layer 2 in an unprocessed state before pattern processing (in other words, the total area of the pattern formable region in the tape carrier for a semiconductor device). 70% or more is desirable. This is because, when the total area of the conductor pattern 3 is set to 70% or more, especially when the thin insulating substrate 1 is used, the transportability after pattern processing by wet etching is improved, and deformation during transport is prevented. As a result, it is possible to manufacture with a high yield.
In addition, by unifying all the inter-pattern spaces 4 to the same dimension Ws as the minimum design space, the total area of the conductor pattern 3 can be easily increased without any design correction or compromise. It tends to be 70% or more of the total area of the pattern formable region in the tape carrier for use. Also in this point, there is an advantage that the dimension Ws of the inter-pattern space 4 is set to the minimum space in the design.

Further, by leaving such a large number of conductor patterns 3 on the insulating substrate 1, the overall expansion and contraction of the tape carrier for the semiconductor device is suppressed by the mechanical strength of the conductor pattern 3, and stable. Implementation is possible. This tends to be more effective particularly when the thickness of the insulating substrate 1 is as thin as 100 μm or less. In this respect, the tape carrier for a semiconductor device and the manufacturing method thereof according to the embodiment of the present invention has an advantage that it can be more effective particularly when the thickness of the insulating substrate 1 is 100 μm or less. Yes. However, the present invention can also be applied to the case of the insulating substrate 1 having a thickness of more than 100 μm, and even in that case, the conductor pattern 3 corresponding to miniaturization can be formed with high accuracy and stability. Of course.

The flow of the main steps in this method for manufacturing a semiconductor device tape carrier is as shown in FIG.
First, as shown in FIG. 2A, a metal material such as a copper foil having a thickness of about 10 μm, for example, is formed on the surface of a tape-like insulating substrate 1 made of a polyimide resin film having a thickness of about 38 μm. A so-called copper-clad film substrate obtained by laminating layers 2 is prepared. The metal material layer 2 may be formed on the surface of the insulating substrate 1 by a copper plating method through a Cr sputtered film (not shown), or may be laminated with, for example, an ultrathin copper foil.
As shown in FIG. 2B, the conveying hole 6 is punched and formed along both longitudinal edges of the copper-clad film substrate.

Subsequently, as shown in FIG. 2C, a liquid photoresist 7 is applied on the surface of the metal material layer 2.
Then, using a photomask for etching resist pattern exposure and a projection exposure apparatus (both not shown), resist exposure is performed as shown in FIG. The mask pattern of the photomask used at this time is provided so that all the spaces between the patterns have the same dimension corresponding to the dimension Wr of the minimum space of the latent image of the etching resist pattern 8 to be formed. Therefore, in the latent image formed by the exposure using the photomask, the inter-pattern space between the adjacent etching resist patterns 8 (indicated by reference numeral 7 in FIG. 2D). The dimensions Wr are all equal and are aligned to the dimensions corresponding to the design minimum space dimension Ws in the semiconductor device tape carrier.

  Subsequently, as shown in FIG. 2E, the photoresist 7 is developed to form an etching resist pattern 8. At this time, the total area of the formed etching resist pattern 8 is desirably 85% or more of the total area of the metal material layer 2 (total area in an unprocessed state before being subjected to pattern processing), for example. . This is to make the total area of the finally completed conductor pattern 3 70% or more, which is a desirable numerical aspect as described above. Considering an etching factor, etc., a margin of about 15% is included. At this point, it is set to 85% or more.

  Subsequently, as shown in FIG. 2 (f), the metal material layer 2 is patterned by a wet etching process using the etching resist pattern 8 as a so-called etching mask to form the conductor pattern 3. In this step, since the inter-pattern space 9 between all the adjacent etching resist patterns 8 is unified and has a dimension Wr, the etching conditions for the metal material layer 2 in all the inter-pattern spaces 9 are equal. It will be a thing. That is, wet etching under the same conditions can be performed in all the inter-pattern spaces 9. Thereby, all the inter-pattern spaces 4 in the conductor pattern 3 formed by patterning the metal material layer 2 in this step can be set to the same dimension Ws. Here, in consideration of the etching factor, etc., Ws = Wr is not strictly required, and there may be some errors (within an allowable range), but the etching is performed so that the total area of the conductor pattern becomes 70% or more. It is desirable to make it.

  Subsequently, as shown in FIG. 2G, the etching resist pattern 8 is peeled and removed. Thereafter, although not shown in the figure, the corresponding portions of the conductor pattern 3 may be subjected to tin plating or the like for surely making an electrical connection to a connection pad in an external semiconductor device or various wiring boards. At this stage, it is desirable that the total area of the already formed conductor pattern 3 is 70% or more of the total area of the metal material layer 2 in an unprocessed state before patterning.

  Then, as shown in FIG. 2 (h), in order to cover the conductor pattern 3 and further improve the insulation and mechanical strength thereof, a solder resist 5 is formed by, for example, a printing method to implement the present invention. The main part of the tape carrier for semiconductor devices according to the embodiment is completed.

  In the tape carrier for a semiconductor device according to the embodiment of the present invention, the portion where the wiring pattern is arranged can be more specifically as shown in FIG. 3 and FIG. is there.

  The thick wiring patterns 3-1, 3-8, the thin wiring patterns 3-3, 3-4, 3-5, 3-7 and the slightly thick wiring patterns 3-2, 3-6 are mixed. The inter-pattern spaces 4 (4-1 to 4-7) between the adjacent wiring patterns 3 are all set to the same dimension Ws. That is, the inter-pattern space 4-1 between the thick wiring pattern 3-1 and the slightly thick wiring pattern 3-2 is also the inter-pattern space 4 between the slightly thick wiring pattern 3-2 and the thin wiring pattern 3-3. -2, the inter-pattern space 4-3 between the thin wiring pattern 3-3 and the thin wiring pattern 3-4, and other inter-pattern spaces 4-4, 4-5, 4-6, 4 −7 are all the same and have the minimum design dimension Ws.

  Further, in the tape carrier for a semiconductor device according to the embodiment of the present invention, the portion where the conductor patterns 3 having different wiring widths and outer dimensions are mixed is more specifically shown in FIG. Can be. In FIG. 5, the topological arrangement on the electrical connection and mounting of the conductor pattern 3 is related to the prior art shown in FIG. 7 in order to facilitate comparison and contrast with the prior art. This is the same as that in the tape carrier for semiconductor devices. That is, for example, in FIG. 7, the portion with the lead line 105 (the portion of the connection pad whose outer dimension is B1 and the outline is rectangular) is the portion with the lead line 3d in FIG. Corresponds to the B1 connection pad portion), and the correspondence between the two is drawn.

  As shown in FIG. 5, in the tape carrier for a semiconductor device according to the embodiment of the present invention, the conductor patterns 3a, 3d, and 3e formed so that the connection pads and the wiring patterns are continuous with the same width B1. Conductor patterns 3b and 3c having wider widths, conductor patterns (wiring patterns) 3f and 3g formed to have narrow widths B2 and B3 by providing notches, and conductor patterns 3b and 3d. Conductor patterns 3h and 3i each having a width B4 provided to align the left margin space and the right margin spaces of the conductor patterns 3c and 3e with the dimension Ws. Although conductor patterns 3 having various shapes are mixed, all inter-pattern spaces 4 between the conductor patterns 3 are the minimum in design. It is unified (corresponding to Ws-1 in FIG. 7) pace Ws.

Here, the wiring width of the conductor pattern 3 (for example, the conductor pattern 3f, which is a wiring pattern) is reduced to a desired thin width, for example, because it is necessary to control the impedance characteristics of the wiring pattern. Although it may be necessary to set to dimension B2, the present invention is applicable also in such a case.
In such a case, as shown as a conductor pattern 3f in FIG. 5, for example, a pattern having a wide width B1 such as a conductor pattern 3d, that is, a procedure such as “notch” or “dummy space”. By providing the inter-pattern space 4 having the width Ws, the wide width B1 can be divided into the narrow width B2 and the narrow width B3, and the conductor pattern 3f having the desired narrow width B2 can be formed.

In this case, the remaining divided conductor pattern 3g may be electrically in a so-called floating state, or in some cases, for example, an electric signal or a predetermined voltage for correcting the impedance characteristic for the conductor pattern 3f is input. It is good also as a thing. In any case, the inter-pattern space 4 formed in the manner of “dummy space” as described above divides the conductor pattern 3 having a wide width such as the conductor patterns 3d, 3e, 3b, 3a, and 3c. Thus, since the conductor pattern 3 having a narrower width such as the conductor pattern 3f is formed, it is completely different from the case of the “dummy pattern” according to the prior art. Even if it becomes narrower, it can be applied without any inconvenience. Further, as the wiring width and outer dimension of the conductor pattern 3 are reduced, the necessity of forming the inter-pattern space 4 as the “dummy space” according to the present invention tends to be reduced. The invention is advantageous for further miniaturization of the external dimensions and wiring width of the conductor pattern 3, contrary to the case of the prior art in which it becomes difficult to add a “dummy pattern” when the space between patterns is miniaturized. Is something.
As described above, the tape carrier for a semiconductor device and the manufacturing method thereof according to the present invention can sufficiently cope with further miniaturization of the conductor pattern 3 and the inter-pattern space 4. Has a merit.

As described above, according to the tape carrier for a semiconductor device and the method for manufacturing the same according to the embodiment of the present invention, the inter-pattern space 4 is set to the minimum space regardless of the shape and the external dimensions of the conductor pattern 3. Since Ws is completely unified, the progress of etching in all the inter-pattern spaces 4 is performed under exactly the same conditions. As a result, various conductor patterns 3 can be formed with high accuracy and stability. It can be formed with a high yield.
Moreover, since all the inter-pattern spaces 4 are the minimum design space Ws, the total area of the conductor pattern 3 remaining on the insulating substrate 1 after pattern processing is forcibly subjected to design corrections and compromises. Even if it is not necessary, it can be made 70% or more of the effective total area where the pattern can be formed (the total area of the metal material layer 2 before patterning), so that the transportability after patterning by wet etching is improved. It is possible to prevent deformation during transportation. As a result, it is possible to manufacture with a high yield.
Furthermore, the overall strength of the tape carrier for the semiconductor device is suppressed by the mechanical strength of the conductor pattern 3 having a large total area remaining on the insulating substrate 1, and stable mounting is performed. Is possible. In addition, the use of a reinforcing material such as a reinforcing film can be omitted.
In addition, due to the high heat dissipation effect from the wide total area of the conductor pattern 3, there is also a merit that the overall heat dissipation and heat resistance of the tape carrier for a semiconductor device are greatly improved.
Further, according to the present invention, when it is required to form a conductor pattern 3f having a narrower width, by providing the inter-pattern space 4 in the wide conductor pattern 3 in the manner of “dummy space”, Can respond to requests. That is, the present invention can sufficiently cope with further miniaturization of the conductor pattern 3 and the inter-pattern space 4.

In the above embodiment, the COF type semiconductor device tape carrier and the manufacturing method thereof have been mainly described. However, it goes without saying that the application of the present invention is not limited to this. In addition, the present invention is applicable to a tape carrier for a semiconductor device having a conductor pattern in which sparse and dense inter-pattern spaces are mixed, and a manufacturing method thereof.
Further, it goes without saying that the present invention can be applied to a tape carrier for a semiconductor device in which a reinforcing film is attached to the back surface, a manufacturing method thereof, and the like.

DESCRIPTION OF SYMBOLS 1 Insulating substrate 2 Metal material layer 3 Conductor pattern 4 Space between patterns 5 Solder resist 6 Carrying hole 7 Photoresist 8 Etching resist pattern 9 Space between patterns of etching resist pattern

Claims (8)

A tape carrier for a semiconductor device having a conductor pattern including a wiring pattern formed by patterning a metal material layer provided on an insulating substrate by a subtractive method,
A tape carrier for a semiconductor device, wherein the size of the space between all the conductor patterns in the tape carrier for a semiconductor device is set to be the same as the size of the minimum space in the pattern design of the conductor pattern. The semiconductor device tape carrier according to claim 1,
The tape carrier for a semiconductor device, wherein the space between patterns is 10 μm or more. In the tape carrier for semiconductor devices according to claim 1 or 2,
A tape carrier for a semiconductor device, wherein the total area of the conductor pattern is 70% or more of the total area of the metal material layer in an unprocessed state before the pattern processing. In the tape carrier for semiconductor devices according to any one of claims 1 to 3,
A tape carrier for a semiconductor device, wherein the insulating substrate has a thickness of 100 μm or less. A resist pattern is formed on the surface of the metal material layer provided on the film substrate made of an insulating material, and the metal material layer is subjected to pattern processing by a wet etching process using the resist pattern as a mask to form a wiring pattern. A method of manufacturing a semiconductor device tape carrier for forming a conductor pattern comprising:
A semiconductor device characterized in that the conductor pattern is formed by setting the size of the space between all the conductor patterns in the tape carrier for the semiconductor device to be the same as the size of the minimum space in the pattern design of the conductor pattern. Tape carrier manufacturing method. In the manufacturing method of the semiconductor device tape carrier according to claim 5,
A manufacturing method of a tape carrier for a semiconductor device, wherein the space between patterns is 10 μm or more. In the manufacturing method of the tape carrier for semiconductor devices according to claim 5 or 6,
A method for manufacturing a tape carrier for a semiconductor device, wherein a total area of the conductor pattern is 70% or more of a total area of the metal material layer in an unprocessed state before the pattern processing. In the manufacturing method of the tape carrier for semiconductor devices given in any 1 paragraph among Claims 5 thru / or 7,
A method of manufacturing a tape carrier for a semiconductor device, wherein the insulating substrate has a thickness of 100 μm or less.

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