JP4973513B2 - Tape carrier for semiconductor device, method for manufacturing tape carrier for semiconductor device, and semiconductor device - Google Patents

Description

  The present invention relates to a tape carrier for a semiconductor device, a method for manufacturing a tape carrier for a semiconductor device, and a semiconductor device. In particular, the present invention relates to a tape carrier for a semiconductor device as a TAB tape (COF tape) for a Liquid Crystal Display (LCD) to which the Chip On Film (COF) technology is applied, a method for manufacturing a tape carrier for a semiconductor device, and a semiconductor device About.

  With the demand for higher definition and higher image quality in LCDs for LCD TVs and LCDs for personal computer displays, etc., miniaturization of electrical wiring of Tape Automated Bond (TAB) tapes for LCDs Is progressing. As the electrical wiring of the TAB tape becomes finer, the power consumption of the driver IC that drives the LCD is increasing. As a result, for the purpose of reducing problems caused by heat generated from the IC chip, it is desired to improve the heat dissipation characteristics of the heat generated in the IC chip from the TAB tape.

  As a conventional tape carrier for a semiconductor device, a film having an upper surface and a lower surface, an upper metal layer having an input / output terminal pattern and formed on the upper surface, and a ground layer having a size including at least a chip mounting region And a lower metal layer that is formed on a lower surface corresponding to a chip mounting region and is electrically connected to an upper metal layer through a via (see, for example, Patent Document 1).

  In the tape carrier for a semiconductor device according to Patent Document 1, since the ground layer having a size including at least the chip mounting region is provided on the lower surface of the film, the ground layer is electrically connected to the input / output terminal pattern on the upper surface of the tape carrier. Can be grounded by being connected together.

JP 2007-27682 A

  However, the tape carrier for a semiconductor device described in Patent Document 1 does not consider the heat dissipation caused by the heat generated by the increase in power consumption of the driver IC that drives the LCD, and the semiconductor device such as an IC chip is not considered. There is a possibility that it becomes difficult to suppress the malfunction of the LCD due to the temperature rise.

  Accordingly, an object of the present invention is to provide a tape carrier for a semiconductor device, a method for manufacturing the tape carrier for a semiconductor device, and a semiconductor device that can efficiently dissipate heat generated in a semiconductor element.

In order to achieve the above object, the present invention is provided at a predetermined position on the first surface of the insulating film, an insulating film having a first surface and a second surface facing the first surface, A wiring pattern having an inner lead portion on which a semiconductor element is mounted; and a heat radiation pattern provided on the second surface having an opening region on the second surface facing at least a part of the wiring pattern; The opening region is provided in a region where the inner lead portion can be visually recognized from the second surface, provided on the second surface corresponding to a position immediately below the semiconductor element mounted on the inner lead portion, and mounted on the inner lead portion. There is provided a tape carrier for a semiconductor device, which is formed larger than an outer edge of the semiconductor element as viewed from above.

Also, the insulating film, a via through the first surface and the second surface has a position radiating pattern is provided in a part directly under the wiring pattern, the wiring pattern, via a via And may be connected to the heat dissipation pattern. Furthermore, the wiring pattern may be connected to the heat radiation pattern through the via to be conductive. Further, the heat dissipation pattern may be formed with a film thickness of 8 μm or more, and the heat dissipation pattern may be formed of pure copper. Alternatively, the wiring pattern may be formed by performing a surface plating process.

In order to achieve the above object, the present invention provides an insulating film preparation step of preparing an insulating film having a first surface and a second surface facing the first surface, and the first surface of the insulating film. A wiring pattern forming step for forming a wiring pattern having an inner lead portion on which a semiconductor element is mounted at a predetermined position above, and a heat dissipation pattern having an opening region on a second surface facing at least a part of the wiring pattern A heat radiation pattern forming step formed on the second surface, wherein the heat radiation pattern forming step includes an opening region in a region where the inner lead portion is visible from the second surface, and is mounted on the inner lead portion. on the second surface corresponding to just below the semiconductor element, a half, characterized in that providing a larger opening formed region of the outer edge in the top view of the semiconductor device to be mounted on the inner lead portion To provide a method of manufacturing a tape carrier for the body system.

In order to achieve the above object, the present invention provides a semiconductor element having an electrode, an insulating film having a first surface and a second surface opposite to the first surface, and a first surface of the insulating film. A wiring pattern having an inner lead portion provided at a predetermined position on the semiconductor device and mounted by bonding a semiconductor element via an electrode; and an inner lead on a second surface facing at least a part of the wiring pattern A semiconductor device is provided that includes an opening region that is formed larger than the outer edge of the semiconductor element mounted on the portion when viewed from above, and a heat dissipation pattern provided on the second surface.

  In the semiconductor device, the semiconductor element may be mounted on the wiring pattern by bonding the electrode and the wiring pattern by Au—Sn alloy bonding or Au—Au alloy bonding. The electrode and the wiring pattern may be connected by a film or an anisotropic conductive adhesive paste and mounted on the wiring pattern.

In order to achieve the above object, the present invention provides an insulating film having a first surface and a second surface opposite to the first surface, and a predetermined position on the first surface of the insulating film. An inner lead on which a semiconductor element is mounted and an outer lead provided on the opposite side of the inner lead, covering a wiring pattern formed of copper and an intermediate region between the inner lead and the outer lead, A plurality of feeds penetrating from the first surface to the second surface, provided at both ends of the first surface along the direction from the inner lead to the outer lead. Reinforcing frame having holes, and an upper surface of the semiconductor element mounted on the inner lead portion in a region visible from the second surface on the second surface corresponding to the region immediately below the region where the semiconductor element is mounted Visual Has a definitive larger open regions than the outer edge, the outer edge on a part of the second surface is provided in a rectangular shape, the semiconductor device tape carrier and a heat radiation pattern formed of copper is provided .

  According to the tape carrier for a semiconductor device of the present invention, the heat generated in the semiconductor element can be efficiently dissipated. According to the method for manufacturing the tape carrier for a semiconductor device of the present invention, the heat generated in the semiconductor element can be efficiently A tape carrier for a semiconductor device that can dissipate heat well can be provided. Furthermore, a semiconductor device having such a tape carrier for a semiconductor device can be provided.

[First Embodiment]
FIG. 1A shows a perspective view of the surface of the tape carrier for a semiconductor device according to the first embodiment of the present invention, and FIG. 1B shows the semiconductor device according to the first embodiment. The perspective view of the back surface of the tape carrier for medical use is shown.

(Configuration of tape carrier 1 for semiconductor device)
The tape carrier 1 for a semiconductor device according to the first embodiment includes an insulating film 10 having a first surface and a second surface opposite to the first surface, and a first surface of the insulating film 10. And a wiring pattern 13 including a plurality of wirings having an inner lead 12 and an outer lead 14, and a solder resist 16 provided in a predetermined region between the inner lead 12 and the outer lead 14. Further, the semiconductor device tape carrier 1 includes a plurality of gaps at predetermined intervals along a direction from the inner lead 12 to the outer lead 14 or from the outer lead 14 to the inner lead 12 (or a direction perpendicular to the direction). A reinforcing frame 18 having a feed hole 18a and provided at both ends of the first surface, and a heat radiation pattern 20 having an opening region 22 and provided on the second surface are provided.

  The insulating film 10 is formed to have a first surface and a second surface opposite to the first surface. The insulating film 10 is formed from an insulating material having a predetermined thickness. As an example, the insulating material is a polyimide resin. The insulating material is not limited to polyimide resin as long as it is a material that exhibits good flexibility and heat dissipation as a COF tape. The insulating film 10 is formed to have a predetermined thickness or less (for example, 38 μm or less) for the purpose of exhibiting good flexibility and heat dissipation as a COF tape.

  The wiring pattern 13 is formed on the first surface of the insulating film 10. Specifically, the wiring pattern 13 has a plurality of wires including an inner lead 12 and an outer lead 14 provided on the opposite side of the extending direction of the inner lead 12. The distances between the inner leads 12 of each wiring are set to be narrower than the distances between the outer leads 14 of each wiring, and are arranged at predetermined positions on the first surface. As an example, two wiring patterns 13 are provided on the first surface. Then, two wiring patterns 13 are provided on the first surface with the inner leads 12 of one wiring pattern 13 and the inner leads 12 of the other wiring pattern 13 facing each other at a predetermined distance.

  For example, the wiring pattern 13 includes a copper layer having a thickness of about 8 μm plated on the surface of the resin film 10 via a Cr sputter layer. In addition, the wiring pattern 13 can also be comprised from the copper alloy material containing copper and another metal material. Alternatively, the wiring pattern 13 includes an inner layer formed of copper, and can be configured by forming a metal material such as tin as an outer layer on the surface of the inner layer. The outer layer can be formed by surface plating. The inner lead 12 is a portion where a semiconductor element is mounted. Specifically, the electrode of the semiconductor element and the inner lead 12 are electrically connected. The outer lead 14 is a portion that is electrically connected to an external circuit. A metal layer having a predetermined reflectance with respect to a predetermined wavelength can be formed between the wiring pattern 13 and the first surface.

  The solder resist 16 as a heat resistant coating agent is provided on the first surface so as to cover an intermediate region between the inner lead 12 and the outer lead 14. As an example, the solder resist 16 can be formed from a polyimide heat-resistant resin material having insulating properties.

  The reinforcing frame 18 is provided at each end of the insulating film 10 with a predetermined width. The reinforcing frame 18 is provided at both ends of the first surface along the direction from the inner lead 12 to the outer lead 14, for example. Each reinforcing frame 18 has a plurality of feed holes 18a penetrating from the first surface to the second surface at a predetermined interval. The reinforcing frame 18 is made of, for example, a copper layer having a predetermined thickness.

  The heat dissipation pattern 20 has an opening region 22 on the second surface facing at least a portion of the wiring pattern 13 and is provided on at least a portion of the second surface. The heat radiation pattern 20 is formed in a rectangular shape in a top view, for example, from a copper layer (solid copper) having a thickness of about 8 μm or a layer of a copper alloy material. The heat radiation pattern 20 can also be formed thicker (for example, 8 μm or more) than the wiring pattern 13 for the purpose of improving the heat radiation property of the tape carrier 1 for semiconductor devices. Furthermore, the heat radiation pattern 20 may be plated on the surface using a predetermined metal material such as tin.

  Further, the heat radiation pattern 20 can be formed in a rectangular shape having an outer edge having a length L1 and a width W1. Here, the relationship between the length and the width satisfies L1> W1 or L1 = W1 or L1 <W1. L1 and W1 are formed at least larger than the outer edge of the semiconductor element mounted on the inner lead 12 in a top view. In addition, the thickness of the heat radiation pattern 20 can be formed to a thickness of 8 μm or more for the purpose of improving the heat radiation performance of the heat radiation pattern 20. Specifically, the heat dissipation pattern 20 includes an opening region 22 on the second surface corresponding to a region immediately below the region where the semiconductor element is mounted, has a rectangular outer edge, and is partly on the second surface. Provided. In the present embodiment, the wiring pattern 13 and the heat dissipation pattern 20 are not electrically connected.

  The opening region 22 is provided with the opening region 22 on the second surface facing a part of the wiring pattern 13 on which the semiconductor element is mounted. The opening region 22 is formed in a rectangular shape as an example when viewed from above. Each corner of the rectangle can be formed to include an arc having a predetermined curvature. The arcs are provided at a part of the four corners of the opening region 22 (for example, one of the four corners or one corner and another corner positioned opposite to the one corner). Can be used to align or align the semiconductor element 200 with respect to the substrate. The opening region 22 is provided in a region of the wiring pattern 13 where at least a part of the inner lead 12 is visible from the second surface. Here, “visible” includes, for example, the meaning that it is visible through the insulating film 10 from the second surface in an apparatus for optical automatic appearance inspection (Automatic Optical Inspection: AOI).

  Further, the opening region 22 can be provided on the second surface corresponding to the portion immediately below the semiconductor element mounted on the inner lead 12 of the wiring pattern 13 according to the shape of the semiconductor element in a top view. For example, the opening region 22 can be formed to be substantially the same as the outer edge of the shape of the semiconductor element in a top view or a size that is a predetermined multiple of the outer edge. For example, the opening region 22 has a length L2 and can be formed as a width W2. Here, the relationship between the length and width of the opening region 22 satisfies L2> W2 or L2 = W2 or L2 <W2. Furthermore, the relationship of L1> L2 and W1> W2 is satisfied. Note that L2 and W2 are formed at least larger than the outer edge of the semiconductor element mounted on the inner lead 12 in a top view.

  Further, in the modified example of the first embodiment, the surface of the second surface corresponding directly below the inner lead 12 is exposed to form the opening region 22, and the heat radiation pattern 20 is formed between the inner leads 12. The heat radiation pattern 20 and the opening region 22 can be provided by arranging them. In this case, the heat radiation pattern 20 is provided in a comb shape toward the opening region 22.

  2A shows a cross section taken along line AA of FIG. 1A of the tape carrier for a semiconductor device according to the first embodiment of the present invention, and FIG. 2B shows the first embodiment. The cross section in the BB line of Fig.1 (a) of the tape carrier for semiconductor devices which concerns on the form of is shown.

  Referring to FIG. 2A, each wiring pattern 13 is provided on the insulating film 10 at a predetermined interval. And by covering a part on the wiring pattern 13 with the solder resist 16, the insulation resistance between each wiring improves, and the mechanical strength of the tape carrier 1 for semiconductor devices improves.

  Reference is made to FIG. The inner lead 12 on the first surface facing the opening region 22 surrounded by the heat radiation pattern 20 is a direction from the end of the opening region 22 toward the center of the opening region 22 along the surface of the first surface. Protruding to form. That is, the inner lead 12 is formed at a position where the end portion of the inner lead 12 is visible from the opening region 22.

  FIG. 3 shows a cross section of a semiconductor device in which a semiconductor element is mounted on the tape carrier for a semiconductor device according to the first embodiment of the present invention.

  The semiconductor device 2 according to the present embodiment is configured by mounting a semiconductor element 200 having a plurality of electrodes on the inner leads 12 of the wiring pattern 13 via bumps 90. The semiconductor element 200 as the heating element is, for example, an LCD driver IC. As can be seen with reference to FIG. 3, the heat dissipation pattern 20 according to the present embodiment has an opening region 22 in a region on the second surface including the second surface corresponding directly below the semiconductor element 200. That is, in the present embodiment, the heat radiation pattern 13 is not provided immediately below the semiconductor element 200 as a heating element.

  The bump 90 can be formed from an alloy material. As an example, the bump 90 uses an Au—Sn alloy as a bonding material. Specifically, an Au—Sn alloy layer is provided on the electrode of the semiconductor element 200 or on the surface of the inner lead 12, or on the electrode of the semiconductor element 200 and on the surface of the inner lead 12, and the electrode and the inner lead 12 are brought into contact with each other. Then, heat treatment (or heat treatment and pressure treatment) at a predetermined temperature is performed. Thereby, the semiconductor element 200 is mounted on the wiring pattern 13 via the bumps 90.

  In addition, an Au layer is formed on the outermost surface of the electrode of the semiconductor element 200 and an Au layer is formed on the outermost surface of the inner lead 12, and the Au—Au is formed between the Au layer of the electrode and the Au layer of the inner lead 12. The semiconductor element 200 can be mounted on the wiring pattern 13 by alloy bonding. In this case, Au—Au functions as a bonding material.

  When the semiconductor element 200 is bonded to the inner lead 12 by Au—Sn alloy bonding or Au—Au alloy bonding, the eutectic temperature of Au—Sn alloy and the temperature at which Au and Au are bonded are determined by solder materials such as Pb-containing solder. Higher than that. Accordingly, by providing the opening region 22 on the second surface corresponding to at least the portion of the inner lead 12 that is joined to the electrode of the semiconductor element 200, the heat supplied to the inner lead 12 in contact with the electrode and the electrode is Since heat is efficiently transferred to the bonding material existing between the electrode and the inner lead 12, the bonding between the electrode of the semiconductor element 200 and the inner lead 12 is facilitated.

  When the semiconductor element 200 is mounted on the narrow pitch inner leads 12, an anisotropic conductive adhesive film formed of a material in which conductive particles are uniformly dispersed in an insulating adhesive as the bump 90 or An anisotropic conductive adhesive paste can also be used. By using the anisotropic conductive adhesive film or the anisotropic conductive adhesive paste, the conductive particles in the adhesive do not protrude from the side of the inner lead 12, and a short circuit between the inner leads 12 can be prevented.

  4 to 6 show a manufacturing process of the tape carrier for a semiconductor device according to the first embodiment of the present invention.

  First, reference is made to FIG. First, an insulating film 10 having a first surface and a second surface and serving as a resin tape formed from a polyimide resin is prepared (insulating film preparation step). Then, a Cr sputter layer as the first metal layer 32 is formed by sputtering on both the first surface and the second surface of the insulating film 10. Subsequently, copper plating as the second metal layer 34 is performed on the Cr sputter layer. Thereby, the metal layer 30 is formed on both surfaces of the insulating film 10 (base material formation process with a double-sided copper layer).

  Next, as shown in FIG. 4B, a resist is applied to each of the surfaces of the metal layer 30 by spin coating or the like to form a resist layer 40 having a predetermined thickness (resist coating step). Subsequently, the resist layer 40 formed on one surface of the metal layer 30 is exposed through a photomask for positive resist or a photomask for negative resist having a wiring pattern of a desired shape. As a result, as shown in FIG. 4C, when the resist layer 40 is a positive resist, a resist film 40a (a portion not exposed by the mask) is formed as a non-exposed portion, and the resist layer 40 is a negative type. In the case of a resist, a resist film 40a (a portion exposed by the absence of a mask) is formed as an insoluble portion.

  Similarly, the resist layer 40 formed on the other surface of the metal layer 30 is exposed through a photomask for positive resist or a photomask for negative resist having a heat radiation pattern of a desired shape. Thus, as shown in FIG. 4C, when the resist layer 40 is a positive resist, a resist film 40b is formed as a non-exposed portion. When the resist layer 40 is a negative resist, a resist as an insoluble portion is formed. A film 40b is formed (exposure process). In this embodiment, the exposure process is first performed on the wiring pattern side having a higher definition pattern.However, when forming a wiring pattern that does not require a higher definition pattern, the exposure process is performed first on the heat radiation pattern side. It can also be applied.

  Next, the exposed resist layer 40 is developed using a predetermined developer (development process). As a result, as shown in FIG. 5D, resist films 40a and 40b are formed on the second metal layer 34 on which the wiring pattern and the heat dissipation pattern are formed (resist pattern forming step). Although not shown, a resist pattern for the reinforcing frame 18 provided at both ends of the first surface of the insulating film 10 is also formed in the resist pattern forming step. The resist pattern for the reinforcing frame 18 is formed so as to have an opening corresponding to the shape of the feed hole 18a at a portion where the plurality of feed holes 18a are formed. Subsequently, in a state where the resist films 40a and 40b are present on the second metal layer 34, an etching process is performed using a predetermined etchant. As a result, as shown in FIG. 5E, the first metal layer 32 and the second metal layer 34 except for the region immediately below the region where the resist films 40a and 40b are formed are removed (etching step). Then, as shown in FIG. 5F, the resist films 40a and 40b are removed (resist removal step).

  Next, as shown in FIG. 6G, after the resist films 40a and 40b are removed, a predetermined cleaning process is performed, whereby the first metal layer 32 and the second metal layer 32 are formed on the first surface of the insulating film 10. A pattern for a wiring pattern composed of the metal layer 34 is formed, and a pattern for a heat radiation pattern composed of the first metal layer 32 and the second metal layer 34 is formed on the second surface (cleaning step). . In addition, the pattern of the reinforcement frame 18 which has an opening part in the area | region in which the several feed hole 18a is formed is formed by passing through a washing | cleaning process (not shown). Subsequently, predetermined metal plating is performed on the first metal layer 32 and the second metal layer 34 formed on the first surface and the second surface, respectively (metal plating step).

  Then, by removing unnecessary residual components such as plating solution, as shown in FIG. 6H, the wiring pattern 13 is formed on the first surface and the heat radiation pattern 20 is formed on the second surface. (Wiring pattern forming process, heat radiation pattern forming process). Further, a plurality of feed holes 18 a are formed by forming through holes in the openings of the reinforcing frame 18. The process of forming the plurality of feed holes 18a is not limited to after the pattern formation process and the heat dissipation pattern formation process, and can be performed at an appropriate timing such as before the base material formation process with a double-sided copper layer. The plated layer 50 may be an Sn plated layer as an example when the purpose is to easily and reliably connect the IC chip as the semiconductor element 200 and the liquid crystal glass.

  Then, the solder resist 16 is printed in a predetermined area of the wiring pattern 13 (solder resist printing process). Thus, the semiconductor device tape carrier 1 according to the first embodiment is manufactured. The semiconductor device tape carrier 1 obtained after the solder resist printing process is shipped as a product through a predetermined inspection process.

(Effects of the first embodiment)
According to the tape carrier 1 for a semiconductor device according to the first embodiment of the present invention, the heat radiation pattern 20 is not provided on the second surface of the insulating film 10 corresponding to the region where the semiconductor element 200 is mounted. When the semiconductor element 200 is mounted, the inner lead 12 can be recognized from the second surface side.

  Further, according to the tape carrier 1 for a semiconductor device according to the first embodiment, the opening region 22 is formed on the second surface corresponding to the region where the inner lead 12 is provided. The heat is not easily dissipated. Therefore, since heat efficiently propagates to the bonding material between the electrode of the semiconductor element 200 and the inner lead 12 when the semiconductor element 200 is mounted, the semiconductor element 200 and the inner lead 12 can be reliably bonded.

  Moreover, according to the tape carrier 1 for semiconductor devices which concerns on 1st Embodiment, since the thermal radiation pattern 20 is not provided on the 2nd surface of the insulating film 10 corresponding to the area | region where the semiconductor element 200 is mounted, tape It is possible to easily detect defects such as fine protrusions and chips caused by transmitted light propagating from the second surface to the first surface during inspection (for example, optical automatic appearance inspection (AOI)).

  Furthermore, according to the tape carrier 1 for a semiconductor device according to the first embodiment, since the heat radiation pattern 20 is provided on a part of the second surface, the heat radiation pattern 20 is provided on the second surface of the insulating film 10. As compared with the case where the tape carrier 1 is not provided, the heat dissipation characteristics of the semiconductor device tape carrier 1 can be improved.

[Second Embodiment]
FIG. 7 shows a cross section of a tape carrier for a semiconductor device according to the second embodiment of the present invention.

  The tape carrier for a semiconductor device according to the second embodiment is different from the first embodiment except that the wiring pattern 13 and the heat radiation pattern 20 are connected by a filler 70 that fills the via 60. The semiconductor device tape carrier 1 according to the present invention has substantially the same configuration. Therefore, except for the differences, detailed description is omitted.

  In the tape carrier 1a for a semiconductor device according to the second embodiment, the wiring pattern 13 and the heat radiation pattern 20 are connected by a filler 70 filled in a via 60 provided in the insulating film 10. For example, the via 60 is formed in a part of the insulating film 10 by laser processing, punching processing, or the like. And the filler 70 is a copper material formed by giving copper plating to the via 70 as an example. In the present embodiment, since it is not essential to electrically connect the wiring pattern 13 and the heat dissipation pattern 20, the filler 70 may be a metal material such as aluminum or tungsten, an organic material such as silicone, or the like. It can be formed from a material having high thermal conductivity such as an insulating material.

  The semiconductor tape carrier 1a according to the second embodiment is manufactured as follows, for example. First, an insulating film with vias in which fine holes are formed in advance at a predetermined position of the insulating film 10 by laser processing or punching processing is prepared. Then, copper plating is performed on the insulating film with vias, thereby forming copper layers on both sides of the film and filling the vias with copper. Subsequent processes are the same as those in the method for manufacturing the semiconductor tape carrier 1 according to the first embodiment in the above description of FIGS.

[Third Embodiment]
8 and 9 show a manufacturing process of a tape carrier for a semiconductor device according to the third embodiment of the present invention.

  First, reference is made to FIG. First, an insulating film 10 having a first surface and a second surface and serving as a resin tape formed from a polyimide resin is prepared (insulating film preparation step). Then, a Cr sputter layer as the first metal layer 32 is formed on the first surface of the insulating film 10 by sputtering. Subsequently, copper plating as the second metal layer 34 is performed on the Cr sputter layer. A reinforcing tape 80 is bonded to the second surface. Thereby, the metal layer 30 is formed in one surface of the insulating film 10 (base material formation process with a single-sided copper layer).

  Next, a resist is applied to the surface of the metal layer 30 by spin coating or the like to form a resist layer 40 having a predetermined thickness (resist coating step). Subsequently, the resist layer 40 formed on the surface of the metal layer 30 is exposed through a photomask for positive resist or a photomask for negative resist having a wiring pattern of a desired shape. Thus, as shown in FIG. 8B, when the resist layer 40 is a positive resist, as shown in FIG. 8B, a resist film 40a as a non-exposed portion is formed, and when the resist layer 40 is a negative resist, A resist film 40a is formed as an insoluble portion.

  Next, the exposed resist layer 40 is developed using a predetermined developer (development process). Thereby, as shown in FIG. 8C, a resist film 40a is formed on the second metal layer 34 on which the wiring pattern is formed (resist pattern forming step). Subsequently, in a state where the resist film 40a exists on the second metal layer 34, an etching process is performed using a predetermined etchant. As a result, as shown in FIG. 8D, the first metal layer 32 and the second metal layer 34 except for the region immediately below the region where the resist film 40a is formed are removed (etching step). Subsequently, the resist film 40a is removed (resist removal step).

  Subsequently, as shown in FIG. 9E, predetermined metal plating is performed on the first metal layer 32 and the second metal layer 34 formed on the first surface (metal plating step). As the plating layer 50, an Sn plating layer can be used as in the first embodiment. Then, after the metal plating step, the reinforcing tape 80 is peeled off. Then, as shown in FIG. 9F, a solder resist 16 is printed in a predetermined region of the wiring pattern 13 (solder resist printing process).

  Subsequently, as shown in FIG. 9G, a heat radiation pattern 20 (a heat radiation pattern with an adhesive) formed in advance in a shape having an opening region 22 in a portion corresponding to a region immediately below the region where the semiconductor element 200 is mounted. ) Thereby, as shown in FIG. 9H, the semiconductor tape carrier according to the third embodiment is manufactured. In addition, a heat dissipation pattern with an adhesive can be configured, for example, by forming a copper layer on a film formed from a predetermined adhesive and forming a heat dissipation pattern of a desired shape on the copper layer.

[ Reference example]
FIGS. 10A to 10C show the shape of the heat radiation pattern according to the reference example of the present invention.

  FIG. 10A shows a semiconductor device tape carrier 1b in which the heat radiation pattern 20a has a plurality of opening regions 22a and 22b. Each of the opening regions 22a and 22b is provided in a region including the second surface corresponding to a position directly below the inner lead 12 provided on the first surface. Since the opening regions 22a and 22b shown in FIG. 10A are located immediately below the inner lead 12, when the semiconductor element 200 is mounted on the wiring pattern 13, heat can be easily concentrated on the inner lead 12.

  FIG. 10B shows a semiconductor device tape carrier 1c in which the heat radiation pattern 20b has a plurality of opening regions 22c formed in the direction along the reinforcing frame 18 with the longitudinal direction. Each of the plurality of opening regions 22 c is provided on a second surface corresponding to a portion directly below a part of the inner lead 12. That is, in the opening region 22 according to the first embodiment, all the inner leads 12 can be recognized from the second surface toward the first surface, but the opening according to the tape carrier 1c for a semiconductor device. In the region 22c, only a part of the inner lead 12 can be recognized. This makes it possible to recognize only the portion of the inner lead 12 that is essential to be confirmed in the mounting of the semiconductor element 200 from the second surface and to improve the heat dissipation characteristics.

  FIG. 10C shows a semiconductor device tape carrier 1d in which the heat dissipation pattern 20c has a plurality of circular opening regions 22d. Each of the plurality of circular opening regions 22 d is provided on the second surface corresponding to a position directly below the inner lead 12. The plurality of opening regions 22d are provided at intervals at which the inner leads 12 can be recognized from the second surface. Thereby, the heat dissipation characteristic is improved as compared with the opening region 22 according to the first embodiment.

The embodiment and the reference example of the present invention have been described above. However, the embodiment and the reference example described above do not limit the invention according to the claims. It should be noted that not all the combinations of features described in the embodiments and the reference examples are necessarily essential to the means for solving the problems of the invention.

(A) is a perspective view of the surface of the tape carrier for semiconductor devices which concerns on 1st Embodiment, (b) is a perspective view of the back surface of the tape carrier for semiconductor devices which concerns on 1st Embodiment. is there. (A) is sectional drawing in the AA of FIG. 1 (a) of the tape carrier for semiconductor devices which concerns on 1st Embodiment, (b) is the semiconductor device which concerns on 1st Embodiment. It is sectional drawing in the BB line of FIG. It is sectional drawing of the semiconductor device which mounted the semiconductor element in the tape carrier for semiconductor devices which concerns on 1st Embodiment. It is a figure which shows the manufacturing process of the tape carrier for semiconductor devices which concerns on 1st Embodiment. It is a figure which shows the manufacturing process of the tape carrier for semiconductor devices which concerns on 1st Embodiment. It is a figure which shows the manufacturing process of the tape carrier for semiconductor devices which concerns on 1st Embodiment. It is sectional drawing of the tape carrier for semiconductor devices which concerns on 2nd Embodiment. It is a figure which shows the manufacturing process of the tape carrier for semiconductor devices which concerns on 3rd Embodiment. It is a figure which shows the manufacturing process of the tape carrier for semiconductor devices which concerns on 3rd Embodiment. (A)-(c) is a figure which shows the shape of the thermal radiation pattern which concerns on a reference example.

Explanation of symbols

1, 1a, 1b Semiconductor device tape carrier 2 Semiconductor device 10 Insulating film 12 Inner lead 13 Wiring pattern 14 Outer lead 16 Solder resist 18 Reinforcing frame 18a Feed hole 20, 20a, 20b, 20c Heat radiation pattern 22, 22a, 22b, 22c 22d Open region 30 Metal layer 32 First metal layer 34 Second metal layer 40 Resist layer 40a, 40b Resist film 50 Plating layer 60 Via 70 Filler 80 Reinforcement tape 90 Bump 200 Semiconductor element

Claims (11)

An insulating film having a first surface and a second surface facing the first surface;
A wiring pattern provided at a predetermined position on the first surface of the insulating film and having an inner lead portion on which a semiconductor element is mounted;
An opening region on the second surface facing at least a part of the wiring pattern, and a heat dissipation pattern provided on the second surface,
The opening region is provided in a region where the inner lead portion is visible from the second surface, and is provided on the second surface corresponding to a position immediately below the semiconductor element mounted on the inner lead portion , The tape carrier for a semiconductor device, wherein the tape carrier is formed to be larger than an outer edge of the semiconductor element mounted on the inner lead portion in a top view . The insulating film has a via penetrating the first surface and the second surface at a position directly below a part of the wiring pattern and the heat dissipation pattern is provided,
The tape carrier for a semiconductor device according to claim 1, wherein the wiring pattern is connected to the heat dissipation pattern through the via. The tape carrier for a semiconductor device according to claim 2, wherein the wiring pattern is connected to the heat dissipation pattern through the via to be conductive. The tape carrier for a semiconductor device according to any one of claims 1 to 3, wherein the heat radiation pattern is formed with a film thickness of 8 µm or more. The tape carrier for a semiconductor device according to any one of claims 1 to 4, wherein the heat radiation pattern is formed of pure copper. The tape carrier for a semiconductor device according to claim 5, wherein the wiring pattern is formed by performing a surface plating process. An insulating film preparation step of preparing an insulating film having a first surface and a second surface facing the first surface;
A wiring pattern forming step of forming a wiring pattern having an inner lead portion on which a semiconductor element is mounted at a predetermined position on the first surface of the insulating film;
A heat dissipation pattern forming step of forming on the second surface a heat dissipation pattern having an opening region on the second surface facing at least a part of the wiring pattern,
In the heat radiation pattern forming step, the opening region is provided in a region where the inner lead portion is visible from the second surface, and the second region corresponding to a position directly below the semiconductor element mounted on the inner lead portion. A method of manufacturing a tape carrier for a semiconductor device, comprising: providing an opening region formed larger than an outer edge of the semiconductor element mounted on the inner lead portion as viewed from above. A semiconductor element having an electrode;
An insulating film having a first surface and a second surface facing the first surface;
A wiring pattern having an inner lead portion provided at a predetermined position on the first surface of the insulating film and mounted by bonding the semiconductor element via the electrode;
An opening region formed on the second surface facing at least a part of the wiring pattern that is larger than an outer edge in a top view of the semiconductor element mounted on the inner lead portion; A semiconductor device comprising a heat dissipation pattern provided on the semiconductor device. The semiconductor device according to claim 8, wherein the semiconductor element is mounted on the wiring pattern by bonding the electrode and the wiring pattern by Au—Sn alloy bonding or Au—Au alloy bonding. The semiconductor device according to claim 8, wherein the semiconductor element is mounted on the inner lead portion by connecting the electrode and the inner lead portion with an anisotropic conductive adhesive film or an anisotropic conductive adhesive paste. An insulating film having a first surface and a second surface facing the first surface;
A wiring pattern which is provided at a predetermined position on the first surface of the insulating film, has an inner lead on which a semiconductor element is mounted, and an outer lead provided on the opposite side of the inner lead, and is formed from copper When,
A solder resist that covers an intermediate region between the inner lead and the outer lead and is provided in contact with the first surface;
A reinforcing frame provided at both ends of the first surface along the direction from the inner lead to the outer lead, and having a plurality of feed holes penetrating from the first surface to the second surface;
A top view of the semiconductor element mounted on the inner lead portion in a region where the inner lead portion is visible from the second surface on the second surface corresponding to the region immediately below the region where the semiconductor element is mounted. A tape carrier for a semiconductor device, comprising: an opening region formed larger than the outer edge ; a part of the second surface having a rectangular outer edge, and a heat dissipation pattern formed of copper.

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