JP2010197134A - Board inspecting jig - Google Patents

Board inspecting jig Download PDF

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JP2010197134A
JP2010197134A JP2009040485A JP2009040485A JP2010197134A JP 2010197134 A JP2010197134 A JP 2010197134A JP 2009040485 A JP2009040485 A JP 2009040485A JP 2009040485 A JP2009040485 A JP 2009040485A JP 2010197134 A JP2010197134 A JP 2010197134A
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inspection
board
substrate
inspected
selection circuit
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Hiroatsu Nomura
浩功 野村
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Toppan Inc
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Toppan Printing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To carry out an electric inspection of a board to be inspected without increasing its board inspecting jigs and inspection frequencies even when the number of channels of a scanner of a board electric inspection apparatus gets low. <P>SOLUTION: A board inspecting jig is used, which is composed of a probe pin for contacting with an inspection point of a wiring pattern of the board to be inspected by the board electric inspection apparatus, and a connector having a terminal for electrically connecting with the probe pin, and which is characterized by including a choosing circuit for, in turn, choosing one among a plurality of probe pins and electrically connecting it to one terminal of the connector, thereby reducing the number of channels to be connected to the scanner of the board electric inspection apparatus. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、プリント配線板などの被検査基板に形成された配線パターンの導通を電気的に検査する基板電気検査装置の基板検査治具に関するものである。   The present invention relates to a board inspection jig for an electric board inspection apparatus for electrically inspecting the continuity of a wiring pattern formed on a board to be inspected such as a printed wiring board.

複数の配線パターン2を有するプリント配線板(被検査基板)の導通検査は、検査対象となるパターンの端部に設けられた電極パッド等の検査点に電圧または電流を印加することでパターンの抵抗値を測定し、ある設定された閾値に対して良否判定が行われる。このような導通検査を行う装置としては、特許文献1のように被検査基板の複数の検査点に同時に針状のプローブピンを接触させ、電圧または電流を印加し検査を行うものが知られている。   The continuity inspection of a printed wiring board (substrate to be inspected) having a plurality of wiring patterns 2 is performed by applying a voltage or current to an inspection point such as an electrode pad provided at an end of the pattern to be inspected, thereby resistance of the pattern A value is measured, and a pass / fail judgment is performed for a certain threshold value. As an apparatus for performing such a continuity test, an apparatus is known in which a needle-like probe pin is simultaneously brought into contact with a plurality of inspection points of a substrate to be inspected and a voltage or a current is applied thereto as in Patent Document 1. Yes.

図1にこの基板電気検査装置で検査する被検査基板1の配線パターン2の一例を断面の模式図で示す。この配線パターン2には、被検査基板1の上面に101から106の6箇所の上側検査点と、下面に201から204の4箇所の下側検査点があるものとする。図1の被検査基板1では、検査すべき配線パターン2の回路網(ネット)が4つ存在している。回路網(ネット)とは、電気接続されて同電位となっている配線パターン2の群である。図1の被検査基板1の場合は、2点間の導通検査をする検査点の組み合わせは、201−101間、202−102間、202−103間、203−104間、203−105間、204−106間の6通りがある。この検査点間の導通検査は、検査点間が導通することをチェックする導通チェックと、検査点間が絶縁されていることをチェックする絶縁チェックのために導通を検査するものである。   FIG. 1 is a schematic cross-sectional view showing an example of a wiring pattern 2 of a substrate 1 to be inspected by this board electrical inspection apparatus. The wiring pattern 2 has six upper inspection points 101 to 106 on the upper surface of the substrate 1 to be inspected and four lower inspection points 201 to 204 on the lower surface. In the inspected substrate 1 in FIG. 1, there are four circuit networks (nets) of the wiring pattern 2 to be inspected. The circuit network (net) is a group of wiring patterns 2 that are electrically connected and have the same potential. In the case of the inspected substrate 1 in FIG. 1, the combination of inspection points for conducting a continuity test between two points is between 201-101, 202-102, 202-103, 203-104, 203-105, There are 6 ways between 204-106. This continuity test between inspection points is a continuity check for checking continuity between inspection points and an insulation check for checking that the inspection points are insulated.

図2は図1の被検査基板1を検査する基板電気検査装置の模式図である。被検査基板1の各上側検査点101〜106に接触させる上側治具プローブピン301から306が割り当てられ、各下側検査点201〜204に接触させる下側治具プローブピン401から404が割り当てられ、各プローブピンの先端は各検査点に正確に接触するよう支持体3によって支持されている。各プローブピンの他端は信号ケーブルと導通しており、基板検査治具の支持板4に取り付けられたコネクタ5を介してスキャナ6に接続され、検査対象の信号が順次選択される。選択された信号には直流電流源7によって電流が印加され、電圧計8で電圧を測定することで抵抗値を算出する。このプローブピンと支持体3と支持板4とコネクタ5とが一体となった構造物が基板検査治具である。   FIG. 2 is a schematic diagram of a board electrical inspection apparatus for inspecting the board 1 to be inspected in FIG. Upper jig probe pins 301 to 306 to be brought into contact with the respective upper inspection points 101 to 106 of the substrate 1 to be inspected are assigned, and lower jig probe pins 401 to 404 to be brought into contact with the respective lower inspection points 201 to 204 are assigned. The tip of each probe pin is supported by the support 3 so as to accurately contact each inspection point. The other end of each probe pin is electrically connected to the signal cable, and is connected to the scanner 6 via the connector 5 attached to the support plate 4 of the board inspection jig, and signals to be inspected are sequentially selected. A current is applied to the selected signal by the DC current source 7, and the resistance value is calculated by measuring the voltage with the voltmeter 8. A structure in which the probe pin, the support 3, the support plate 4, and the connector 5 are integrated is a substrate inspection jig.

特開2008−281406号公報JP 2008-281406 A

プリント配線板においても最近は高密度化が進み、それに伴いプリント配線板(被検査基板1)の検査点も以前と比べ増加している。これに対し基板検査治具は被検査基板1ごとに検査点の数と位置が相違するため、被検査基板1ごとに専用に作製する。基板検査治具は、被検査基板1の検査点が増せばプローブピンを検査点の数だけ増して設置して製造する。一方、基板電気検査装置のスキャナ6はチャンネル数を固定したスキャナ6を用いるので、チャンネル数が不足する場合がある。そのような場合の対処方法は以下の手法で対処していた。(a)基板検査治具を複数台準備し検査を複数回実行することによって対処する方法。この手法では、工数増加及びコストアップにつながるという欠点がある。(
b)スキャナ6の増設によっても対処する方法。この手法では、スキャナ6は非常に高額な部品でありこれもコストアップにつながてしまう欠点がある。特許文献1に記載された方法では、検査時間の短縮はできるものの、スキャナ6のチャンネル数が不足した場合には基板検査治具を複数台準備し複数回検査を行わなければならず、工数が増加しコストアップする欠点がある。
In recent years, the density of printed wiring boards has been increasing, and the number of inspection points for printed wiring boards (board 1 to be inspected) has increased accordingly. On the other hand, since the number and position of the inspection points are different for each substrate 1 to be inspected, the substrate inspection jig is produced exclusively for each substrate 1 to be inspected. The board inspection jig is manufactured by increasing the number of probe pins by the number of inspection points when the number of inspection points of the inspected substrate 1 increases. On the other hand, since the scanner 6 of the board electrical inspection apparatus uses the scanner 6 with a fixed number of channels, the number of channels may be insufficient. In such cases, the following method was used. (A) A method for coping with by preparing a plurality of substrate inspection jigs and executing the inspection a plurality of times. This method has a drawback that it leads to an increase in man-hours and cost. (
b) A method of coping with the addition of the scanner 6. In this method, the scanner 6 is a very expensive part, which also has a drawback of increasing the cost. In the method described in Patent Document 1, although the inspection time can be shortened, when the number of channels of the scanner 6 is insufficient, a plurality of substrate inspection jigs must be prepared and inspected a plurality of times. There is a drawback that the cost increases.

そこで本発明は、基板電気検査装置のスキャナ6のチャンネル数が不足した場合でも基板検査治具の増加および検査回数の増加をせずに被検査基板1の電気検査を行えるようにすることを課題とする。   SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to perform an electrical inspection of a substrate 1 to be inspected without increasing the number of substrate inspection jigs and increasing the number of inspections even when the number of channels of the scanner 6 of the substrate electrical inspection apparatus is insufficient. And

上記の課題を解決するために、本発明は、基板電気検査装置で検査する被検査基板の配線パターンの検査点に接触させるプローブピンと前記プローブピンに電気接続する端子を有するコネクタとから構成される基板検査治具であって、複数の前記プローブピンのうちの一つを順番に選択して前記コネクタの1つの端子に電気接続させる選択回路を有することを特徴とする基板検査治具である。   In order to solve the above-mentioned problems, the present invention is composed of a probe pin that is brought into contact with an inspection point of a wiring pattern of a substrate to be inspected by a substrate electrical inspection apparatus and a connector having a terminal that is electrically connected to the probe pin A board inspection jig comprising a selection circuit that sequentially selects one of the plurality of probe pins and electrically connects to one terminal of the connector.

また、本発明は、上記の基板検査治具であって、上記選択回路が半導体集積回路から成ることを特徴とする基板検査治具である。   According to another aspect of the present invention, there is provided the substrate inspection jig, wherein the selection circuit is formed of a semiconductor integrated circuit.

また、本発明は、上記の基板検査治具であって、上記選択回路に接続するプローブピンは、複数の検査点を有するネットの1つの検査点に接触させるように配置し、上記選択回路を介さずに上記コネクタの端子に接続するプローブピンの少なくとも1つを前記ネットの他の検査点に接触させるように配置したことを特徴とする基板検査治具である。   Further, the present invention is the above board inspection jig, wherein the probe pin connected to the selection circuit is disposed so as to contact one inspection point of a net having a plurality of inspection points, and the selection circuit is arranged. The board inspection jig is characterized in that at least one of the probe pins connected to the terminal of the connector without being interposed is arranged so as to contact another inspection point of the net.

本発明によれば、被検査基板1の検査点数が基板電気検査装置のスキャナ6のチャンネル数を越えた場合であっても、基板検査治具および検査回数の増加を抑制することができる。またスキャナ6の増設に伴うコストアップを抑制することができる。   According to the present invention, even when the number of inspection points of the inspected substrate 1 exceeds the number of channels of the scanner 6 of the substrate electrical inspection apparatus, it is possible to suppress an increase in the substrate inspection jig and the number of inspections. In addition, an increase in cost associated with the addition of the scanner 6 can be suppressed.

被検査基板の断面の模式図である。It is a schematic diagram of the cross section of a to-be-inspected board | substrate. 被検査基板を検査する基板検査治具および基板電気検査装置の模式図である。It is a schematic diagram of a substrate inspection jig and a substrate electrical inspection apparatus for inspecting a substrate to be inspected. 本発明の実施例の基板検査治具の模式図である。It is a schematic diagram of the board | substrate inspection jig | tool of the Example of this invention. 本発明の実施例の基板検査治具に搭載する選択回路の回路図である。It is a circuit diagram of the selection circuit mounted in the board | substrate inspection jig | tool of the Example of this invention. 本発明の実施例の選択回路の動作のタイミングチャートである。It is a timing chart of operation | movement of the selection circuit of the Example of this invention.

本発明を実施するための形態を図3から図5を用いて説明する。図3に、本実施形態の基板検査治具を示す。本実施形態では、この基板検査治具を接触させる被検査基板1の検査点が10箇所あるものとした場合に、スキャナ6のチャンネル数が、その検査点の数より少ない6個のチャンネル数しかない場合における本発明の実施の形態を説明する。   A mode for carrying out the present invention will be described with reference to FIGS. FIG. 3 shows the substrate inspection jig of this embodiment. In this embodiment, when there are 10 inspection points of the substrate 1 to be inspected with which the substrate inspection jig is brought into contact, the number of channels of the scanner 6 is only six channels, which is smaller than the number of inspection points. An embodiment of the present invention in the case where there is no case will be described.

本実施形態の基板検査治具は、10箇所の検査点を検査するための10本のプローブピン501から510を有し、それらが支持体3で固定されている。プローブピンの他端は信号ケーブルに接続され、プローブピン501から505の信号端子は直接コネクタ5に電気接続し、検査時に基板電気検査装置のスキャナ6に電気接続する。一方、プローブピン506から510の信号端子は選択回路9の入力端子F506からF510に接続する。   The substrate inspection jig of this embodiment has 10 probe pins 501 to 510 for inspecting 10 inspection points, and these are fixed by the support 3. The other end of the probe pin is connected to a signal cable, and the signal terminals of the probe pins 501 to 505 are electrically connected directly to the connector 5 and are electrically connected to the scanner 6 of the board electrical inspection apparatus at the time of inspection. On the other hand, the signal terminals of the probe pins 506 to 510 are connected to the input terminals F506 to F510 of the selection circuit 9.

図4に選択回路9の回路図の一例を示す。選択回路9は、Clock信号で駆動するD−FF(フリップフロップ)回路10を、その出力端子をAND回路11の入力端子に接続し、AND回路11の他の入力端子に、Reset信号を反転したインバータ回路の出力端子を接続する。そしてAND回路11の出力端子を次段のD−FF回路10に接続することで、5段接続した5ビットのカウンタ回路を構成する。図5に示すようにReset信号およびClock信号を選択回路9に入力することで、5ビットのカウンタ回路の出力端子Q1からQ5の出力信号が順次H出力となる。   FIG. 4 shows an example of a circuit diagram of the selection circuit 9. The selection circuit 9 connects the output terminal of the D-FF (flip-flop) circuit 10 driven by the Clock signal to the input terminal of the AND circuit 11 and inverts the Reset signal to the other input terminal of the AND circuit 11. Connect the output terminal of the inverter circuit. Then, by connecting the output terminal of the AND circuit 11 to the D-FF circuit 10 in the next stage, a 5-bit counter circuit connected in five stages is configured. As shown in FIG. 5, when the Reset signal and the Clock signal are input to the selection circuit 9, the output signals from the output terminals Q1 to Q5 of the 5-bit counter circuit sequentially become H outputs.

選択回路9の5ビットのカウンタ回路の出力信号Q1からQ5を、各インバータ回路14の入力端子に接続し、また、カウンタ回路の出力信号Q1からQ5と各インバータ回路14の出力端子の逆相信号とをトランスファーゲート13のスイッチ制御信号入力端子に入力させる。トランスファーゲート13のスイッチ端子には、プローブピン506から510に接続する入力端子F506からF510を接続し、図5のS506からS510のタイミングでスイッチ制御信号入力端子にカウンタ回路の出力信号Q1からQ5を加えることで、トランスファーゲート13のスイッチ端子を順次、選択回路9の一本の出力端子T500に導通させる。そして、その出力端子T500を基板検査治具のコネクタ5の一本の端子に電気接続する。コネクタ5には、プローブピン501から505の信号端子に接続する5本の端子と、トランスファーゲート13の出力端子T500に接続する一本の端子との6本の端子を設ける。そして、基板検査治具のコネクタ5の6本の端子は、基板電気検査装置のスキャナ6の入力端子に接続され、順次導通検査を実施する。また、コネクタ5の端子は、更に、選択回路9の、駆動電源端子、Clock信号端子、Reset信号端子に接続する端子を加え、それらの端子もスキャナ6に接続することでトランスファーゲート13の切り替えをスキャナ6に制御させる。   The output signals Q1 to Q5 of the 5-bit counter circuit of the selection circuit 9 are connected to the input terminals of the inverter circuits 14, and the output signals Q1 to Q5 of the counter circuit and the reverse phase signals of the output terminals of the inverter circuits 14 Are input to the switch control signal input terminal of the transfer gate 13. The input terminals F506 to F510 connected to the probe pins 506 to 510 are connected to the switch terminal of the transfer gate 13, and the output signals Q1 to Q5 of the counter circuit are supplied to the switch control signal input terminal at the timing of S506 to S510 in FIG. In addition, the switch terminals of the transfer gate 13 are sequentially brought into conduction with one output terminal T500 of the selection circuit 9. Then, the output terminal T500 is electrically connected to one terminal of the connector 5 of the board inspection jig. The connector 5 is provided with six terminals including five terminals connected to the signal terminals of the probe pins 501 to 505 and one terminal connected to the output terminal T500 of the transfer gate 13. Then, the six terminals of the connector 5 of the board inspection jig are connected to the input terminals of the scanner 6 of the board electrical inspection apparatus, and the continuity inspection is sequentially performed. In addition, the terminals of the connector 5 are further connected to the drive power supply terminal, the clock signal terminal, and the reset signal terminal of the selection circuit 9, and these terminals are also connected to the scanner 6 to switch the transfer gate 13. The scanner 6 is controlled.

本発明では、選択回路9に接続する検査点は同時には1箇所のみが選択されるため、その検査点同士の導通検査ができない。この問題により、絶縁するべきネット同士の短絡不良をチェックする絶縁チェックが行われないことを回避するため、選択回路9の入力端子F506からF510に電気接続するプロ−ブピンは、それが接する検査点を、複数の検査点を含むネットの検査点に限定するように配置することが望ましい。その理由は、検査点が1箇所しかないネット2つを選択回路9に接続した場合、その2つのネット同士の導通検査ができないので、その2つのネット同士の絶縁チェックができず、絶縁チェックが完璧なものではなくなってしまう可能性があるからである。通常、被検査基板1の電気検査は導通チェックとともに絶縁チェックも実施される。絶縁チェックは、検査対象のネットがその他全てのネットに対し絶縁が保たれているかをチェックする。しかし選択回路9に接続する検査点同士では絶縁チェックが実施されない問題がある。この問題は、選択回路9に接続するプロ−ブピンの接触する検査点を電源またはグラウンドなど複数の検査点を持つ配線パターン2のネットの検査点に限定し、そのネットの複数の検査点のうち最低1点に接触するプローブピンは選択回路9を介さずにコネクタ5に接続するようにプローブピンを基板検査治具に配置することで回避できる。   In the present invention, since only one inspection point connected to the selection circuit 9 is selected at the same time, the continuity inspection between the inspection points cannot be performed. In order to avoid the fact that the insulation check for checking the short-circuit failure between the nets to be insulated is not performed due to this problem, the probe pin electrically connected to the input terminals F506 to F510 of the selection circuit 9 is the inspection point where it contacts. Is preferably arranged so as to be limited to inspection points of a net including a plurality of inspection points. The reason for this is that if two nets with only one inspection point are connected to the selection circuit 9, the continuity test between the two nets cannot be performed. This is because it may not be perfect. Usually, the electrical inspection of the substrate 1 to be inspected is performed with an insulation check as well as a continuity check. The insulation check checks whether the inspection target net is insulated from all other nets. However, there is a problem that the insulation check is not performed between the inspection points connected to the selection circuit 9. This problem is limited to the inspection points of the net of the wiring pattern 2 having a plurality of inspection points such as the power supply or the ground, and the inspection points that contact the probe pins connected to the selection circuit 9 are out of the plurality of inspection points of the nets. The probe pin that contacts at least one point can be avoided by arranging the probe pin on the board inspection jig so as to be connected to the connector 5 without going through the selection circuit 9.

また図4の選択回路9は、半導体電子回路が望ましく、省スペースを実現するためにはLSI部品とすることが特に望ましい。その場合、LSI部品におけるカウンタ回路の段数は任意としておき必要な段数だけ使用するようにすればLSI部品を汎用品として使用することができ基板検査治具のコストを低減できる効果がある。   Further, the selection circuit 9 in FIG. 4 is preferably a semiconductor electronic circuit, and is particularly preferably an LSI component in order to realize space saving. In that case, if the number of stages of the counter circuit in the LSI component is arbitrarily set and the required number of stages is used, the LSI component can be used as a general-purpose product, and the cost of the substrate inspection jig can be reduced.

本発明は、被検査基板1などに形成された配線パターン2の導通を電気的に検査する基板検査治具に利用可能である。   The present invention can be used for a substrate inspection jig for electrically inspecting conduction of a wiring pattern 2 formed on a substrate 1 to be inspected.

1・・・被検査基板
2・・・配線パターン
3・・・支持体
4・・・支持板
5・・・コネクタ
6・・・スキャナ
7・・・直流電流源
8・・・電圧計
9・・・選択回路
10・・・D−FF回路
11・・・AND回路
12、14・・・インバータ回路
13・・・トランスファーゲート
101〜106・・・(上側)検査点
201〜204・・・(下側)検査点
301〜306・・・(上側治具)プローブピン
401〜404・・・(下側治具)プローブピン
501〜510・・・プローブピン
F506、F507、F508、F509、F510・・・プローブピン506から510に接続する選択回路の入力端子
Q1、Q2、Q3、Q4、Q5・・・カウンタ回路の出力信号
T500・・・選択回路9の出力端子
S506〜S510・・・506から510の信号をT500へ導通させるタイミング
DESCRIPTION OF SYMBOLS 1 ... Board | substrate 2 ... Wiring pattern 3 ... Support body 4 ... Support plate 5 ... Connector 6 ... Scanner 7 ... DC current source 8 ... Voltmeter 9 ··· Selection circuit 10 ··· D-FF circuit 11 ··· AND circuit 12 and 14 · · · Inverter circuit 13 · · · Transfer gates 101 to 106 (upper side) inspection points 201 to 204 ( (Lower side) Inspection points 301 to 306 (Upper jig) Probe pins 401 to 404 (Lower jig) Probe pins 501 to 510 ... Probe pins F506, F507, F508, F509, F510 ..Input terminals Q1, Q2, Q3, Q4, Q5 of the selection circuit connected to the probe pins 506 to 510 .... Output signal T500 of the counter circuit .... Output terminals S506 to S510 of the selection circuit 9. The timing for conducting the signal et 510 to T500

Claims (3)

基板電気検査装置で検査する被検査基板の配線パターンの検査点に接触させるプローブピンと前記プローブピンに電気接続する端子を有するコネクタとから構成される基板検査治具であって、複数の前記プローブピンのうちの一つを順番に選択して前記コネクタの1つの端子に電気接続させる選択回路を有することを特徴とする基板検査治具。   A substrate inspection jig comprising a probe pin brought into contact with an inspection point of a wiring pattern of a substrate to be inspected by a substrate electrical inspection apparatus, and a connector having a terminal electrically connected to the probe pin, wherein the plurality of probe pins A board inspection jig comprising a selection circuit that sequentially selects one of the terminals and electrically connects to one terminal of the connector. 請求項1に記載の基板検査治具であって、前記選択回路が半導体集積回路から成ることを特徴とする基板検査治具   2. The substrate inspection jig according to claim 1, wherein the selection circuit is formed of a semiconductor integrated circuit. 請求項1に記載の基板検査治具であって、前記選択回路に接続するプローブピンは、複数の検査点を有するネットの1つの検査点に接触させるように配置し、前記選択回路を介さずに前記コネクタの端子に接続するプローブピンの少なくとも1つを前記ネットの他の検査点に接触させるように配置したことを特徴とする基板検査治具。   The board inspection jig according to claim 1, wherein the probe pin connected to the selection circuit is disposed so as to contact one inspection point of a net having a plurality of inspection points, and does not pass through the selection circuit. The board inspection jig is characterized in that at least one of the probe pins connected to the terminal of the connector is placed in contact with another inspection point of the net.
JP2009040485A 2009-02-24 2009-02-24 Board inspecting jig Pending JP2010197134A (en)

Priority Applications (1)

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JP2009040485A JP2010197134A (en) 2009-02-24 2009-02-24 Board inspecting jig

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Application Number Priority Date Filing Date Title
JP2009040485A JP2010197134A (en) 2009-02-24 2009-02-24 Board inspecting jig

Publications (1)

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JP2010197134A true JP2010197134A (en) 2010-09-09

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Family Applications (1)

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Country Link
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