JP2010191107A - Liquid crystal display device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a liquid crystal display device, the method completely repairing a display defect without lowering an aperture ratio. <P>SOLUTION: The liquid crystal display device includes a main TFT (thin film transistor) and a redundant TFT having a source region and a drain region of an amorphous oxide containing In, Ga and Zn made to have high electric conductivity by the application of ultraviolet rays. A transparent drain region of the redundant TFT is formed extending to a repair region provided at a signal line so as to overlap with a pixel electrode. The repair region and the end of the drain region of the redundant TFT are insulated by an insulating layer. The main TFT is separated from the pixel electrode with respect to a pixel part in which a display defect has occurred, and the end of the drain region of the redundant TFT and the signal line are welded in the repair region. The redundant TFT thereby functions as a switching element to completely repair the display defect. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a liquid crystal display device and a manufacturing method thereof, and more particularly, to a liquid crystal display device using a metal oxide amorphous semiconductor thin film and a repair technique for a pixel portion in the manufacturing method thereof.

  In recent years, semiconductor elements using metal oxide semiconductor thin films have attracted attention. This thin film can be formed at a low temperature and has a feature that a film transparent to visible light can be formed. It is flexible and transparent on a transparent substrate such as a plastic substrate or a film. A thin film transistor (hereinafter referred to as a “TFT”) can be formed (Patent Document 1).

A semi-insulating transparent amorphous thin film made of an oxide containing In, Ga and Zn is known as an oxide semiconductor film used for an active layer of a TFT. A structure of a top gate type TFT using an Au film laminated on a layer of InGaZnO ₃ (ZnO) _{4 having} a high conductivity as a source electrode and a drain electrode is disclosed. Further, an amorphous InGaZnO ₄ TFT is an amorphous silicon TFT. It has been disclosed that it has a significantly higher mobility than that of Japanese Patent Application Laid-Open No. 2003-259542 (Patent Document 2).

  A TFT having an oxide containing In, Ga and Zn having such excellent characteristics as a semiconductor layer is used for a display device such as a television receiver, a monitor for a personal computer, a portable terminal, particularly an active matrix type. Active research and development continues to be used as a switching element in liquid crystal display devices.

  On the other hand, in order to improve the manufacturing yield of liquid crystal display devices and reduce costs, the occurrence of display defects such as pixel point defects (dark spot defects, bright spot defects, etc.) and line defects is reduced in the liquid crystal display panel manufacturing process. In addition to the manufacturing technology, the technology for repairing these defects has become increasingly important (Patent Document 3).

JP 2000-150900 A JP 2006-165529 A JP-A-9-127549

  Hereinafter, for convenience, in this specification, among the source and drain of a TFT, the side to which a load (liquid crystal) is connected is referred to as a source, and the other is referred to as a drain. Even if the drain is called the source, the operation and effect are the same.

  In an active matrix liquid crystal display device, switching elements are arranged in a matrix in the vicinity of the intersections of a plurality of scanning lines and a plurality of signal lines, and pixel electrodes are connected to the respective switching elements. In the liquid crystal display device having such a configuration, particularly in the case of a large-screen liquid crystal display device, in the manufacturing process, display defects such as point defects and line defects such as bright spot defects or dark spot defects of pixels. Can occur.

  For example, a defect in which a source region or a source electrode is short-circuited with a gate electrode or a scanning line due to a defective formation of a TFT used as a switching element, and the potential of the pixel electrode is always the same as the scanning line potential A pixel having such a defect becomes a pixel having a so-called dark spot defect or a so-called bright spot defect that becomes a dark display when displayed as a display device. In the case of a dark spot defect, such a defect is likely to be visually recognized when the surrounding pixels are brightly displayed, and in the case of a bright spot defect, such a defect is easily visible when the surrounding pixels are darkly displayed. Further, even when the leak does not occur until such a short circuit occurs, a normal image signal is not supplied to the pixel electrode, and the display gradation of the pixel becomes abnormal regardless of the image signal. Whether it becomes a bright spot defect or a dark spot defect depends on the defect mode, the setting of the transmission axis of the polarizing plate, and the like.

  Various repair methods have been proposed to deal with point defects such as bright spot defects and dark spot defects. For example, there is a method in which a pad extending from a pixel electrode is provided in advance so as to overlap with a signal line, and the signal line and the pixel electrode are welded by irradiating the pad with laser (patent) Reference 3). However, this repair method makes the defect inconspicuous by performing a pseudo display so that the image signal from the signal line is always supplied to the pixel electrode regardless of the selection period or the non-selection period. Only. Therefore, a display device in which point defects are completely repaired cannot be realized, and there is a problem in display quality.

  In order to completely repair point defects, in addition to TFTs originally provided as switching elements (referred to as “main TFTs”), redundant TFTs (referred to as “redundant TFTs”) are formed in the pixel portion in advance. There is also a repair method in which when a point defect occurs due to a defective formation of the main TFT, the main TFT is separated from the pixel electrode, and a redundant TFT is connected to the pixel electrode instead of the main TFT to function as a switching element. It has been. According to this method, since the redundant TFT operates normally according to the selection period or the non-selection period, the pseudo display is not performed as described above, and the display quality is improved. However, in this method, when a redundant TFT is formed by a conventionally used amorphous silicon TFT or polysilicon TFT, a connection pattern made of a light-shielding metal or the like is previously provided between the redundant TFT and the signal line. Such a light-shielding connection pattern often overlaps the pixel electrode in plan view, and as a result, the aperture ratio of the pixel portion is lowered, which is not preferable.

  In order to avoid such a decrease in the aperture ratio, it is conceivable to connect the redundant TFT and the signal line with a connection pattern made of ITO (Indium Tin Oxide), which is a transparent conductor. However, in this method, if such a connection pattern is formed in the same layer as the layer on which the pixel electrode is formed, the area of the pixel electrode is reduced and the aperture ratio is reduced. Further, if it is formed in a layer different from the layer on which the pixel electrode is formed, a film forming and patterning process different from the pixel electrode forming process is required, so that PEP (Photo Engraving Process) increases and productivity decreases. There is.

  As another method for avoiding a decrease in the aperture ratio, the connection pattern between the signal line and the redundant TFT is extended in a branch shape from the signal line to the redundant TFT, and the tip of the extended connection pattern is connected to the redundant TFT, In order to avoid a decrease in the aperture ratio, there is a method in which such a connection pattern is disposed above the scanning line via an insulating layer so as to overlap the scanning line in plan view. In this method, the connection pattern can be formed of the same light-shielding material as the material of the signal line, and the aperture ratio does not decrease. The parasitic capacitance generated increases, the time constant of the waveform of the scanning signal supplied by the scanning line also increases, and this causes deterioration in display quality in image display, which is not preferable.

  The present invention has been made in view of the above points, and the present invention provides a liquid crystal display device capable of repairing display defects such as point defects generated in a pixel portion by using redundant TFTs, and a method for manufacturing the same. The purpose is to do. Another object of the present invention is to provide a liquid crystal display device that can be repaired without decreasing the aperture ratio and a method for manufacturing the same. It is another object of the present invention to provide a repairable liquid crystal display device having a high display quality without adding an extra PEP and a method for manufacturing the same.

  In the method for manufacturing a liquid crystal display device of the present invention, a liquid crystal is sandwiched between opposing substrates, and a plurality of signal lines and a plurality of scanning lines intersecting each other on one of the substrates, and pixels corresponding to the intersections. A method of manufacturing a liquid crystal display device including an electrode, wherein the first semiconductor layer of the first thin film transistor including the first source region and the first drain region overlaps the second source region and the pixel electrode in plan view. A second semiconductor layer of a second thin film transistor including a second drain region formed so that an end thereof extends to the repair region and the repair region and the insulating layer are sandwiched to overlap each other in plan view, and includes In, Ga, and Zn Irradiating the first semiconductor layer and the second semiconductor layer with ultraviolet rays from a first step of forming from an amorphous oxide containing oxygen and a light-shielding gate electrode connected to the scanning line A second step of increasing the conductivity of the first semiconductor layer and the second semiconductor layer as compared with before irradiation, and a third step of forming the insulating layer on the first semiconductor layer and the second semiconductor layer. A signal line including the repair region connected to the second drain region by being short-circuited to the second drain region and connected to the first drain region on the insulating layer; A fourth step of forming, a fifth step of forming the pixel electrode and connecting the pixel electrode to the first source region and the second source region, separating the first thin film transistor from the pixel electrode, And a sixth step of repairing the display defect by short-circuiting the second drain region and the signal line in the repair region.

  By adopting such a configuration, the present invention connects the first thin film transistor, which is a main thin film transistor, the second thin film transistor, which is a redundant thin film transistor, and both of these thin film transistors, for each pixel portion partitioned by a scanning line and a signal line. Formed pixel electrodes are formed. Each of the first thin film transistor and the second thin film transistor uses a transparent amorphous oxide containing In, Ga, and Zn as a semiconductor layer. By irradiating this with ultraviolet light, the conductivity of the semiconductor layer is increased. The conductivity can be increased to a level close to that of a conductive material. Then, by selectively irradiating a part of the semiconductor layer with such ultraviolet rays, the conductivity can be increased only in the irradiated region. Therefore, by selectively irradiating the regions to be the source region and the drain region among the semiconductor layers of the first thin film transistor and the second thin film transistor, the semiconductor device has high conductivity enough to be used as a transparent electrode or a conductor. A source region and a drain region can be formed. On the other hand, the conductivity of the region of the semiconductor layer that has not been irradiated with ultraviolet rays is maintained as it was before the irradiation, and therefore should be the channel region of the first thin film transistor and the channel region of the second thin film transistor. By preventing the region from being irradiated with ultraviolet rays using a light-shielding gate electrode as a shadow mask, the region can be a region having conductivity that can be used as a channel of a thin film transistor.

  The signal line is provided with a repair region, and the second drain region of the second thin film transistor extends from the junction with the channel region of the second thin film transistor so as to overlap with the pixel electrode in plan view. Since the end of the second drain region is formed to overlap the repair region and the insulating layer in plan view, the transparent second drain region is formed of the transparent pixel electrode. The lower portion extends to reach the lower portion of the repair area. The repair region is provided in the signal line and is a part of the signal line, and the second drain region is a part of the second semiconductor layer, and the signal line and the second semiconductor layer are insulated from each other. Since the layer is formed, the second drain region is insulated from the repair region, that is, the signal line, before repair.

  Then, after forming the pixel electrode connected to both the source region of the first thin film transistor and the source region of the second thin film transistor, the dark spot generated by the scanning line being short-circuited with the pixel electrode through the first thin film transistor in the inspection process. When a display defect such as a defect is found, the pixel electrode is separated from the first thin film transistor, and repair is performed to short-circuit the second drain region and the repair region insulated by the insulating layer with a laser beam or the like. Thus, the second drain region of the second thin film transistor can be connected to the signal line. As a result, a liquid crystal display device in which the second thin film transistor functions as a switching element instead of the first thin film transistor and a display defect such as a dark spot defect is repaired and a normal display can be produced can be manufactured.

  As described above, the manufacturing method of the liquid crystal display device according to the present invention is such that the pixel electrode is connected to the signal line through the second thin film transistor, and the pixel electrode and the signal line are directly connected by welding or the like. Since this is different from the conventional example in which the defect is not noticeable by performing a typical display, the display defect of the pixel is completely repaired and the display quality is improved.

  Further, as the semiconductor layer of the second drain region up to the repair region, an oxide containing In, Ga, and Zn, which is made highly transparent by ultraviolet irradiation and is transparent, is used as in the conventional example. Since silicon or polysilicon is not used, it is not necessary to previously wire a connection pattern made of a light-shielding metal or the like between the second thin film transistor and the signal line. Therefore, even if the second drain region is formed so as to overlap with the pixel electrode in plan view, the aperture ratio of the pixel portion does not decrease.

  Furthermore, since the second drain region is formed in a layer different from the pixel electrode, it is not necessary to reduce the area of the pixel electrode as in the conventional example, and the aperture ratio does not decrease. Further, there is no need to add PEP in order to form a connection pattern made of a transparent conductive layer such as ITO in a layer different from the pixel electrode, and productivity does not decrease.

  In addition, since it is necessary to increase the conductivity of the drain region or the like by the above-described ultraviolet irradiation, the present invention does not form the second drain region so as to overlap the light-shielding scanning line. The two drain regions are formed so as to overlap the pixel electrode in plan view. Therefore, there is no increase in parasitic capacitance with the scanning line, the time constant of the waveform of the scanning signal is increased, and there is no inconvenience that the display quality is deteriorated.

  Thus, according to the method for manufacturing a liquid crystal display device according to the present invention, display defects such as point defects generated in the pixel portion can be repaired by using the second thin film transistor, and the aperture ratio is reduced. There is nothing. In addition, a liquid crystal display device with high display quality can be manufactured without adding extra PEP.

  Note that the second step in the present invention is to irradiate ultraviolet rays from the gate electrode side toward the semiconductor layer using a light-shielding gate electrode as a shadow mask, so that both top-gate and bottom-gate thin film transistors are applied. Can be applied. That is, by performing the gate electrode forming step and the gate insulating film forming step before the first step, the manufacturing method of the liquid crystal display device according to the present invention can be applied to a liquid crystal display device using a bottom gate thin film transistor. it can. Similarly, by performing the gate insulating film formation step and the gate electrode formation step after the first step and before the second step, the present invention can be applied to a liquid crystal display device using a top-gate thin film transistor.

  In the method of manufacturing a liquid crystal display device according to the present invention, the sixth step includes a step of repairing the first thin film transistor by separating it from the signal line. With this configuration, not only the scanning line and the pixel electrode are short-circuited via the first thin film transistor, but also the scanning line is further short-circuited to the signal line via the channel region of the first thin film transistor. In this case, the first thin film transistor can be separated from the signal line. Thereby, in addition to the above operations and effects, it is possible to repair a line defect caused by such a short circuit between the scanning line and the signal line.

  In the method for manufacturing a liquid crystal display device according to the present invention, the repair in the sixth step is performed by laser light irradiation. By adopting such a configuration, it is possible to repair both welding and cutting not only at the stage where the pixel electrode is formed but also after the counter substrate is bonded and the liquid crystal is sealed.

  In the method for manufacturing a liquid crystal display device according to the present invention, the resistances of the first drain region and the second drain region after irradiation with the ultraviolet light are lower than the on-resistances of the first thin film transistor and the second thin film transistor, respectively. It is characterized by. By adopting such a configuration, it is possible to reduce a decrease in signal level such as an image signal due to the resistance of the entire drain region.

  In the method of manufacturing a liquid crystal display device according to the present invention, the impurity concentration of the channel region of the first thin film transistor and the second thin film transistor is set such that the first source region, the first drain region, the second source region, and the second drain. The impurity concentration of the region is the same. By adopting such a configuration, it is not necessary to perform treatment such as ion doping when forming a source region or a drain region having higher conductivity than the channel region as in the conventional case, which contributes to rationalization of manufacturing equipment. In addition, since damage due to ion doping can be avoided, the reliability of the thin film transistor is improved.

  In the method of manufacturing a liquid crystal display device according to the present invention, the light source for irradiating the ultraviolet rays is a surface light source. Since this invention takes such a structure, it can irradiate an ultraviolet-ray uniformly at once to the wide irradiation area which covers the whole board | substrate. Further, since a surface light source is used, it is not necessary to scan the substrate as in the case of a laser light source with a narrow beam spot, and double irradiation of the semiconductor layer by scanning does not occur. Therefore, it is possible to irradiate ultraviolet rays with uniform irradiation energy, and as a result, in the case of forming a large number of thin film transistors over the entire display screen of a large area, not only simplification of the process and improvement of mass productivity but also the thin film transistor A variation in characteristics can be suppressed and uniform, and a display device with high display quality can be obtained without luminance variation and luminance unevenness.

  In the method for manufacturing a liquid crystal display device of the present invention, the light source for irradiating the ultraviolet rays is a mercury lamp. Since the present invention adopts such a configuration, a lamp that irradiates ultraviolet rays having a specific range of wavelengths can be used instead of a laser light source. Therefore, it is possible to avoid problems due to heat generation of the substrate by the laser light, and it is possible to use a plastic film substrate. Further, an ultraviolet irradiation device that is less expensive than a laser beam irradiation device can be used.

In the method for manufacturing a liquid crystal display device according to the present invention, the wavelength of the ultraviolet ray ranges from 270 nm to 450 nm. By irradiating ultraviolet rays in such a wavelength range, the conductivity of the source region and drain region irradiated with the ultraviolet rays can be improved to an appropriate level. In the method of manufacturing a liquid crystal display device of the present invention, the cumulative irradiation energy density of ultraviolet rays in the second step is (309 · n) when the conductivity is increased to 10 ⁿ times (where 0 <n ≦ 6). Or (392 · n) J / cm ² . Since the present invention has such a configuration, if the target conductivity is set, the cumulative irradiation energy density of ultraviolet rays, the irradiation time, and the like can be calculated in advance.

The method for producing a liquid crystal display device of the present invention is characterized in that an integrated irradiation energy density of ultraviolet rays in the second step is 1620 J / cm ² or more. The present invention is, to take such a configuration, it is possible to increase to a sufficient conductivity to function the conductivity of the source region and the drain region as electrodes or conductors (about 10 -1 ^{S / m} or higher).

The method for producing a liquid crystal display device of the present invention is characterized in that the irradiation energy density of ultraviolet rays in the second step is 100 mJ / sec · cm ² . Since the present invention adopts such a configuration, the irradiation energy density can be used for irradiation using a general ultraviolet irradiation device used for other applications, and thus the manufacturing equipment can be rationalized. Can be achieved.

  In the method for manufacturing a liquid crystal display device of the present invention, the first semiconductor layer and the second semiconductor layer are further irradiated with ultraviolet rays between the first step and the second step, and before the irradiation with the ultraviolet rays. Includes a pre-ultraviolet irradiation step for forming the amorphous first semiconductor layer and the second semiconductor layer having high conductivity. By adding this step, even if the conductivity of the channel region of the thin film transistor is not preferable as it is because the conductivity after the formation of the semiconductor layer is low, the conductivity is improved by such a pre-ultraviolet irradiation step. As a channel region, the conductivity can be improved to an appropriate level, and the yield can be improved.

The method for producing a liquid crystal display device of the present invention is characterized in that an integrated irradiation energy density of ultraviolet rays in the pre-ultraviolet irradiation step is 148 to 1012 J / cm ² . By selecting such integrated irradiation energy density, the conductivity of the channel region can be made appropriate (about 10 ⁻⁴ to 10 ⁻³ S / m).

  In the liquid crystal display device of the present invention, a liquid crystal is sandwiched between opposing substrates, and a plurality of signal lines intersecting each other, a plurality of scanning lines, and a pixel electrode corresponding to each intersection are disposed on one of the substrates. A first gate electrode connected to the scanning line, a first drain region having a higher conductivity than before irradiation by ultraviolet irradiation, and a first source connected to the pixel electrode. A first thin film transistor including a first semiconductor layer including an amorphous oxide including In, Ga, and Zn, a second gate electrode connected to the scanning line, and before irradiation by the ultraviolet irradiation. A second drain region having a higher conductivity and extending to reach the repair region in a plan view so as to overlap with the pixel electrode so that the end portion overlaps the repair region and the insulating layer in a plan view A second semiconductor layer made of an amorphous oxide containing In, Ga, and Zn, including a second source region connected to the pixel electrode and having a higher conductivity than that before irradiation by the ultraviolet irradiation. Two thin film transistors and the signal line including the repair region connected to the second drain region by being connected to the first drain region and being short-circuited to the second drain region. It is characterized by providing. The liquid crystal display device according to the present invention is characterized in that the signal line is connected to the second drain region by the repair, and the first thin film transistor and the pixel electrode are separated from each other. To do.

  With such a configuration, the present invention can provide a liquid crystal display device capable of repairing display defects such as point defects generated in the pixel portion by using redundant TFTs, and a manufacturing method thereof. Further, the present invention can provide a liquid crystal display device that can be repaired without reducing the aperture ratio and a method for manufacturing the same. Furthermore, the present invention can provide a repairable liquid crystal display device having a high display quality without adding an extra PEP and a method for manufacturing the same.

1 is a schematic configuration diagram of a liquid crystal display device according to an embodiment of the present invention. 1 is a schematic plan view of a pixel unit that is an embodiment of the present invention. It is explanatory drawing of the manufacturing process of the pixel part containing the top gate type main TFT which is one Embodiment of this invention. It is explanatory drawing of the manufacturing process of the pixel part containing the top gate type redundant TFT which is one Embodiment of this invention. It is a graph which shows the relationship between the electrical conductivity of the amorphous oxide semiconductor layer containing In, Ga, and Zn of this invention, and ultraviolet irradiation time. It is explanatory drawing of the manufacturing process of the pixel part containing the bottom gate type main TFT which is one Embodiment of this invention. It is explanatory drawing of the manufacturing process of the pixel part containing the bottom gate type redundant TFT which is one Embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that in this specification, an oxide containing In, Ga, and Zn is referred to as “IGZO”.

[overall structure]
The liquid crystal display device according to the present embodiment includes a liquid crystal panel in which liquid crystal is sandwiched between a cell array substrate and a counter substrate. FIG. 1 is a schematic schematic configuration diagram of a liquid crystal panel portion of an active matrix type liquid crystal display device according to the present embodiment. FIG. 1A is a schematic plan view of the cell array substrate 101, and FIG. 1B is an equivalent circuit diagram for explaining the functions of the pixel unit 10 and its peripheral members, which will be described later. It is a figure before repairing. Note that in each drawing used for description in this specification, the scale or aspect ratio is appropriately changed for convenience.

  The cell array substrate 101 is formed with a plurality of scanning lines 72 extending in the X (row) direction and connected to the scanning line external terminals 74 and gate electrodes of a plurality of TFTs as switching elements in the pixel unit 10. ing. A scanning signal that is a signal for selectively switching the TFTs in units of rows is supplied to the TFTs via the scanning lines 72. A plurality of scanning line external terminals 74 corresponding to the plurality of scanning lines 72 are provided in the Y direction near the end of the cell array substrate 101. The scanning line external terminal 74 is connected to a predetermined terminal (not shown) of the scanning line driving device 70 such as a scanning line driver IC via an ACF (anisotropic conductor) (not shown).

  In addition, a plurality of signal lines 82 extending in the Y (column) direction and connected to the signal line external terminals 84 and the drain electrodes of the plurality of TFTs in the pixel unit 10 are formed on the cell array substrate 101. . An image signal is supplied to the TFT selected by the scanning signal via the signal line 82. A plurality of signal line external terminals 84 corresponding to the plurality of signal lines 82 are provided along the X direction near the end of the cell array substrate 101. The signal line external terminal 84 is connected to a predetermined terminal (not shown) of the signal line driver 80 such as a signal line driver IC via an ACF (not shown). The scanning line driving device 70 and the signal line driving device 80 may be disposed on the cell array substrate 101.

  The pixel units 10 are arranged in a matrix in a region defined by the scanning lines 72 and the signal lines 82 corresponding to the intersections of the scanning lines 72 and the signal lines 82 on the cell array substrate. The pixel unit 10 includes a main TFT 20a, a redundant TFT 20b, and a pixel electrode 32 (see FIG. 1B). The gate electrodes 12a and 12b of the main TFT 20a and the redundant TFT 20b are both connected to the same scanning line 72 and are conductive. The drain region 16a of the main TFT 20a is electrically connected to the signal line 82 through the drain electrode 26a and is conductive. The source region 15a of the main TFT 20a is electrically connected to the pixel electrode 32 and is conductive.

  The drain region 16b of the redundant TFT 20b is formed so that the end portion 16be extends to the repair region 24. Before the repair, the end portion 16be is insulated from the signal line 82 and the drain electrode 26b. The drain electrode 26 b is a part of the signal line 82 and includes the repair region 24. Therefore, the repair area 24 is a part of the signal line. The drain electrode 26b is connected to the drain region 16b of the redundant TFT 20b by repair, and thereby functions as the drain electrode of the redundant TFT 20b. The source region 15b of the redundant TFT 20b is electrically connected to the pixel electrode 32 and is conductive. As described above, the drain electrodes 26a and 26b of the main TFT 20a and the redundant TFT 20b are both connected to the same signal line 82 and are conductive. The source regions 15a and 15b of the main TFT 20a and the redundant TFT 20b are both connected to the same pixel electrode 32 and are conductive. Details of the main TFT 20a and redundant TFT 20b and details of repair will be described later.

  The common electrode (counter electrode) 34 is formed so as to face the pixel electrode 32 and is a transparent electrode common to each pixel. The common electrode 34 is generally formed on a counter substrate (not shown) in a TN (Twisted Nematic) type or VA (Vertical Alignment) type liquid crystal display device. A common signal having a predetermined voltage is applied to the common electrode 34 via a common electrode line (common electrode line) 35. A liquid crystal 99, which is an electro-optic member, is disposed between the pixel electrode 32 and the counter electrode 34, and the cell array substrate 101 and a counter substrate (not shown) sandwich the liquid crystal 99.

  The operation of the liquid crystal display device 100 including such a pixel unit 10 is, for example, as follows. The scanning line driving device 70 selects a pixel unit 10 to which the image signal from the signal line 82 should be written in units of rows based on a synchronization signal and other information of an image signal (not shown) input to the liquid crystal display device 100. Is output. Similarly, the signal line driving device 80 operates in synchronization with the scanning signal based on the luminance information of the image signal and supplies the image signal to the pixel unit 10 selected in the scanning period. Then, a voltage corresponding to the image signal from the signal line driving device 80 is applied to the pixel electrode 32 through the main TFT 20a in the selected pixel unit 10. That is, an image signal that is a signal for controlling light modulation of the liquid crystal is supplied to the pixel electrode 32 from the source region 15a of the main TFT 20a. As a result, an electric field is generated between a pair of electrodes including the pixel electrode 32 and the common electrode 34, and the orientation of the molecules of the liquid crystal 99 (the orientation of the liquid crystal molecules) is controlled by this electric field. Then, the display action of an image or the like is performed by modulating the light transmitted through the liquid crystal using this change in orientation. Although the liquid crystal display device is configured in this way, in the pixel portion without point defects, the main TFT 20a functions as a switching element of the pixel portion 10 as described above, and the redundant TFT 20b has no influence on the liquid crystal display device. Absent. In the pixel portion where the point defect occurs, the redundant TFT 20b functions as a switching element instead of the main TFT 20a by repair as will be described later.

[Pixel area and surrounding area]
Next, with reference to FIG. 2, FIG. 3C, and FIG. 4C, a configuration of a pixel portion using a top gate TFT as a switching element and its surroundings will be described. FIG. 2 is a schematic plan view including the pixel portion 10 and its periphery according to the present embodiment in a stage before the repair after the formation of the pixel electrode 32 is finished, except for the cut portions 97 and 98 described later. FIG. 3C is a schematic cross-sectional configuration diagram of the main TFT 20a in the arrow direction along the line AA ′ in FIG. FIG. 4C is a schematic cross-sectional configuration diagram of the redundant TFT 20b taken along the line BB ′ in FIG. In FIG. 2, the gate insulating film 13, the interlayer insulating film 18, and the passivation layer 19 are removed for easy understanding, and the viewing layer is appropriately changed.

  The main TFT 20 a in the pixel portion 10 is provided in the vicinity of the intersection between the scanning line 72 and the signal line 82. As shown in FIG. 3C, the main TFT 20a includes a semiconductor layer 14a formed on the substrate 11, a gate insulating film 13 that is a first insulating layer formed on the semiconductor layer 14a, and a semiconductor layer 14a. A gate electrode 12a formed on the channel region 17a which is a part of the semiconductor layer 14a via the gate insulating film 13, and a source region 15a and a drain region which are part of the semiconductor layer 14a and which are formed with the channel region 17a interposed therebetween. 16a is comprised. An interlayer insulating film 18 as a second insulating layer is formed on the gate electrode 12a. Further, a signal line 82 and a drain electrode 26a made of a second metal layer are formed on the interlayer insulating film 18, and a contact hole that reaches the drain region 16a through the interlayer insulating film 18 and the gate insulating film 13 is formed. The drain electrode 26a and the drain region 16a are connected through 23ad and are conductive. Further, a passivation layer 19 that is a third insulating layer is formed on the second metal layer, and the passivation layer 19, the interlayer insulating film 18, and the gate insulating film 13 are penetrated on the passivation layer 19 to form the source region 15 a. A pixel electrode 32 is formed which is electrically connected to the source region 15a through a contact hole 23as that reaches.

  As shown in FIG. 2, the redundant TFT 20 b is provided near the main TFT 20 a, for example, at a location along the scanning line 72. As shown in FIG. 4C, the redundant TFT 20b has a structure similar to that of the main TFT 20a, and a semiconductor layer 14b formed on the substrate 11 and a first insulating layer formed on the semiconductor layer 14b. And the gate electrode 12b formed on the channel region 17b which is a part of the semiconductor layer 14b via the gate insulating film 13 and the part of the semiconductor layer 14b which sandwiches the channel region 17b. The source region 15b and the drain region 16b are formed. An interlayer insulating film 18 as a second insulating layer is formed on the gate electrode 12b. A signal line 82 and a drain electrode 26b made of a second metal layer are formed on the interlayer insulating film 18. Unlike the main TFT 20a, the drain extends through the interlayer insulating film 18 and the gate insulating film 13. A contact hole reaching the region is not formed, and an insulating layer, that is, an interlayer insulating film 18 and a gate insulating film 13 are insulated between the drain electrode 26b formed to extend from the signal line 82 and the drain region 16b. Has been. Similar to the main TFT 20a, a passivation layer 19 as a third insulating layer is formed on the second metal layer, and a pixel electrode 32 is formed on the passivation layer 19. The pixel electrode 32 is connected to and conductive with the source region 15b through a contact hole 23bs that passes through the passivation layer 19, the interlayer insulating film 18, and the gate insulating film 13 and reaches the source region 15b.

  The semiconductor layers 14a and 14b of the main TFT 20a and the redundant TFT 20b are formed apart from each other. As for the material, it is desirable that at least the semiconductor layer 14b of the redundant TFT 20b is a transparent amorphous semiconductor made of IGZO. In the present invention, the material of the semiconductor layer 14a of the main TFT 20a is not necessarily limited to IGZO. For example, even if silicon is used for the semiconductor layer 14a, the operation and effect on the repair and the aperture ratio according to the present invention are achieved. However, it is more desirable to use IGZO for the semiconductor layer of the main TFT 20a. By using the same semiconductor material, the electrical characteristics of the main TFT 20a and the redundant TFT 20b are the same, and the manufacturing process Is also simplified.

  The semiconductor layer 14a includes three regions, ie, a source region 15a, a drain region 16a, and a channel region 17a, which are formed as a single island-shaped molded product without being separated from each other. Has been. The conductivity is the same in any of these three regions when forming the semiconductor layer 14a, but by selectively irradiating with ultraviolet rays in a predetermined step after the formation of the semiconductor layer as described later, The drain region 16a and the source region 15a are configured to have higher conductivity than the channel region 17a. The same applies to the semiconductor layer 14b. Details of the relationship between ultraviolet irradiation and conductivity will be described later.

  The gate electrode 12a of the main TFT 20a is made of a light-shielding metal layer and is formed on the channel region 17a in a shape that branches from the scanning line 72 toward the channel region 17a in each pixel unit 10. The scanning line 72 is electrically connected to the gate electrode 12a. The same applies to the gate electrode 12b of the redundant TFT 20b. The drain electrode 26a of the main TFT 20a is formed in a shape that branches from the signal line 82 in each pixel unit 10, and the drain region 16a is electrically connected to the drain electrode 26a, that is, the signal line 82. The drain electrode 26b to be connected to the redundant TFT 20b after repair is formed in a shape that branches from the signal line 82 in each pixel unit 10 into branches. The drain electrode 26b includes a repair region 24 in part. Therefore, the repair area 24 is also a part of the signal line 82. The repair region 24 is a region in which the drain electrode 26b, that is, the signal line 82 and the drain region 16b overlap in plan view with the insulating layer (the interlayer insulating film 18 and the gate insulating film 13) interposed therebetween. The repair region 24 is formed so as not to overlap the pixel electrode 32 in plan view.

  The drain region 16b of the redundant TFT 20b is formed into a shape extending from the junction with the channel region 17b of the redundant TFT 20b to the repair region 24 so as to overlap with the pixel electrode 32 in plan view. The end portion 16be of the region 16b is formed to overlap the repair region 24 and the insulating layer (interlayer insulating film 18 and gate insulating film 13) in plan view. Accordingly, the transparent drain region 16b is formed so as to extend under the transparent pixel electrode 32 until it reaches under the repair region 24. The repair region 24 is provided in the signal line 82 and is a part of the signal line 82, and the drain region 16 b is a part of the semiconductor layer 14 b and is interposed between the signal line 82 and the semiconductor layer 14 b. Since an insulating layer (interlayer insulating film 18 and gate insulating film 13) is formed, the drain region 16b is insulated from the repair region 24, that is, the signal line 82 before repair.

  In the present embodiment, the drain electrodes 26a and 26b are formed by extending part of the side end of the signal line 82 on the pixel electrode 32 side in a branch shape to the pixel electrode 32 side by a length Ld. The drain electrodes 26a and 26b are formed so as to overlap with the drain regions 16a and 16b formed in the lower layer in plan view, respectively, but the extent of the overlap is such that the contact hole 23ad can be formed for the drain electrode 26a. In addition, the drain electrode 26b only needs to be wide enough to secure a repair region 24 that can be sufficiently repaired by laser light described later. Further, the length Ld of the branch portions of the drain electrodes 26a and 26b is not particularly limited, but may be several μm, for example, about 5 μm or less. If the length Ld of the branch portion is about this level, the branch portion is formed under a black matrix (hereinafter referred to as “BM”) (not shown), that is, inside the BM without protruding from the region overlapping with the BM. Therefore, the aperture ratio is not reduced by the branch drain electrodes 26a and 26b. Note that BM is a light shielding layer formed of metal or black resin, and is formed on the counter substrate together with a color filter, for example. The BM is formed in a lattice shape so as to cover the scanning line 72 and signal line 82 forming region, the region between them and the pixel electrode 32, and the peripheral edge of the pixel electrode 32. When the TFTs 20a and 20b are not formed on the scanning line 72, the TFTs are formed so as to cover such TFTs.

  In the present embodiment, the drain region 16b is formed to extend to the repair region 24 while bypassing the gate electrode 12b. Moreover, since the drain regions 16a and 16b are also part of the semiconductor layers 14a and 14b made of IGZO, both are transparent to visible light. Therefore, even if the drain region 16b is formed to extend under the pixel electrode 32, the aperture ratio does not decrease. Further, the drain regions 16a and 16b are formed so that the conductivity thereof becomes higher than the conductivity of the channel region 17 when irradiated with ultraviolet rays, as will be described later.

  Similarly to the drain region, the source regions 15a and 15b of the main TFT 20a and the redundant TFT 20b are also formed so that the conductivity thereof becomes higher than the conductivity of the channel region 17 by irradiation with ultraviolet rays, as will be described later. Therefore, the resistance of the source regions 15a and 15b is smaller than before the ultraviolet irradiation, and can function as an electrode. As described above, the source regions 15a and 15b having high conductivity serve as the source or source electrodes 25a and 25b as the carrier sources of the main TFT 20a and the redundant TFT 20b.

  Further, since the source regions 15a and 15b are also part of the semiconductor layers 14a and 14b made of IGZO, both are transparent to visible light. Since the pixel electrode 32 is also transparent and the source region has a high conductivity, it is necessary to form a light-shielding metal pattern for electrical connection between the source region and the pixel electrode as in the prior art. The pixel electrode 32 made of a transparent conductive layer such as ITO can be directly connected to the source regions 15a and 15b through the contact holes 23as and 23bs to be conductive. Therefore, the metal pattern does not block light around the contact hole 23as or 23ad, which contributes to the improvement of the aperture ratio.

  The channel regions 17a and 17b of the main TFT 20a and the redundant TFT 20b are formed so as to be sandwiched between the source region and the drain region in a self-aligned manner with respect to the gate electrodes 12a and 12b, as will be described later. The pixel electrode 32 has a shape and a size that do not overlap with the gate electrode, the drain electrode, the scanning line, and the signal line in plan view, and is formed in a planar shape so as to fit inside the pixel portion 10.

  Next, each member such as the main TFT 20a and the redundant TFT 20b will be described in more detail. As the substrate 11, a plastic substrate can be used in addition to a glass substrate, a quartz substrate, etc., which are substrates having insulation and transparency. In order to faithfully reproduce the display color of the display device, the substrate is more preferably transparent to visible light. The thickness of the semiconductor layers 14a and 14b is not particularly limited, but is preferably 50 nm to 150 nm, and more preferably about 100 nm.

  As the material of the gate insulating film 13 which is the first insulating layer, a silicon oxide-based or silicon nitride-based SiNx, SiOx or SiOxNy single layer film, or a laminated film in which these are combined can be used. Further, when the film thickness can be reduced, liquid silicon oxide can be used. Thereby, an insulating and transparent layer can be formed. The gate insulating film 13 is generally formed so as to cover the entire substrate 11. As a result, the semiconductor layers 14 a and 14 b are covered with the gate insulating film 13. The thickness of the gate insulating film 13 is desirably 100 nm to 500 nm, and more desirably 250 nm to 300 nm.

  The gate electrodes 12a and 12b and the scanning line 72 are formed by patterning the first metal layer. The first metal layer may be, for example, a single layer film of AlNd, Al, or Mo, or a laminated film formed by combining arbitrary elements selected from AlNd, Al, Mo, and Cu. For example, when such a wiring to be formed contains Al and may be connected to a transparent conductive layer such as an oxide semiconductor or ITO, the first metal layer should be a laminated structure. Is desirable. For example, an upper layer that may be connected to ITO or the like in a later process is preferably a metal containing Mo, and a lower layer is a metal layer containing Al, such as AlNd. By adopting such a material and structure, it is possible to avoid electrical corrosion at the interface between ITO and Al and to achieve good electrical connection. The thickness of the first metal layer is desirably 200 nm to 400 nm, and more desirably 300 nm. Note that in the case where it is necessary to prevent the TFT characteristics from being affected by external light, it is desirable to use a material having a high light blocking property at least for the gate electrode.

  The material of the interlayer insulating film 18 that is the second insulating layer is not particularly limited, but a silicon oxide system or a silicon nitride system having insulation and transparency can be used. The interlayer insulating film 18 is formed so as to cover the entire surface of the substrate. As a result, the semiconductor layers 14 a and 14 b are covered with the interlayer insulating film 18. The film thickness is desirably 300 nm to 400 nm.

  The drain electrodes 26a and 26b and the signal line 82 are formed by patterning the second metal layer. The material or structure of the second metal layer is not particularly limited, and may be a single layer film of Al or Mo, but when a transparent conductive layer such as ITO may be formed on the upper layer, the ITO or the like and Al In order to avoid electric corrosion between them, it is desirable to have a laminated structure. For example, it is desirable to use a laminated film (laminated wiring) formed by combining Al and Mo, such that the upper layer in contact with ITO is Mo and the lower layer is Al. In addition, when an oxide semiconductor is used as the material of the semiconductor layer, particularly when IGZO is used as the semiconductor layer, IGZO has similar chemical characteristics to ITO, so that the same is true at the interface between IGZO and Al. In order to avoid the problem of electric corrosion, when connecting Al and ITO or IGZO, a metal layer having a three-layer structure such as Mo-Al-Mo is used, and ITO or IGZO is connected to Al via Mo. Such a structure is desirable. As described above, by using the second metal layer in which the uppermost layer and the lowermost layer are made of a metal containing Mo, Mo functions as a so-called cover metal to prevent the electrolytic corrosion reaction, and the lower layer of the second metal layer is oxidized. Prevents galvanic corrosion between Al and oxide semiconductor layers and between Al and ITO and other transparent conductive layers even when connected to a physical semiconductor and the upper layer is connected to a transparent conductive layer such as ITO. In addition, a good ohmic contact can be obtained with a low resistance, and a highly reliable electrical connection can be achieved. The thickness of the second metal layer is 200 nm to 400 nm, more preferably 300 nm.

  The material of the passivation layer 19 that is the third insulating layer is not particularly limited, and silicon nitride or the like having insulation and transparency can be used. The thickness of the passivation layer 19 is 200 nm to 500 nm. The passivation layer 19 is formed so as to cover the entire surface of the substrate. As a result, the drain electrodes 26 a and 26 b and the signal line 82 formed from the second metal layer are covered with the passivation layer 19. The material of the pixel electrode 32 is not particularly limited. For example, a transparent conductive material such as ITO is used.

[repair]
Display defect repair will be described with reference to FIGS. 3C and 3D and FIGS. 4C and 4D, taking the top-gate TFT according to this embodiment as an example. FIGS. 3C and 3D are schematic cross-sectional configuration diagrams in the direction of the arrows in the line AA ′ in FIG. 2 before and after the repair of the main TFT 20a, respectively. Similarly, FIGS. 4C and 4D are schematic cross-sectional views in the direction of the arrows in the line BB ′ of FIG. 2 before and after repair of the redundant TFT 20b, respectively.

  First, as an example of a liquid crystal display device having a display defect, a case of a TN type normal white mode liquid crystal display device having a point defect caused when the pixel electrode 32 is short-circuited with the scanning line 72 due to a manufacturing defect of the main TFT 20a will be described. In a liquid crystal display device in which two polarizing plates are arranged so that their transmission axes are orthogonal to each other, and a TN liquid crystal having a twist angle of 90 degrees is sandwiched between these two polarizing plates, no electric field is applied to the liquid crystal Is a white display (bright display) that transmits light from the backlight. When an electric field corresponding to black display is applied to the liquid crystal, the light from the backlight is absorbed to display black (dark display). Normal white mode LCD is displayed.

  In such a TN type normal white mode liquid crystal display device, when a defect such that the pixel electrode 32 is short-circuited with the scanning line 72 due to a manufacturing defect of the main TFT 20a occurs, an image signal is displayed on the pixel electrode 32. The normal voltage based thereon is not supplied, and the potential of the pixel electrode 32 becomes almost the same as the potential of 72 of the scanning line. Since the voltage level of the scanning signal supplied to the scanning line 72 is generally different from the voltage level of the common signal applied to the common electrode 34 and the potential difference between the two is relatively large, the pixel portion having such a short-circuit defect. An electric field corresponding to the difference between the scanning signal potential and the common electrode potential is applied between the pixel electrode 32 and the common electrode 34. Therefore, when an image is displayed on such a liquid crystal display device, the pixel portion having such a short-circuit defect is darkly displayed, and when the peripheral pixel portion is brightly displayed, it is visually recognized as a so-called dark spot defect. The

  Next, the repair method according to the present embodiment will be described taking the dark spot defect of such a TN type normal white mode liquid crystal as an example. First, after the cell array substrate 101 is formed, information such as the presence / absence of a dark spot defect and a defect position is acquired in an inspection process. Next, when there is a dark spot defect in which the pixel electrode 32 and the scanning line 72 are short-circuited due to a manufacturing defect of the main TFT 20a, as shown in FIG. 3D, the main TFT 20a and the pixel electrode 32 are repaired. Disconnect the connection. Specifically, for example, in the case of a pattern layout as shown in FIG. 2, repair is performed such that the source region 15a is cut by irradiating a laser beam to the cut portion 97 of the source region 15a of the main TFT 20a. Thereby, the pixel electrode 32 is separated from the main TFT 20a and released from the main TFT 20a.

  Note that the cut portion 97 depends on the pattern layout of the main TFT, redundant TFT, scanning line, or pixel electrode, but does not depart from the spirit of the present invention as long as at least the pixel electrode 32 can be separated from the short-circuited portion. As long as it is not particularly limited. For example, when the scanning line 72 is short-circuited not only with the pixel electrode 32 but also with the signal line 82 via the channel region 17a of the main TFT 20a, the drain region 16a is also cut at the cutting point 98 in addition to the cutting point 97. The signal line 82 and the scanning line 72 are separated from each other. When IGZO is used as the semiconductor layer 14a of the main TFT 20a, the mobility of IGZO is large. Therefore, when the scanning line 72 and the channel region 17a are short-circuited, the channel region 17a is also formed between the signal line 82 and the scanning line 72. It is easy to be in a short circuit state. Therefore, when such a high mobility semiconductor is used as the semiconductor layer of the TFT, it is possible to cut not only the source region but also the drain region of the TFT causing the short circuit as described above. Desirably, the line defect caused by the short circuit between the scanning line and the signal line can be repaired by performing such cutting. Note that when a semiconductor such as IGZO with high mobility is used as the semiconductor layer of the TFT, the channel width W can be reduced because of the large mobility. Therefore, the source region 15a and the drain region 16a At least a portion can be patterned narrowly. Therefore, cutting with a laser beam is easy.

  Next, as shown in FIG. 4D, the repair region 24 and the drain are irradiated by irradiating the repair region 24 where the end portion 16be of the drain region 16b of the redundant TFT 20b and the drain electrode 26b overlap with each other. The insulating layer (interlayer insulating film 18 and gate insulating film 13) that insulates the region 16b is pierced, and the drain electrode 26b and the drain region 16b are welded to form a welded portion 24e. As a result, the signal line 82 and the drain region 16b are electrically connected, and the two are made conductive. As a result, the image signal supplied to the signal line 82 is supplied to the pixel electrode 32 via the redundant TFT 20b, and the redundant TFT 20b operates as a switching element instead of the main TFT 20a to drive the pixel electrode 32. Can do. The potential of the pixel electrode 32 becomes a normal potential corresponding to the switching operation of the redundant TFT 20b. Therefore, when an image is displayed on such a liquid crystal display device, the dark spot defect is repaired and normal display without the point defect is performed.

  In the present embodiment, the main TFT 20a and the redundant TFT 20b are both TFTs having IGZO as a semiconductor layer, and are formed to have the same channel length, channel width, and the like, and are redundant with the main TFT 20a. It is provided at a position close to the TFT 20b. Therefore, the electrical characteristics of these two TFTs are almost the same. Even if the TFT that drives the pixel electrode 32 before and after the repair is changed from the main TFT 20a to the redundant TFT 20b, the gradation displayed on the pixel is the same as that of both TFTs. There is very little change due to the difference in electrical characteristics, and the difference is rarely seen.

  In the present embodiment, the main TFT 20a and the redundant TFT 20b may be formed in a size such as a channel length and a channel width that have the ability to drive the pixel electrode independently, that is, in a regular size. desirable. In addition, the liquid crystal display device according to the present embodiment is not formed by connecting in parallel two TFTs each having only half the pixel electrode driving capability, and the pixel electrode is driven solely by the main TFT 20a before repair. In addition, the redundant TFT 20 b is not connected to the signal line 82. By adopting such a configuration, even if the redundant TFT 20b is provided, the parasitic capacitance generated in the signal line 82 is not increased, and the display quality is not deteriorated. In addition, as described above, the main TFT 20a and the redundant TFT 20b are formed in regular sizes such as the channel length and the channel width so that the pixel electrode can be driven independently, so that the main TFT 20a is separated by repair. However, there is no inconvenience that the driving ability is reduced by half and affects the gradation of the pixel.

  Although the description has been made with the example of the normal white mode so far, the present invention can also be applied to a normal black mode liquid crystal display device in which the transmission axes of two polarizing plates are provided in parallel. In a normal black mode liquid crystal display device, when no electric field is applied to the liquid crystal, light from the backlight is absorbed to display black (dark display), and when an electric field corresponding to white display is applied to the liquid crystal, the backlight emits light. Light is transmitted and white display (bright display) is obtained. Accordingly, the defect mechanism of the bright spot defect and the dark spot defect is also opposite to that of the normal white mode liquid crystal display device. However, the repair method described in this embodiment also applies to the normal black mode liquid crystal display device having the bright spot defect. Can be applied.

[Production method]
Next, a pixel portion including a top gate type TFT according to this embodiment and a method for manufacturing the periphery thereof will be described in the order of steps. FIG. 3 is a schematic cross-sectional view in the direction of the arrow along the line AA ′ in FIG. 2 until the repair process of the main TFT 20a is completed. Similarly, FIG. 4 is a schematic cross-sectional view in the direction of the arrow in the line BB ′ of FIG. 2 until the repair process of the redundant TFT 20b is completed. First, as shown in FIGS. 3A and 4A, the semiconductor layer 14a of the main TFT 20a and the semiconductor layer 14b of the redundant TFT 20b are formed on the substrate 11 (first step). A method for forming the semiconductor layer is not particularly limited, but a sputtering method is desirable. By using the sputtering method to form the IGZO semiconductor layer, it is possible to control the conductivity, carrier concentration, mobility, etc. to some extent by controlling the gas flow rate during film formation and the partial pressure of oxygen in the film formation atmosphere. Thus, it is possible to form a film with a more stable composition. In addition, when an amorphous IGZO semiconductor layer is formed on a plastic substrate, a sputtering method is preferable in consideration of the heat resistance of the substrate and reducing damage to the substrate.

As a sputtering target, solid InGaZnO ₄ containing In, Ga, Zn, and O (oxygen) is used. The composition ratio (stoichiometry) represented by the molecular formula of InGaZnO ₄ is In: Ga: Zn: O = 1: 1: 1: 4, but Zn and oxygen are poorer than this. For example, an oxide in which In: Ga: Zn: O is 1: 1: 0.5: 3.5 can also be used as a target before film formation. The semiconductor layer after film formation is a transparent amorphous semiconductor layer, and the composition ratio of each component of In, Ga, Zn, and O is not limited to 1: 1: 1: 4, but is approximately 1: 1: 0.5: As in 2, Zn or oxygen may be poor. In the present invention, the term “amorphous” does not mean only a completely amorphous state, but also includes those containing microcrystals as long as the gist of the present invention is not impaired.

  The formed amorphous IGZO semiconductor layer is patterned by a photolithography method or an etching method. As a result, the semiconductor layer 14a of the main TFT 20a and the semiconductor layer 14b of the redundant TFT 20b made of amorphous IGZO are formed. The etchant of the semiconductor layers 14a and 14b is not particularly limited. However, since the chemical property of IGZO is similar to that of ITO, an etchant of ITO such as oxalic acid is used regardless of before and after irradiation with ultraviolet rays. be able to. Succinic acid does not etch Al, but can etch ITO and IGZO. Since the ITO etchant can also be used as the IGZO etchant, the TFT manufacturing process can be simplified. The etching temperature may be around room temperature.

  Next, the gate insulating film 13 is formed on the entire surface of the substrate by a CVD method or the like (second step). As a result, the semiconductor layers 14 a and 14 b are covered with the gate insulating film 13. As a formation method, a CVD method is desirable, and a thermal CVD method, a plasma CVD method, or the like can be used. When it is desired to suppress an increase in the substrate temperature, for example, when a plastic substrate is used, the substrate temperature at the time of forming the gate insulating film is desirably about 250 ° C. or less, and it may be formed by a plasma CVD method. it can. Next, a first metal layer is formed and patterned to form gate electrodes 12a and 12b and a scanning line 72 (not shown) (third step). A method for forming the first metal layer is not particularly limited, but a sputtering method may be used. The material and structure of the first metal layer are as described above.

  Next, as shown in FIGS. 3B and 4B, the ultraviolet rays 22 are irradiated (fourth step). As an irradiation method, for example, the light-shielding gate electrodes 12a and 12b are used as shadow masks, from the gate electrode side toward the semiconductor layer, that is, from the surface of the substrate 11, the gate electrodes 12a and 12b, and the semiconductor layers 14a and 14b. Irradiate ultraviolet rays 22 toward the surface (surface irradiation).

  In this way, by irradiating the semiconductor layer with ultraviolet rays using the gate electrode as a shadow mask, the semiconductor layers can be selectively irradiated with ultraviolet rays. In this embodiment, since a transparent amorphous oxide made of IGZO is used as the material for the semiconductor layers of the main TFT 20a and the redundant TFT 20b, the conductivity of the semiconductor layer can be increased by irradiating it with ultraviolet rays 22. It can be as high as the conductive material. Then, by selectively irradiating a part of the semiconductor layer with such ultraviolet rays, the conductivity can be increased only in the irradiated region. Accordingly, by selectively irradiating the regions that should become the source regions 15a and 15b and the drain regions 16a and 16b in the semiconductor layers 14a and 14b of the main TFT 20a and the redundant TFT 20b, it can be used as an electrode or a conductor. Source regions 15a and 15b and drain regions 16a and 16b having conductivity can be formed.

  Therefore, it is not necessary to separately form a low-resistance semiconductor layer such as an n + amorphous silicon layer in order to connect to a source electrode made of a metal, for example, like an amorphous silicon TFT. On the other hand, the conductivity of the region of the semiconductor layer that has not been irradiated with ultraviolet rays is maintained as it was before the irradiation, so that the regions that should become the channel regions 17a and 17b of the main TFT 20a and the redundant TFT 20b. By using a light-shielding layer or the like so as not to irradiate ultraviolet rays, the region becomes a region having conductivity that can be used as a TFT channel. Details of the relationship between ultraviolet irradiation and conductivity will be described later. As described above, in the present embodiment, the main TFT 20a and the redundant TFT 20b are both irradiated with ultraviolet rays by using the gate electrode as a shadow mask to irradiate the surface with ultraviolet rays, so that the source region, the drain region, and the ultraviolet rays before ultraviolet irradiation are increased. Three regions of the channel region having conductivity are formed in a self-aligned manner with respect to the gate electrode (self-alignment).

  Next, the conditions for ultraviolet irradiation will be described in more detail. First, in the ultraviolet irradiation process, at least the semiconductor layers 14a and 14b are formed, the semiconductor layers to be the source regions 15a and 15b and the drain regions 16a and 16b are not shielded, and serve as a shadow mask. As long as the light shielding layers such as the electrodes 12a and 12b are formed at positions where the channel regions 17a and 17b are to be formed, respectively, the subsequent steps may be performed as long as the gist of the present invention is not impaired.

  Next, the irradiation conditions such as the ultraviolet light source, wavelength, irradiation energy density, and irradiation time in the ultraviolet irradiation step are as follows. The ultraviolet light source to be irradiated is preferably a surface light source. Since a surface light source is used, it is possible to uniformly irradiate ultraviolet rays at once over a wide irradiation area that covers the entire substrate. In addition, since a surface light source is used, it is not necessary to scan the substrate as in the case of a laser light source with a narrow beam spot, so double irradiation of the semiconductor layer due to scanning and accompanying in-plane variations in TFT characteristics are also caused. Does not occur. Therefore, it is possible to irradiate ultraviolet rays with uniform irradiation energy. As a result, when a large number of TFTs are formed over the entire display screen of a large area, not only simplification of the process and improvement of mass productivity, A variation in characteristics can be suppressed and uniform, and a display device with high display quality and free from variations in luminance and luminance can be obtained.

  The ultraviolet light source may be a lamp that irradiates ultraviolet rays having a specific range of wavelengths instead of a laser light source. Since a laser light source is not used, it is possible to avoid problems due to heat generation of the substrate due to the laser light, and it is possible to use a plastic film substrate. Further, an ultraviolet irradiation device that is less expensive than a laser beam irradiation device can be used. Although the kind of lamp | ramp used as an ultraviolet light source is not specifically limited, For example, a mercury lamp can be used. The wavelength of the ultraviolet light to be irradiated is desirably a wavelength ranging from about 270 nm to about 450 nm. By irradiating ultraviolet rays in this wavelength range, the conductivity of the irradiated region can be improved. The temperature and irradiation atmosphere of the substrate at the time of ultraviolet irradiation are not particularly limited, but can be performed in the air at room temperature.

Next, the irradiation energy density of ultraviolet rays and the irradiation time will be described. FIG. 5 is a graph showing the relationship between the conductivity of the amorphous IGZO semiconductor layer and the ultraviolet irradiation time when the amorphous IGZO semiconductor layer is irradiated with ultraviolet rays having an irradiation energy density of 100 mJ / sec · cm ^2. is there. From the figure, it is recognized that the increase in conductivity is saturated when irradiated at an irradiation energy density of 100 mJ / sec · cm ² for about 6 hours or more. Until then, the irradiation time is 6 hours, and the conductivity is In sample # 1, 2 × 10 ¹ S / m, which is approximately 3.33 × 10 ⁵ times (= 10 ^5.52 times), compared to 6 × 10 ⁻⁵ S / m before irradiation, and in sample # 2 the same irradiation It is recognized that it is improved exponentially to 4 S / m, which is about 10 ⁷ times that of the previous 4 × 10 ⁻⁷ S / m. That the conductivity increases exponentially from about 3.33 × 10 ⁵ times (= 10 ^5.52 times) to about 10 ⁷ times in 6 hours of irradiation, in other words, about 0.86 to about This means that the conductivity increases about an order of magnitude every 1.09 hours.

As a measure of the irradiation time of ultraviolet rays, when the irradiation energy density is 100 mJ / sec · cm ² , the conductivity after ultraviolet irradiation (target conductivity) is improved to 10 ⁿ times the conductivity before ultraviolet irradiation. In general, the irradiation may be performed with 0.86 · n hours to 1.09 · n hours (provided that 0 <n ≦ 6) as a guide. This is equivalent to about (309 · n) J / cm ² to (392 · n) J / cm ² in terms of integrated irradiation energy density (= irradiation energy density × irradiation time). Since the conductivity depends on the cumulative irradiation energy density of ultraviolet rays, for example, if the same conductivity is obtained, the irradiation time may be ¼ if the irradiation energy density is quadrupled. Therefore, the irradiation energy density and the irradiation time can be easily set if the target conductivity is determined after measuring the conductivity before irradiation, and is made of amorphous IGZO having a desired conductivity by appropriate irradiation of ultraviolet rays. A semiconductor layer can be obtained.

For example, according to the figure, the conductivity is improved to about 10 ^-1 S / m or more by irradiating with ultraviolet rays for about 4.5 hours (accumulated irradiation energy density of about 1620 J / cm ² ). Is recognized. In addition, as in sample # 1, depending on the conductivity before ultraviolet irradiation, this level of conductivity is reached even in about 3.52 hours (accumulated irradiation energy density of about 1267 J / cm ² ). And if it is such high conductivity, it can be functioned as an electrode or a conductor.

  Note that the integrated irradiation energy density of ultraviolet rays to be irradiated to the source regions 15a and 15b and the drain regions 16a and 16b is generally the resistance of the entire source region 15a, the entire 15b, and the entire drain region 16a and 16b, respectively. It is desirable that the value be lower than the on-resistance of the main TFT 20a and the redundant TFT 20b. Therefore, you may set the integrated irradiation energy density which should be irradiated from such a viewpoint. By doing in this way, the fall of signal levels, such as an image signal, by the resistance of the whole source region or the whole drain region can be made small.

  As described above, by selectively irradiating the regions to be the source regions 15a and 15b and the drain regions 16a and 16b of the semiconductor layers 14a and 14b with ultraviolet rays, the conductivity can be controlled to a desired value. Therefore, in order to form the source regions 15a and 15b and the drain regions 16a and 16b having higher conductivity than the channel regions 17a and 17b, it is not necessary to perform impurity implantation by ion doping or the like as in the prior art. 17b, drain regions 16a and 16b, and source regions 15a and 15b may have the same impurity concentration. Therefore, an expensive ion doping apparatus or the like is not required, and the manufacturing process can be rationalized, and damage to the semiconductor layer due to ion doping can be avoided. The cumulative irradiation energy density of ultraviolet rays also depends on the film thickness of the amorphous IGZO semiconductor layer, and generally requires a larger energy density as the film thickness increases.

  After the ultraviolet irradiation process as described above, as shown in FIGS. 3C and 4C, an interlayer insulating film 18 as a second insulating layer is formed on the entire surface of the substrate, and further, for the main TFT 20a. Contact hole 23ad is opened (fifth step). Thus, the semiconductor layers 14a and 14b are covered with the interlayer insulating film 18, and a contact hole 23ad for connecting to the drain region 16a of the main TFT 20a can be formed. Note that no contact hole is formed between the drain region 16b of the redundant TFT 20b and the drain electrode 26b. As a result, the repair region 24 is insulated from the end portion 16be of the drain region 16b by an insulating layer (gate insulating film 13 and interlayer insulating film 18), and a structure is formed in which both can be connected by repair in a later step. The The method for forming the interlayer insulating film 18 is not particularly limited, but a CVD method can be used. The material of the interlayer insulating film 18 is as described above. As an etching method at this time, it is desirable to use a dry etching method using plasma.

  Next, a second metal layer is formed (sixth step). By patterning the second metal layer, the drain electrode 26a, the drain electrode 26b including the repair region 24, the signal line 82, and the like are formed. Thereby, the drain electrode 26a is connected to the drain region 16a of the main TFT 20a through the contact hole 23ad. Since no contact hole is formed in the drain electrode 26b, it is insulated from the drain region 16b. Although the formation method of a 2nd metal layer is not specifically limited, You may use a sputtering system. The material and structure of the second metal layer are as described above.

  Next, a passivation layer 19 as a third insulating layer is formed on the entire surface of the substrate by CVD using silicon nitride or the like, and further, a contact hole 23as for the main TFT 20a and a contact hole 23bs for the redundant TFT 20b are opened. (Seventh step). Thus, the drain electrodes 26a, 26b and the signal line 82 made of the second metal layer are covered with the passivation layer 19, and the contact hole 23as for connecting to the source region 15a of the main TFT 20a and the source region 15b of the redundant TFT 20b are covered. A contact hole 23bs for connecting to can be formed. A method for forming the passivation layer 19 is not particularly limited, but a CVD method can be used. The material of the passivation layer 19 is as described above.

  Next, a transparent conductive layer is formed on the entire surface of the substrate by sputtering or the like, and is patterned to form pixel electrodes 32 (eighth step). The pixel electrode 32 is connected to the source region 15a of the main TFT 20a and the source region 15b of the redundant TFT 20b through the contact holes 23as and 23bs. Through the above steps, the top gate type main TFT 20a, redundant TFT 20b, pixel electrode 32, various wirings and the like using IGZO as a semiconductor layer are formed, and the cell array substrate 101 is formed.

  Next, the cell array substrate 101 formed in this way is inspected for defects (9th step). At this stage, the cell array substrate 101 is in a state where up to the pixel electrode 32 is formed, and is not yet sealed with the counter substrate and the liquid crystal is not sealed, but is defective by several methods. The pixel portion can be detected including its position. For example, in the EB tester (Electron Beam Tester) method, a storage capacitor line (not shown) is formed below the pixel electrode 32 via an insulating layer, and the storage capacitor Cs ( (Not shown) is configured in advance. A predetermined voltage is applied to the storage capacitor line, and a voltage is applied to the pixel electrode 32 of the cell array substrate 101 using the scanning line driving device 70 and the signal line driving device 80 (see FIG. 1) to store the storage capacitor. After holding the charge in Cs, each pixel electrode 32 is irradiated with an electron beam. Then, the amount of secondary electrons emitted from each pixel electrode 32 by the electron beam is detected. Since the amount of secondary electrons varies depending on the amount of charge held in the pixel electrode, it is possible to distinguish between a normal pixel and a defective pixel that cannot hold charge due to a short circuit or disconnection. And when a defect is discovered, a repair process is performed (10th step). The repair method is as described in the above-mentioned repair column.

  Next, an orientation process or the like is performed on the counter array substrate provided with the cell array substrate 101 and the color filter and the like thus repaired, and then both substrates are bonded together with a sealing material. As the sealing material, for example, an ultraviolet curable sealing material such as a photo-curing acrylic resin is used. Liquid crystal is injected between the liquid crystal substrates thus sealed, and an optical member such as a drive circuit, a polarizing plate, or a backlight is attached to complete the liquid crystal display device 100 (11th step).

  The method of manufacturing the liquid crystal display device according to the present embodiment has such a configuration, so that the main TFT 20a, the redundant TFT 20b, and the like are provided for each pixel unit 10 partitioned by the scanning line 72 and the signal line 82. A pixel electrode 32 connected to both TFTs is formed. The main TFT 20a and the redundant TFT 20b both have transparent amorphous IGZO as a semiconductor layer, and the source regions 15a and 15b and the drain regions 16a and 16b of both TFTs are transparent by selective irradiation with ultraviolet rays. It has high conductivity enough to be used as an electrode or a conductor. On the other hand, the channel regions 17a and 17b of both TFTs are not irradiated with ultraviolet rays because the light-shielding gate electrode functions as a shadow mask, and the conductivity that can be used as the channel is maintained.

  The signal line 82 is provided with a repair region 24. The drain region 16b of the redundant TFT 20b extends from the junction with the channel region 17b of the redundant TFT 20b so as to overlap the pixel electrode 32 in plan view. The drain region 16b is formed so that the end portion 16be of the drain region 16b overlaps the repair region 24 and the insulating layer (interlayer insulating film 18 and gate insulating film 13) in plan view. Therefore, the transparent drain region 16b is formed to extend under the transparent pixel electrode 32 until it reaches under the repair region 24. The repair region 24 is provided in the signal line 82 and is a part of the signal line 82, and the drain region 16 b is a part of the semiconductor layer 14 b and is interposed between the signal line 82 and the semiconductor layer 14 b. Since an insulating layer (interlayer insulating film 18 and gate insulating film 13) is formed, the drain region 16b is insulated from the repair region 24, that is, the signal line 82 before repair.

  In the inspection process, when a display defect such as a dark spot defect caused by short-circuiting the scanning line 72 with the pixel electrode 32 via the main TFT 20a is found, the pixel electrode 32 is separated from the main TFT 20a and an insulating layer ( The redundant TFT 20b functions as a switching element in place of the main TFT 20a by performing repair that short-circuits the drain region 16b and the repair region 24 insulated by the interlayer insulating film 18 and the gate insulating film 13) with a laser beam or the like. In addition, it is possible to manufacture a liquid crystal display device in which display defects such as dark spot defects are repaired and normal display is performed.

  As described above, the manufacturing method of the liquid crystal display device according to the present embodiment is such that the pixel electrode 32 is connected to the signal line 82 via the redundant TFT 20b, and the pixel electrode 32 and the signal line 82 are directly connected by welding or the like. This is different from the conventional example in which the pseudo display is performed by making the connection to make the defect inconspicuous, so that the display defect of the pixel is completely repaired and the display quality is improved.

  Further, as the semiconductor layer of the drain region 16b up to the repair region 24, a transparent amorphous IGZO that has been made highly conductive by ultraviolet irradiation and does not use amorphous silicon or polysilicon as in the conventional example. Therefore, there is no need to wire a connection pattern made of a light-shielding metal or the like between the redundant TFT 20b and the signal line 82 in advance. Therefore, even if the drain region 16b is formed so as to overlap the pixel electrode 32 in plan view, the aperture ratio of the pixel portion does not decrease.

  Furthermore, since the drain region 16b is formed in a layer different from the pixel electrode 32, it is not necessary to reduce the area of the pixel electrode as in the conventional example, and the aperture ratio does not decrease. Further, there is no need to add PEP in order to form a connection pattern made of a transparent conductive layer such as ITO in a layer different from the pixel electrode, and productivity does not decrease. In addition, since it is necessary to increase the conductivity of the drain region and the like by the above-described ultraviolet irradiation, the present embodiment does not form the drain region 16b so as to overlap the light-shielding scanning line 72. The drain region 16b is formed so as to overlap the pixel electrode 32 in plan view. Therefore, there is no increase in parasitic capacitance with the scanning line, the time constant of the waveform of the scanning signal is increased, and there is no inconvenience that the display quality is deteriorated.

  As described above, according to the manufacturing method of the liquid crystal display device according to the present embodiment, display defects such as point defects generated in the pixel portion can be repaired by using the redundant TFT, and the aperture ratio is reduced. I will not let you. In addition, a liquid crystal display device with high display quality can be manufactured without adding extra PEP. Moreover, the liquid crystal display device manufactured by this manufacturing method also has the same effect.

  In this embodiment, a TN liquid crystal display device has been described. However, the present invention is not limited to the TN type, but VA type, IPS (In-Plane Switching) type, and FFS (Fringe Field Switching) type operation modes. It can also be applied to a liquid crystal display device having In the case of FFS type and IPS type liquid crystal display devices, the present invention can be applied although there are structural differences such as the common electrode (counter electrode) provided on the cell array substrate. Further, since the normal black mode is often used in FFS type and IPS type liquid crystal display devices, it is particularly useful for repairing bright spot defects.

  In the present embodiment, the defect inspection process and the repair process have been described as being performed on the cell array substrate 101 on which the pixel electrodes 32 are formed. However, the defect inspection process and the repair process are performed in this manner. However, the present invention is not limited to this, and any process can be performed even after the counter substrate is bonded and the liquid crystal is sealed. In such a case, defect inspection can be performed, for example, by actually displaying an image, and cutting and welding can be performed by irradiating laser light in a repair process. By performing defect inspection and repair in such a process, it is possible to perform inspection and repair in a state close to a finished product, so that a special device such as an EB tester is not required, leading to cost reduction. Further, as compared with the method of inspecting defects immediately after the formation of the cell array substrate, defects generated in the panel assembling process after the formation of the cell array substrate can be collectively inspected and repaired.

[Concrete example]
Hereinafter, specific examples of the production method of the present invention will be described. On the substrate 11, first, the semiconductor layers 14 a and 14 b were formed by using a sputtering method. As a target, an ingot in which the composition ratio of each component of In, Ga, Zn, and O was 1: 1: 1: 4 was used. The input power of the sputtering apparatus was 0.5 kW. The substrate temperature during film formation was room temperature, the atmosphere was a total pressure of 0.265 Pa, and the oxygen partial pressure was 0.011 Pa. The gas flow rate during film formation was 67 sccm for Ar as a carrier gas, 22 sccm for Ar as a holder gas, and 4 sccm for oxygen. Note that sccm is an abbreviation for standard cc / min. The film formation rate is 43.2 nm / min. As a result, a transparent n-type amorphous IGZO semiconductor layer having a thickness of 100 nm could be formed on the glass substrate 11 having insulation and transparency.

As shown in FIG. 5, the electrical conductivity of this semiconductor layer is about 6 × 10 ⁻⁵ S / m to 4 × 10 ⁻⁷ S / m at room temperature, so that it can be used as a semiconductor layer of a TFT. Note that a two-probe measurement method was used to measure the conductivity. The amorphous IGZO semiconductor layer formed in this way is patterned and formed into an appropriate size and shape by using a photolithography method and an etching method, and the semiconductor layer to be the channel region, drain region, and source region of the TFT 14a and 14b were molded. As the etchant, oxalic acid having a concentration of 3.2% was used. The etching temperature was 30 ° C.

  Next, the gate insulating film 13 was formed by plasma CVD. The substrate temperature during the formation of the gate insulating film 13 was set to 200.degree. The film thickness was 300 nm. Next, a first metal layer was formed. A two-layered first metal layer having an AlNd layer as a lower layer and Mo as an upper layer was formed by sputtering, and patterned to form gate electrodes 12a and 12b and a scanning line 72. The composition of the lower AlNd layer was Al containing about 2% Nd. The thickness of the first metal layer was 300 nm. This metal layer has light shielding properties.

  Next, ultraviolet rays were irradiated from the surface of the substrate 11 toward the semiconductor layers 14a and 14b using the gate electrodes 12a and 12b as shadow masks. As a light source device, a UV irradiation device (model number UL750) manufactured by HOYA CANDEO OPTRONICS was used. This apparatus uses an ultrahigh pressure mercury lamp as a light source, and this lamp emits ultraviolet rays having a wavelength ranging from about 270 nm to about 450 nm. The temperature of the substrate 11 at the time of ultraviolet irradiation was room temperature, and the irradiation atmosphere was performed in the air. Note that after the film formation and before the ultraviolet irradiation step, annealing treatment at a special temperature in a special atmosphere was not performed. Neither laser irradiation nor ion doping was performed.

The ultraviolet irradiation energy density was 100 mJ / sec · cm ² . If it is this irradiation energy density, since it can irradiate using the general ultraviolet irradiation device used for the other use, rationalization of a manufacturing facility can be aimed at. When the irradiation time is about 4.5 hours (accumulated irradiation energy density is about 1620 J / cm ² ), the conductivity of the source region and the drain region of the main TFT 20a and the redundant TFT 20b is improved to about 10 ⁻¹ S / m. I was able to.

In addition, when the stoichiometric analysis of the IGZO semiconductor layer after ultraviolet irradiation was performed using an XPS M-Probe analyzer (SPS) XPS (X-ray photoelectron spectroscopy), In, Ga, Zn, and O (oxygen) The composition ratio of each component was about 1: 1: 0.6: 3. Further, the IGZO semiconductor layers before and after the ultraviolet irradiation are both transparent, and when X-ray diffraction is performed at an incident angle of 1 degree using the Rigaku X-ray diffractometer RINT-2000, it can be seen in the InGaZnO ₄ crystal. No diffraction peak was observed, confirming that all were amorphous IGZO semiconductor layers.

  Next, an interlayer insulating film 18 was formed by CVD using silicon oxide, and predetermined contact holes were opened. Next, a second metal layer was formed. As the second metal layer, a metal layer having a three-layer structure of Mo—Al—Mo was used. After the formation of the second metal layer, the drain electrodes 26a and 26b and the signal line 82 were formed by patterning. Next, a passivation layer 19 is formed by CVD using silicon nitride, a predetermined contact hole is opened, and then a pixel electrode 32 is formed using ITO to perform predetermined patterning. The subsequent steps are the same as those after the ninth step described in the column of the manufacturing method.

[Application Example 1]
In the present embodiment, as described above, the process includes forming the source region, the drain region, and the channel region of the main TFTs 20a and 20b in a self-aligned manner by irradiating the ultraviolet rays 22 using the gate electrodes 12a and 12b as shadow masks. Although the manufacturing method has been described, the shadow mask is not limited to the gate electrode having light shielding properties, and may be a light shielding layer such as a resist having light shielding properties. In such a manufacturing method, the source region, the drain region and the channel region of the main TFT 20a and the redundant TFT 20b are not formed in a self-alignment with the gate electrode, but the source region and the drain region are highly conductive by ultraviolet rays. After the conversion, the light shielding layer such as a resist is removed, and then the first metal layer is formed to form the gate electrode. The subsequent steps are the same as those in the fifth and subsequent steps described in the column of the manufacturing method described above, and even if such a manufacturing method is employed, the function and effect of the present invention are not impaired.

[Application 2]
In the step before forming the first metal layer to be the scanning lines and the gate electrodes 12a and 12b in the above embodiment, a step of further irradiating the semiconductor layers 14a and 14b with ultraviolet rays (referred to as “pre-ultraviolet irradiation step”). May be added. That is, the conductivity of the semiconductor layers 14a and 14b can be improved by irradiating the semiconductor layers 14a and 14b with ultraviolet rays in the step after forming the semiconductor layers 14a and 14b and before forming the first metal layer. By adding this step, even if it is not preferable to use the channel regions 17a and 17b of the TFT as it is because the conductivity at the time of film formation of the semiconductor layer is low, the conductivity is reduced by the pre-ultraviolet irradiation step. The conductivity can be improved to an appropriate level for the regions 17a and 17b.

  The pre-ultraviolet irradiation process may be performed after the semiconductor layer is formed, before the semiconductor layers 14a and 14b are patterned, or after the patterning. The pre-ultraviolet irradiation may be performed after the gate insulating film 13 is formed as long as the gate insulating film 13 is transparent. The irradiation direction of pre-ultraviolet irradiation can be either back-surface irradiation or front-surface irradiation in the case of a top gate type TFT.

  The region to be irradiated with ultraviolet rays may be the entire semiconductor layer regardless of the patterning of the semiconductor layer, or may be selectively irradiated, and at least in regions to be channel regions 17a and 17b of the main TFT 20a and redundant TFT 20b in the future. Irradiate. It should be noted that the same or different amounts of ultraviolet rays may be irradiated simultaneously or at different times on the regions that will become the source regions 15a and 15b or the drain regions 16a and 16b in the future. Since the pre-ultraviolet irradiation process is a process of controlling the conductivity of the channel regions 17a and 17b of the semiconductor layers 14a and 14b, the conductivity of the semiconductor layer after film formation is appropriate from the beginning as the conductivity of the channel regions 17a and 17b. It is not necessary to irradiate the light if it is a problem.

In the present embodiment, by irradiating the entire surface of the semiconductor layers 14a and 14b with ultraviolet rays in this pre-ultraviolet irradiation step, the channel region, drain region and source region of the main TFT 20a and redundant TFT 20b all have conductivity. It is formed as a semiconductor layer having the same target conductivity. As shown in FIG. 5, when the irradiation energy density is 100 mJ / sec · cm ² , the irradiation time of the pre-ultraviolet irradiation is about 0.41 hours to 2 hours or more (about 148 to 724 J in terms of the integrated irradiation energy density). / Cm ² or more), the conductivity can be increased to about 10 ⁻⁴ S / m (Siemens / m). In addition, if the time is about 1.47 hours to 2.81 hours or less (about 529 to 1012 J / cm ² or less in terms of integrated irradiation energy density), the conductivity can be kept at about 10 ⁻³ S / m or less. it can. By doing so, channel regions 17a and 17b having a conductivity of about 10 ⁻⁴ to 10 ⁻³ S / m can be formed.

  When the source region and the drain region are formed in a self-aligned manner with respect to the gate electrodes 12a and 12b by ultraviolet irradiation after patterning the gate electrodes 12a and 12b as described in the above embodiment, the integration is performed. The irradiation energy density can be determined in consideration of the target conductivity of the source region and the drain region and the conductivity of the source region and the drain region already increased by the pre-ultraviolet irradiation. The irradiation conditions for pre-ultraviolet irradiation are the same as those described in the above embodiment for the ultraviolet light source, the light source device, etc. other than the irradiation time and accumulated irradiation energy density, and the steps after pre-ultraviolet irradiation are as follows: This is as described in the above embodiment and its specific examples.

[Application Example 3]
The present invention can also be applied to a liquid crystal display device using a bottom gate type TFT, and an embodiment in the case of such a bottom gate type TFT will be described with reference to the drawings. Note that the bottom gate TFT and the above-described top gate TFT are only different in several points such as the order of stacking of the semiconductor layers, the gate electrodes, and the like, the structure, and the irradiation direction of ultraviolet rays. In this example, the difference will be mainly described, and the same or equivalent components as those described in the above embodiment will be denoted by the same reference numerals, and detailed description thereof will be omitted. 6 and 7 are schematic cross-sectional views of the bottom gate type main TFT 20a and the redundant TFT 20b until the end of the repair process, and correspond to FIGS. 3 and 4 which are cross-sectional views of the top gate type TFT, respectively.

  As shown in FIGS. 6A and 7A, the manufacturing method of the liquid crystal display device using the bottom gate type TFT is as follows. First, the main TFT 20a made of the first metal layer and the redundant TFT 20b are formed on the substrate 11. The gate electrodes 12a and 12b and the scanning line (not shown) are formed, and the semiconductor layers 14a and 14b are formed through the gate insulating film 13 as the first insulating layer. Next, as shown in FIG. 6B and FIG. Thereby, the source regions 15a and 15b and the drain regions 16a and 16b having high conductivity are formed in a self-aligned manner. Next, as shown in FIG. 6C and FIG. 7C, after forming the channel protective film 18 as the second insulating layer, opening the contact hole 23ad, the drain electrode 26a made of the second metal layer. 26b and the signal line 82 are formed. Thereby, the drain region 16a of the main TFT 20a is connected to the drain electrode 26a, and the end portion 16be of the drain region 16b of the redundant TFT 20b and the drain electrode 26b are insulated via the channel protective film 18, and the drain electrode 26b. A repair region 24 is formed in a part of the same as described above in the present embodiment. Then, a passivation layer 19 which is a third insulating layer is formed, and contact holes 23as and 23ad are opened, and a pixel electrode 32 made of ITO or the like is formed. Thereby, the source regions 15a and 15b of the main TFT 20a and the redundant TFT 20b are connected to the pixel electrode 32. The subsequent steps are the same as those of the top gate type including the repair step.

  As described above, the stacking order and the cross-sectional structure of the bottom gate TFT are such that after the gate electrodes 12a and 12b are formed on the substrate, the semiconductor layers 14a and 14b are formed on the gate insulating film via the gate insulating film 13. This is different from the top gate type TFT in which the semiconductor layers 14 a and 14 b are formed on the substrate and then the gate electrodes 12 a and 12 b are formed on the gate insulating film via the gate insulating film 13.

  Further, reference numeral 18 in FIGS. 6 and 7 in the bottom gate type TFT is an insulating layer called a channel protective film, and the material thereof is preferably a silicon oxide system having insulation and transparency. Since the channel protective film 18 is in contact with IGZO, when silicon nitride is used as a channel protective film by the CVD method, nitrogen of ammonia used as one of the source gases is combined with oxygen in the IGZO to convert oxygen in the IGZO. It tends to be deficient, and the characteristics of IGZO tend to change. Such inconvenience does not occur if the silicon oxide system is used, and the composition of IGZO can be maintained by using the silicon oxide system. Further, the thickness of the channel protective film may be 200 nm or less. In the case of a bottom gate TFT, the repair region 24 and the drain region 16b of the drain electrode 26b are insulated by the channel protective film 18.

  Further, regarding the ultraviolet irradiation process of the fourth step described in the column of the manufacturing method in the case of the top gate type, the irradiation direction of the ultraviolet ray is as shown in FIGS. 6B and 7B in the case of the bottom gate type TFT. As shown in FIG. 3 (b) and FIG. 4 (b), the semiconductor layers 14a and 14b are irradiated with the semiconductor layers 14a and 14b from the substrate 11 side as shown in FIG. It differs from the top gate type TFT which irradiates the substrate 11 from the side (surface irradiation). However, both the top gate type and the bottom gate type are the same in that ultraviolet rays are irradiated from the gate electrodes 12a and 12b toward the semiconductor layers 14a and 14b, thereby forming a self-aligned TFT. .

  In the repair process, in the case of a bottom gate type TFT, as shown in FIG. 7D, the repair region 24 is irradiated with laser light to break through the channel protective film 18 and drain electrode 26b and drain region 16b. As shown in FIG. 4D, the repair region 24 is irradiated with laser light to break through the interlayer insulating film 18 and the gate insulating film 13, thereby welding the drain electrode 26b and the drain region 16b. This is different from the top gate type TFT.

  Note that in the case of using a bottom gate TFT, when pre-ultraviolet irradiation is performed, it is preferable to perform surface irradiation after forming the semiconductor layer. Thereby, the whole semiconductor layer can be made highly conductive without being shielded by the gate electrodes 12a and 12b. About the process of pre-ultraviolet irradiation, it does not ask before and after patterning of a semiconductor layer. Except for the above several points, the bottom gate TFT and the top gate TFT have substantially the same planar structure, stacking order, cross-sectional structure, and manufacturing method of the pixel portion and its periphery, and in view of the gist of the present invention, The above differences do not prevent the present invention from being applied to a pixel portion using a bottom gate TFT and its peripheral portion. Therefore, the present invention can also be used for a liquid crystal display device using a bottom gate type TFT.

  The liquid crystal display device manufactured as described above can be used as a television receiver, a monitor for a personal computer, a mobile phone, an in-vehicle monitor, a game machine, and other flat panel displays. Note that FIGS. 1 to 7 simply describe the main members and the relationships between the members related to the present embodiment in a simplified manner in order to explain the present embodiment. In addition to those mentioned in the above description, many members are used to configure the TFT and the display device. However, they are well known to those skilled in the art and will not be described in detail here. The display device described in this embodiment mode is merely an example, and other display devices are included in the scope of the present invention as long as those skilled in the art can arbitrarily select them.

  The present invention has been described with reference to the specific embodiments shown in the drawings, but the present invention is not limited to the embodiments shown in the drawings, and so far as long as the effects of the present invention are exhibited. It goes without saying that any known configuration can be employed.

DESCRIPTION OF SYMBOLS 10 ... Pixel part 11 ... Substrate 12a, 12b ... Gate electrode 13 ... Gate insulating film (1st insulating layer)
14a, 14b ... Semiconductor layer 15a, 15b ... Source region 16a, 16b ... Drain region 16be ... End 17a, 17b ... Channel region 18 ... Interlayer insulating film or channel protective film (second insulating layer)
19: Passivation layer (third insulating layer)
20a ... Main TFT
20b ... Redundant TFT
22 ... UV 23ad, 23as, 23bs ... Contact hole 24 ... Repair area 24e ... Welding portion 25a, 25b ... Source electrode 26a, 26b ... Drain electrode 32 ... Pixel electrode 72 ... Scan line 82 ... Signal line 97, 98 ... Cut 99 ... Liquid crystal 100 ... Liquid crystal display device 101 ... Cell array substrate

Claims (15)

In a method for manufacturing a liquid crystal display device, a liquid crystal is sandwiched between opposing substrates, and a plurality of signal lines intersecting each other, a plurality of scanning lines, and pixel electrodes corresponding to the intersections are provided on one of the substrates. There,
The first semiconductor layer of the first thin film transistor including the first source region and the first drain region, and the end portion extending to the repair region so as to overlap the second source region and the pixel electrode in plan view, Forming a second semiconductor layer of a second thin film transistor having a second drain region formed so as to overlap in plan view across an insulating layer, from an amorphous oxide containing In, Ga and Zn;
By irradiating the first semiconductor layer and the second semiconductor layer with ultraviolet rays from the side of the gate electrode connected to the scanning line and having a light shielding property, the first semiconductor layer and the second semiconductor layer are irradiated before irradiation. A second step of increasing the conductivity,
A third step of forming the insulating layer on the first semiconductor layer and the second semiconductor layer;
The signal line including the repair region connected to the first drain region and connected to the second drain region by short-circuiting with the second drain region is formed on the insulating layer. 4 steps,
A fifth step of forming the pixel electrode and connecting the pixel electrode to the first source region and the second source region;
And a sixth step of repairing a display defect by separating the first thin film transistor from the pixel electrode and short-circuiting the second drain region and the signal line in the repair region. Production method. The method of manufacturing a liquid crystal display device according to claim 1, wherein the sixth step includes a step of repairing the first thin film transistor by separating the first thin film transistor from the signal line. 3. The method of manufacturing a liquid crystal display device according to claim 1, wherein the repair in the sixth step is performed by laser light irradiation. 4. The resistances of the first drain region and the second drain region after irradiation with the ultraviolet light are lower than on-resistances of the first thin film transistor and the second thin film transistor, respectively. A method for producing a liquid crystal display device according to any one of the above. The impurity concentration of the channel region of the first thin film transistor and the second thin film transistor is the same as the impurity concentration of the first source region, the first drain region, the second source region, and the second drain region. A method for manufacturing a liquid crystal display device according to any one of claims 1 to 4. 6. The method for manufacturing a liquid crystal display device according to claim 1, wherein the light source for irradiating the ultraviolet light is a surface light source. The method for manufacturing a liquid crystal display device according to claim 1, wherein the light source for irradiating the ultraviolet rays is a mercury lamp. 8. The method for manufacturing a liquid crystal display device according to claim 1, wherein the wavelength of the ultraviolet ray ranges from 270 nm to 450 nm. The cumulative irradiation energy density of ultraviolet rays in the second step is (309 · n) to (392 · n) J / cm ² when the conductivity is increased 10 ⁿ times (where 0 <n ≦ 6). A method for manufacturing a liquid crystal display device according to claim 1, wherein: 10. The method of manufacturing a liquid crystal display device according to claim 1, wherein an integrated irradiation energy density of ultraviolet rays in the second step is 1620 J / cm ² or more. 11. 11. The method of manufacturing a liquid crystal display device according to claim 1, wherein an irradiation energy density of ultraviolet rays in the second step is 100 mJ / sec · cm ² . Between the first step and the second step, the amorphous first semiconductor having higher conductivity than before the ultraviolet irradiation by irradiating the first semiconductor layer and the second semiconductor layer with ultraviolet rays. The method for manufacturing a liquid crystal display device according to claim 1, further comprising a pre-ultraviolet irradiation step for forming the layer and the second semiconductor layer. 13. The method of manufacturing a liquid crystal display device according to claim 12, wherein an integrated irradiation energy density of ultraviolet rays in the pre-ultraviolet irradiation step is 148 to 1012 J / cm < ² >. A liquid crystal display device comprising a plurality of signal lines, a plurality of scanning lines, and a pixel electrode corresponding to each of the intersections sandwiching liquid crystal between opposing substrates and intersecting each other on one of the substrates,
A first gate electrode connected to the scanning line, a first drain region having a higher conductivity than before irradiation by irradiation of ultraviolet rays, and a first source region connected to the pixel electrode. A first thin film transistor composed of a first semiconductor layer made of an amorphous oxide containing Zn;
A second gate electrode connected to the scanning line and an end portion extending to the repair region so as to be higher in conductivity than before irradiation by the irradiation of the ultraviolet rays and to overlap with the pixel electrode in plan view And a second drain region formed so as to overlap in a plan view across an insulating layer, and a second source region connected to the pixel electrode and having a higher conductivity than before irradiation by irradiation of the ultraviolet light, In, A second thin film transistor composed of a second semiconductor layer made of an amorphous oxide containing Ga and Zn;
The signal line including the repair region connected to the second drain region by being connected to the first drain region and being short-circuited to the second drain region. A liquid crystal display device. 15. The liquid crystal display according to claim 14, wherein the signal line is connected to the second drain region by the repair, and repair is performed so as to separate the first thin film transistor from the pixel electrode. apparatus.

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