KR20130071998A - Thin film transistor panel for flat panel display device and method for manufacturing the same - Google Patents
Thin film transistor panel for flat panel display device and method for manufacturing the same Download PDFInfo
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- KR20130071998A KR20130071998A KR1020110139532A KR20110139532A KR20130071998A KR 20130071998 A KR20130071998 A KR 20130071998A KR 1020110139532 A KR1020110139532 A KR 1020110139532A KR 20110139532 A KR20110139532 A KR 20110139532A KR 20130071998 A KR20130071998 A KR 20130071998A
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13458—Terminal pads
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136213—Storage capacitors associated with the pixel electrode
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
Abstract
Description
The present invention relates to a thin film transistor substrate for a flat panel display and a method of manufacturing the same. In particular, the present invention provides a method of manufacturing a thin film transistor substrate for a flat panel display device and a flat panel display device using the method by performing a back etch process of a semiconductor channel layer using a second gate insulating layer etching process. It relates to a thin film transistor substrate for use.
2. Description of the Related Art Recently, various flat panel display devices capable of reducing weight and volume, which are disadvantages of cathode ray tubes (CRTs), have been developed. The flat panel display includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an electroluminescence device. Due to mass production technology, ease of driving means, high definition, and low power driving means, liquid crystal displays or organic electroluminescent displays using substrates in which thin film transistors (TFTs) are arranged in a matrix array have been spotlighted. I am getting it.
The active matrix thin film transistor substrate is a method of driving a pixel using an amorphous silicon thin film transistor (a-Si TFT) as a switching device. Amorphous silicon is mainly used as a switching element of a thin film transistor substrate for a flat panel display because of low manufacturing cost and low temperature.
A thin film transistor substrate for a vertical field type liquid crystal display according to the prior art will be described with reference to the drawings. 1 is a plan view illustrating a structure of a thin film transistor substrate constituting a vertical field type liquid crystal display device according to the related art. 2A through 2D are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate for a vertical field type liquid crystal display device according to the related art, taken along the line II ′ of FIG. 1.
Referring to FIG. 1, a thin film transistor substrate for a vertical field type liquid crystal display device includes a plurality of gate lines GL running in a horizontal direction on a transparent glass substrate SUB, and a plurality of data lines DL running in a vertical direction. ). The pixel area is defined by the crossing of the gate line GL and the data line DL. The thin film transistor T is disposed in one corner of the pixel region.
The thin film transistor T may include a gate electrode G branching from the gate line GL, a source electrode S branching from the data line DL, and a drain electrode facing away from the source electrode S by a predetermined distance. (D). The pixel electrode PXL to which the pixel voltage corresponding to the image signal is applied is connected to the drain electrode D according to the switching operation of the thin film transistor T.
In order to drive the liquid crystal cell, there must be a common voltage opposite to the pixel voltage. In the case of the vertical electric field type liquid crystal display, the pixel electrode PXL and the common electrode COM are spaced apart from each other in a direction perpendicular to the plane of the substrate, and the electric field is caused by the voltage difference between the pixel voltage and the common voltage. To form. Liquid crystal cells are rearranged according to the size of the electric field, and an image is realized by using optical anisotropy characteristics of the liquid crystal cells. In the vertical field type liquid crystal display, a common electrode is formed on the upper substrate bonded to the thin film transistor substrate.
A portion of the pixel electrode PXL is formed so as to overlap the adjacent gate line GL with the gate insulating film GI and the protective film PAS interposed therebetween. In this way, the portion where the pixel electrode PXL and the gate wiring GL overlap each other forms the storage capacitor STG.
Such a thin film transistor substrate for a flat panel display device is determined for its characteristics and performance due to various factors. In particular, the more complex the manufacturing process, the more factors that affect performance and properties. Therefore, if possible, it is important to simplify the manufacturing process. Hereinafter, a process of manufacturing a thin film transistor substrate for a liquid crystal display device will be described with reference to FIGS. 2A to 2D. Here, the case where four mask processes are used is demonstrated.
A gate metal material is deposited on the transparent substrate SUB and patterned by a first mask process to form a gate material. The gate material includes a gate line GL, a gate electrode G, and a gate pad GP. The gate line GL runs in the horizontal direction on the surface of the substrate SUB. The gate electrode G branches from the gate wiring to the pixel region and is disposed at one corner of the pixel region. The gate pad GP is disposed at one end of the gate line GL (FIG. 2A).
A gate insulating layer GI including an insulating material is coated on the entire surface of the substrate SUB on which the gate material is formed. For the insulating property of the gate insulating film GI, a single gate insulating film GI having a thickness of 4000 kPa to 8000 kPa is formed or a double gate insulating film GI having a thickness of 2000 kPa to 4000 kPa, respectively. On the gate insulating film GI, a semiconductor material, an impurity semiconductor material, and a source-drain metal material are sequentially applied. In the case of a semiconductor material, a semiconductor material containing amorphous silicon and a semiconductor material containing impurities are successively applied. The second mask process simultaneously patterns the source-drain metal material, the impurity semiconductor material, and the semiconductor material to form the semiconductor channel layer A, the impurity semiconductor layer n +, the data wiring DL, the data pad DP, and the source electrode. (S) and the drain electrode D are formed. The semiconductor channel layer A is formed to cover the gate electrode G on the gate insulating layer GI. The data line DL is disposed to be orthogonal to the gate line GL with the gate insulating layer GI interposed therebetween. The data pad DP is formed at one end of the data line DL. The source electrode S is branched from the data line DL to contact one side of the semiconductor channel layer A. FIG. The drain electrode D faces the source electrode S at a predetermined distance, and contacts the other side of the semiconductor channel layer A. FIG. An impurity semiconductor layer n + interposed between the contact surface of the semiconductor channel layer A and the source electrode S and the contact surface of the semiconductor channel layer A and the drain electrode D is formed. Thus, the thin film transistor T is completed. In the exposed portion of the gate insulating layer GI, the source-drain metal material, the impurity semiconductor material, and the semiconductor material are removed, and only the source-drain metal material and the impurity semiconductor material are removed between the source electrode S and the drain electrode D. do. Thus, in order to make the etching degree different from one mask process, it is preferable to use a half-tone mask or a partial exposure mask in a 2nd mask process. A dummy layer including an impurity semiconductor material and a semiconductor material is formed under the data pad DP (FIG. 2B).
The passivation layer PAS including silicon nitride (SiNx) or silicon oxide (SiOx) is coated on the substrate SUB on which the thin film transistor T is completed, and patterned through a third mask process to form contact holes. The contact holes include a gate pad contact hole GPH exposing the gate pad GP, a data pad contact hole DPH exposing the data pad GP, and a drain contact hole DH exposing a part of the drain electrode D. ). When forming the contact holes, the gate pad contact hole GPH etches the passivation layer PAS and the gate insulating layer GI, while the data pad contact hole DPH and the drain contact hole DH are passivation layer PAS. Only etch. Therefore, it is preferable to use a half-tone mask or a partial exposure mask also for the third mask process (FIG. 2C).
A transparent conductive material including indium tin oxide (ITO) or indium zinc oxide (IZO) is coated on the substrate SUB on which the contact holes GPH, DPH, and DH are completed, and patterned using a fourth mask process to form a pixel electrode ( PXL, the gate pad terminal GPT, and the data pad terminal DPT. The pixel electrode PXL is connected while directly contacting the drain electrode D through the drain contact hole DH. The gate pad terminal GPT contacts the gate pad GP through the gate pad contact hole GPH. The data pad terminal DPT contacts the data pad DP through the data pad contact hole DPH. A portion of the pixel electrode PXL is formed to overlap the neighboring gate line GL with the gate insulating layer GI and the passivation layer PAS therebetween. This overlapping portion forms the storage capacitor STG (FIG. 2D).
In the prior art described above, the gate insulating film has a thickness of 4000 kPa to 8000 kPa whether it is a single film or a double film. If the gate insulating film is thick, the parasitic capacitance generated between the gate electrode and the source electrode can be reduced, which is preferable for device characteristics. However, there is a disadvantage that occurs due to the thick gate insulating film. For example, since the gate insulating film and the protective film are interposed at a portion where the storage capacitor is formed, there may be a problem in forming a sufficient storage capacitor. In addition, when forming the pad contact hole exposing the pad part, the etching time is required because the gate insulating film and the protective film must be etched.
In addition, in the above-described method for manufacturing a thin film transistor substrate, a step of back etching the channel layer A using the source-drain electrode as a mask is required. When the etching rate is increased in order to shorten the time required for the back etch process, the etching uniformity of the semiconductor channel layer A due to the back etch is not constant, which causes a factor of deteriorating device characteristics. If the back etch time is sufficiently long to prevent this, a problem arises in that the production yield is lowered.
SUMMARY OF THE INVENTION An object of the present invention is to provide a thin film transistor substrate for a flat panel display and a method of manufacturing the same, which are designed to overcome the above problems and improve the performance and characteristics of a semiconductor channel layer. Another object of the present invention is to maintain a sufficient thickness of the gate insulating film between the gate electrode and the source electrode to reduce the parasitic capacitance, and in the auxiliary capacitor portion by reducing the thickness of the
In order to achieve the object of the present invention, a thin film transistor substrate for a flat panel display according to the present invention includes a gate wiring and a data wiring defining a pixel region by crossing each other with a first gate insulating film and a second gate insulating film interposed therebetween. ; A gate electrode branching from the gate wiring, a channel layer overlapping the gate electrode and formed on the first gate insulating film and the second gate insulating film, a source electrode branching from the data wiring and in contact with one side of the channel layer; A thin film transistor including a drain electrode facing the source electrode and in contact with the other side of the channel layer; A passivation layer covering the thin film transistor; And a pixel electrode in contact with the drain electrode and formed on the first insulating layer and the passivation layer in the pixel area.
And an auxiliary capacitance extending from the pixel electrode and overlapping a portion of the gate wiring with the first gate insulating layer and the passivation layer interposed therebetween.
A gate pad formed on one end of the gate wiring; A gate pad contact hole penetrating the first gate insulating layer and the passivation layer covering the gate pad and exposing a portion of the gate pad; And a gate pad terminal contacting the gate pad through the gate pad contact hole.
A data pad formed at one end of the data line; A data pad contact hole penetrating the passivation layer covering the data pad to expose a portion of the data pad; And a data pad terminal contacting the data pad through the data pad contact hole.
In addition, a method of manufacturing a thin film transistor for a flat panel display according to the present invention includes forming a gate element on a substrate; Successively applying a first gate insulating film, a second gate insulating film, a semiconductor layer, an impurity semiconductor layer, and a source-drain metal layer covering the gate element; Forming a photoresist pattern on the source-drain metal layer, the photoresist pattern having a first thickness in the source-drain region and having a second thickness thinner than the first thickness in the channel layer region; Etching the source-drain metal layer, the impurity semiconductor layer, and the semiconductor layer using the photoresist as a mask; Exposing the photoresist metal layer to a region of the channel layer by thinning the photoresist by the second thickness; Etching the source-drain metal layer using the thinned photoresist as a mask to form a source electrode and a drain electrode, and exposing the impurity semiconductor layer; And removing the exposed impurity semiconductor layer while etching and removing the second gate insulating layer using the thinned photoresist as a mask, and back-etching the semiconductor layer to complete the thin film transistor.
In the step of completing the thin film transistor, the ratio of the etch rate of the second gate insulating layer and the etch rate of the impurity semiconductor layer and the semiconductor layer is 2: 1 to 4: 1.
In the step of completing the thin film transistor, the ratio of the amount of etching gas for etching the second gate insulating film and the amount of the etching gas for etching the impurity semiconductor layer and the semiconductor layer is 2: 1 to 4: 1. It features.
The etching gas for etching the second gate insulating layer includes sulfur fluoride (SF 6 ) gas, and the etching gas for etching the impurity semiconductor layer and the semiconductor layer includes a chlorine (Cl 2 ) gas. It is done.
Applying a passivation layer covering the thin film transistor and forming a drain contact hole exposing the drain electrode; And forming a pixel electrode contacting the drain electrode through the drain contact hole with a transparent conductive material on the passivation layer.
The forming of the pixel electrode may further include forming a storage capacitor that extends from the pixel electrode and overlaps a portion of the gate element with the first gate insulating layer and the passivation layer interposed therebetween.
In the thin film transistor substrate for a flat panel display device according to the present invention, the thickness of the gate insulating film disposed between the gate electrode and the source electrode maintains a sufficient thickness to prevent parasitic capacitance, whereas the auxiliary capacitor portion has a half thickness to provide sufficient auxiliary. Capacity can be secured. In addition, since the gate insulating film covering the pad part has a half thickness, the time for forming the pad contact hole is shortened, thereby increasing productivity. On the other hand, by performing back etching of the semiconductor channel layer by etching the gate insulating layer to half thickness, the etching rate of the channel layer can be controlled to be low, thereby improving the back etch uniformity of the channel layer, thereby improving the characteristics of the device. Can be.
1 is a plan view showing the structure of a thin film transistor substrate constituting a vertical field type liquid crystal display device according to the prior art.
2A to 2D are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate for a vertical field type liquid crystal display device according to the related art, taken along the line II ′ in FIG. 1.
3 is a plan view showing the structure of a thin film transistor substrate for flat panel display according to the present invention;
4A to 4F are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate for a flat panel display according to the present invention, taken along the line II-II ′ of FIG. 3.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.
Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 3 to 4F. 3 is a plan view illustrating a structure of a thin film transistor substrate for a flat panel display according to the present invention. 4A to 4F are cross-sectional views illustrating a manufacturing process of a thin film transistor substrate for a flat panel display according to the present invention, taken along the line II-II ′ of FIG. 3.
Referring to FIG. 3, a thin film transistor substrate for a flat panel display device includes a plurality of gate lines GL running in a horizontal direction on the transparent glass substrate SUB, and a plurality of data lines DL running in a vertical direction. do. The pixel area is defined by the crossing of the gate line GL and the data line DL. The thin film transistor T is disposed in one corner of the pixel region.
The thin film transistor T may include a gate electrode G branching from the gate line GL, a source electrode S branching from the data line DL, and a drain electrode facing away from the source electrode S by a predetermined distance. (D). The pixel electrode PXL to which the pixel voltage corresponding to the image signal is applied is connected to the drain electrode D according to the switching operation of the thin film transistor T.
In the case of a flat panel display such as a liquid crystal display, there must be a common voltage opposite to the pixel voltage. In the case of the vertical electric field type liquid crystal display, the pixel electrode PXL and the common electrode COM are spaced apart from each other in a direction perpendicular to the plane of the substrate, and the electric field is caused by the voltage difference between the pixel voltage and the common voltage. To form. Liquid crystal cells are rearranged according to the size of the electric field, and an image is realized by using optical anisotropy characteristics of the liquid crystal cells. In the vertical field type liquid crystal display, a common electrode is formed on the upper substrate bonded to the thin film transistor substrate.
In the case of the organic light emitting display device, the pixel electrode PXL becomes a first electrode of the organic light emitting diode, and an organic material layer and a second electrode layer are stacked on the pixel electrode PXL. Therefore, in the case of a vertical field type liquid crystal display device or an organic light emitting display device thin film transistor substrate, the pixel electrode PXL is formed in a rectangular shape occupying most of the pixel region.
On the other hand, in the case of a horizontal electric field display device, both the pixel electrode PXL and the common electrode are formed on the thin film transistor substrate. Horizontal electric field display devices are largely classified into two types. One is an In Plane Switching (IPS) method in which the pixel electrode PXL and the common electrode form a horizontal electric field in a form in which they are arranged at regular intervals on the same plane. The other is a fringe field switching (FFS) method using a fringe field formed by overlapping the pixel electrode PXL and the common electrode with an insulating film interposed therebetween.
In the IPS method, the pixel electrode PXL has a bar line shape. In the FFS method, the pixel electrode PXL may be formed in a rectangular shape or may have a bar line shape. In FIG. 3, the pixel electrode PXL has a rectangular shape that occupies most of the pixel region in order to represent a general thin film transistor substrate.
A portion of the pixel electrode PXL is formed so as to overlap the adjacent gate line GL with the gate insulating film GI and the protective film PAS interposed therebetween. In this way, the portion where the pixel electrode PXL and the gate wiring GL overlap each other forms the storage capacitor STG.
Hereinafter, a process of manufacturing a thin film transistor substrate for a flat panel display according to the present invention will be described in detail with reference to FIGS. 4A to 4F.
A gate metal is coated on the transparent substrate SUB and patterned by a first mask process to form a gate element. The gate element may include a gate line GL running in a horizontal direction on the substrate SUB, a gate pad GP disposed at one end of the gate line GL, and a gate electrode branched to the pixel region from the gate line GL. (G). (Fig. 4A)
The first gate insulating layer GI1 and the second gate insulating layer GI2 are successively coated with a material such as silicon oxide SiOx or silicon nitride SiNx on the substrate SUB on which the gate element is formed. Each of the first gate insulating layer GI1 and the second gate insulating layer GI2 is preferably coated to have a thickness of 2000 GPa to 4000 GPa. Subsequently, the semiconductor layer SE, the impurity semiconductor layer n +, and the source-drain metal layer SD are successively coated on the second gate insulating layer GI2. Photoresist PR is applied on the source-drain metal layer SD, and the photoresist PR is patterned by a second mask process. In this case, the portion where the data line DL, the source electrode S, the drain electrode D, and the data pad DP are to be formed has a first thickness, and the portion where the channel layer A is to be formed ( ②), photoresist PR is patterned to have a second thickness thinner than the first thickness. For this purpose, it is preferable to use a half-tone mask in the second mask process. The region (2) on which the channel layer (A) is to be formed is etched simultaneously using the thin photoresist (PR) pattern as a mask, the source-drain metal layer (SD), the impurity semiconductor layer (n +), and the semiconductor layer (SE). . (FIG. 4B)
The photoresist PR is covered only to the extent that the photoresist PR of the
As a result, the top layer of the substrate SUB is divided into a portion where the second gate insulating layer GI2 is exposed, a portion where the photoresist PR remains, and a portion where the impurity semiconductor layer n + is exposed. In this state, the impurity semiconductor layer n + exposed between the second gate insulating film GI2 and the source electrode S and the drain electrode D is etched and removed using the photoresist PR as a mask. The present invention is to complete the thin film transistor T by forming the channel layer A by completely removing the impurity semiconductor layer n + by etching during the etching process of completely removing the second gate insulating layer GI2. It features. (FIG. 4D)
For example, the second gate insulating layer GI2 may be a silicon nitride (SiNx) layer having a thickness of 3500 GPa, and the impurity semiconductor layer n + may be an amorphous silicon (a-Si) layer having a thickness of 1000 GPa. . In this case, in order to remove all the impurity semiconductor layer n + during the time of etching and removing all of the silicon nitride, which is the second gate insulating layer GI2, the etching rate of a-Si may be set to 3.5: 1. For this purpose, it is preferable to mix a mixing ratio of sulfur fluoride (SF 6 ) gas, which is a gas for etching silicon nitride, and chlorine (Cl 2 ) gas, which is a gas for etching amorphous silicon, at 3.5: 1.
In addition, even after all of the impurity semiconductor layer n + exposed between the source electrode S and the drain electrode D is removed, the semiconductor layer SE may be removed to some extent to improve device characteristics. Since the semiconductor layer SE is also the same material as the impurity semiconductor layer n +, if the second gate insulating layer GI2 is further etched, the semiconductor layer SE is back etched to complete the channel layer A. FIG.
In addition, if the etching rate of a-Si relative to SiNx is adjusted to 3: 1 without increasing the additional etching time for back etching, the impurity semiconductor layer n + of 1000 ns is removed while the second gate insulating layer GI2 of 3500 ns is removed. ) Is removed, the semiconductor layer SE is back etched to about 170 kPa. The etching rate of a-Si relative to SiNx is between 2: 1 and 4: 1 depending on the thickness of the second gate insulating layer GI2 and the impurity semiconductor layer n +, and depending on the depth of the semiconductor layer SE back etched. It is preferable to select appropriately.
In another method, when the etching ratio is maintained at 3.5: 1 and the impurity semiconductor layer n + is set to 500 ns, the etching process for removing the second gate insulating layer GI2 is completed. n +) is removed and back etch is performed 500 ms. That is, in the present invention, the thickness of the second gate insulating layer GI2, the thickness of the impurity semiconductor layer n +, and the back etch depth of the semiconductor layer SE are considered within the etching process time of the second gate insulating layer GI2. It is preferable to adjust the etching rate so that the impurity semiconductor layer (n +) and the back etch can be completed.
As such, during the process of etching and removing the second gate insulating layer GI2, the etching rate and / or the thickness of each etching layer are adjusted to remove the impurity semiconductor layer n + and back-etch the semiconductor layer SE, thereby performing a channel layer. (A) can be completed. Using this method, since the back etch is performed based on the time for etching the relatively thick second gate insulating layer GI2, the back etch time is significantly slower than in the related art. Thus, the back etch uniformity of the channel layer A can be precisely adjusted. As a result, it is possible to improve the uniformity of the characteristics of the plurality of thin film transistors formed over a large area.
It is also possible to adjust the back etch rate so that the thickness of the channel layer A can be precisely adjusted. In particular, the thickness of the channel layer (A) can be formed to have a uniform thickness while forming a thinner than the conventional manufacturing method, it is possible to improve the characteristics of the device.
On the other hand, in the present invention, the second gate insulating film GI2 has a structure that continues to exist between the gate electrode G and the source electrode S and between the gate wiring GL and the data wiring DL. Therefore, the gate electrode G and the source electrode D can be formed to be separated by a sufficient distance, so that parasitic capacitance does not occur therebetween. In addition, the insulation between the gate wiring GL and the data wiring DL can be sufficiently ensured.
An insulating film is coated on the entire surface of the substrate SUB on which the thin film transistor T is completed to form a passivation film PAS. The passivation layer PAS is patterned by a third mask process to form a drain contact hole DH exposing a part of the drain electrode D and a data pad contact hole DPH exposing a part of the data pad DP. . At the same time, the first gate insulating layer GI1 is also etched to form a gate pad contact hole GPH exposing a part of the gate pad GP. (FIG. 4E)
In the present invention, the gate insulating film is formed by dividing it into two layers. Therefore, the thickness of the first gate insulating film GI1 of the present invention is about 1/2 of the thickness of the gate insulating film GI according to the prior art. Therefore, the time for etching the first gate insulating film GI1 to form the gate pad contact hole GPH is shortened by half than the time for etching the gate insulating film GI in the related art. Thus, process time can be shortened and production yield can be further increased.
A transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO) is coated on the passivation layer PAS on which contact holes are formed. The transparent conductive material is patterned by a fourth mask process, and connected to the drain electrode D through the drain contact hole DH and formed in the pixel area through the pixel electrode PXL and the gate pad contact hole GPH. A gate pad terminal GPT connected to the GP and a data pad terminal DPT connected to the data pad DP are formed through the data pad contact hole DPH. In addition, a part of the pixel electrode PXL partially overlaps the gate line GL to form the storage capacitor STG. (FIG. 4F)
The storage capacitor STG according to the present invention has a structure in which a first gate insulating film GI1 and a protective film PAS are interposed between a gate wiring GL as a first electrode and a pixel electrode PXL as a second electrode. Have In the present invention, the gate insulating film is formed by dividing it into two layers. Therefore, the thickness of the first gate insulating film GI1 of the present invention is about 1/2 of the thickness of the gate insulating film GI according to the prior art. Therefore, the thickness of the insulating film constituting the storage capacitor STG can be made thin, whereby the charge capacitance of the storage capacitor STG becomes much larger. Therefore, even if the size of the electrode for forming the storage capacitor STG is made small, the same charge storage capacitance can be obtained, and thus the aperture ratio can be further improved.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.
SUB: transparent substrate T: thin film transistor
GL: gate wiring DL: data wiring
G: gate electrode S: source electrode
D: drain electrode A: (semiconductor) channel layer
n +: impurity semiconductor layer SE: semiconductor layer
GI: gate insulating film PR: photoresist
GI1: second gate insulating film GI2: second gate insulating film
GP: gate pad DP: data pad
PAS: Protective Film DH: Drain Contact Hole
GPH: gate pad contact hole DPH: data pad contact hole
GPT: Gate pad terminal DPT: Data pad terminal
PXL: pixel electrode STG: auxiliary capacitance
Claims (10)
A gate electrode branching from the gate wiring, a channel layer overlapping the gate electrode and formed on the first gate insulating film and the second gate insulating film, a source electrode branching from the data wiring and in contact with one side of the channel layer; A thin film transistor including a drain electrode facing the source electrode and in contact with the other side of the channel layer;
A passivation layer covering the thin film transistor; And
And a pixel electrode in contact with the drain electrode and formed on the first insulating layer and the passivation layer in the pixel region.
And a storage capacitor extending from the pixel electrode and overlapping a portion of the gate wiring with the first gate insulating layer and the passivation layer interposed therebetween.
A gate pad formed on one end of the gate wiring;
A gate pad contact hole penetrating the first gate insulating layer and the passivation layer covering the gate pad and exposing a portion of the gate pad; And
And a gate pad terminal in contact with the gate pad through the gate pad contact hole.
A data pad formed at one end of the data line;
A data pad contact hole penetrating the passivation layer covering the data pad to expose a portion of the data pad; And
And a data pad terminal contacting the data pad through the data pad contact hole.
Successively applying a first gate insulating film, a second gate insulating film, a semiconductor layer, an impurity semiconductor layer, and a source-drain metal layer covering the gate element;
Forming a photoresist pattern on the source-drain metal layer, the photoresist pattern having a first thickness in the source-drain region and having a second thickness thinner than the first thickness in the channel layer region;
Etching the source-drain metal layer, the impurity semiconductor layer, and the semiconductor layer using the photoresist as a mask;
Exposing the photoresist metal layer to a region of the channel layer by thinning the photoresist by the second thickness;
Etching the source-drain metal layer using the thinned photoresist as a mask to form a source electrode and a drain electrode, and exposing the impurity semiconductor layer; And
Removing the exposed impurity semiconductor layer while etching and removing the second gate insulating layer using the thinned photoresist as a mask, and back-etching the semiconductor layer to complete the thin film transistor. A method of manufacturing a thin film transistor substrate for a flat panel display;
In the step of completing the thin film transistor, the ratio of the etch rate of the second gate insulating layer and the etch rate of the impurity semiconductor layer and the semiconductor layer is 2: 1 to 4: 1. Substrate manufacturing method.
In the step of completing the thin film transistor, the ratio of the amount of etching gas for etching the second gate insulating film and the amount of the etching gas for etching the impurity semiconductor layer and the semiconductor layer is 2: 1 to 4: 1. A thin film transistor substrate manufacturing method for a flat panel display device.
The etching gas for etching the second gate insulating layer includes sulfur fluoride (SF6) gas,
And the etching gas for etching the impurity semiconductor layer and the semiconductor layer comprises a chlorine (Cl 2) gas.
Applying a passivation layer covering the thin film transistor and forming a drain contact hole exposing the drain electrode; And
And forming a pixel electrode contacting the drain electrode through the drain contact hole with the transparent conductive material on the passivation layer.
In the forming of the pixel electrode, an auxiliary capacitance extending from the pixel electrode and overlapping a portion of the gate element with the first gate insulating layer and the passivation layer therebetween is further formed. Transistor substrate manufacturing method.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10185042B2 (en) | 2015-12-31 | 2019-01-22 | Lg Display Co., Ltd. | Array substrate of X-ray detector, method for manufacturing array substrate of X-ray detector, digital X-ray detector including the same, and method for manufacturing X-ray detector |
| KR20200051887A (en) * | 2018-11-05 | 2020-05-14 | 삼성디스플레이 주식회사 | Liquid crystal display and the method therrof |
| CN112993041A (en) * | 2021-02-03 | 2021-06-18 | 重庆先进光电显示技术研究院 | Liquid crystal display panel, thin film transistor and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030060282A (en) * | 2002-01-08 | 2003-07-16 | 삼성전자주식회사 | A thin film transistor substrate and a method of manufacturing the same |
| KR20100005454A (en) * | 2008-07-07 | 2010-01-15 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method of the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030060282A (en) * | 2002-01-08 | 2003-07-16 | 삼성전자주식회사 | A thin film transistor substrate and a method of manufacturing the same |
| KR20100005454A (en) * | 2008-07-07 | 2010-01-15 | 삼성전자주식회사 | Thin film transistor array panel and manufacturing method of the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10185042B2 (en) | 2015-12-31 | 2019-01-22 | Lg Display Co., Ltd. | Array substrate of X-ray detector, method for manufacturing array substrate of X-ray detector, digital X-ray detector including the same, and method for manufacturing X-ray detector |
| KR20200051887A (en) * | 2018-11-05 | 2020-05-14 | 삼성디스플레이 주식회사 | Liquid crystal display and the method therrof |
| CN112993041A (en) * | 2021-02-03 | 2021-06-18 | 重庆先进光电显示技术研究院 | Liquid crystal display panel, thin film transistor and manufacturing method thereof |
| CN112993041B (en) * | 2021-02-03 | 2023-03-24 | 重庆先进光电显示技术研究院 | Liquid crystal display panel, thin film transistor and manufacturing method thereof |
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