JP2010182723A - Production process of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for forming size-reduced and high-density vias, with high precision and interconnections of a semiconductor device. <P>SOLUTION: Semiconductor chips 2a and 2b are allocated on one surface side of a support substrate 1, which is ground from the other surface side, and the ground support substrate 1 is used as an insulating film, where via hole 6 is formed by using the photolithographic technique. After that, a conductive material is embedded in the via hole 6 to form a via, and further on its upper layer, wiring connected to the via is formed. The flat surface of the support substrate 1 is used as a surface when exposure is carried out, thus forming the via hole 6 highly accurately, and enabling vias to be formed there. Furthermore, it will become possible to highly precisely form wiring on the upper layer of the support substrate 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a semiconductor chip.

  In various electrical devices such as computers, a multi-chip module (MCM) that implements a certain function by mounting a plurality of semiconductor chips on a single substrate is widely used. In recent years, semiconductor chips having various functions and sizes have been mounted on the MCM.

  Regarding the formation of MCM, a technique of polishing an insulating film covering a plurality of semiconductor chips on a substrate, and forming a conductive portion connected to each semiconductor chip using a photolithography technique on the polished insulating film, etc. Is known (for example, see Patent Document 1). In addition, after sealing a plurality of semiconductor chips bonded to the adhesive sheet on the substrate, the substrate and the adhesive sheet are removed, thereby aligning the surface positions of the plurality of semiconductor chips, and providing a conductive portion on these semiconductor chips. The technique etc. which connect are also known (for example, refer patent documents 2-4). Also known is an MCM forming technique for connecting a substrate having a conductive portion and a semiconductor chip using alignment marks formed on each substrate (for example, see Patent Document 5).

JP 2001-274315 A JP 2002-120132 A JP 2002-110714 A JP 2005-294444 A JP 2004-079693 A

  In addition to MCM, in the formation of a semiconductor device including a semiconductor chip, in order to cope with the miniaturization and high density of the semiconductor chip, a conductive portion connected to the semiconductor chip or a plurality of semiconductor chips are connected. It is important to form the conductive portion with high accuracy. However, with the diversification of semiconductor chips used such as the planar size and thickness, there are cases where it is difficult to form such a conductive portion with high accuracy.

  According to an aspect of the present invention, a step of disposing a semiconductor chip above the first main surface of the first substrate via an adhesive member, and a second substrate covering the semiconductor chip above the first main surface And a step of forming a conductive portion that penetrates the first substrate and the adhesive member and is electrically connected to the semiconductor chip.

  According to another aspect of the present invention, a step of disposing a second substrate having a through hole in which a semiconductor chip is accommodated above the first main surface of the first substrate; and the first substrate in the through hole. A step of disposing the semiconductor chip via an adhesive member above one main surface; a step of forming a conductive portion that penetrates the first substrate and the adhesive member and is electrically connected to the semiconductor chip; A method for manufacturing a semiconductor device is provided.

  According to the disclosed method, a high-performance and highly reliable semiconductor device including a conductive portion formed with high accuracy can be formed.

It is explanatory drawing of an example of a support substrate, Comprising: (A) is a plane schematic diagram, (B) is a X1-X1 cross-sectional schematic diagram of (A). It is explanatory drawing of an example of a semiconductor chip arrangement | positioning process, Comprising: (A) is a plane schematic diagram of the chip | tip to arrange | position, (B) is a plane schematic diagram in the state which has arrange | positioned a chip | tip, (C) is X2-X2 of (B). It is a cross-sectional schematic diagram. It is a cross-sectional schematic diagram of an example of the semiconductor chip coating process according to the first embodiment, where (A) shows a state before coating, and (B) shows a state after coating. It is a cross-sectional schematic diagram of an example of the support substrate grinding process which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of an example of the via-hole formation process which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of an example of the 1st electroconductive material formation process which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of an example of the 1st grinding | polishing process which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of an example of the insulating layer formation process which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of an example of the wiring groove | channel formation process which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of an example of the 2nd conductive material formation process which concerns on 1st Embodiment. It is a cross-sectional schematic diagram of an example of the 2nd grinding | polishing process which concerns on 1st Embodiment. It is a principal part plane schematic diagram of an example of the state which formed wiring. It is a cross-sectional schematic diagram of another example of the semiconductor chip covering step according to the first embodiment. It is a cross-sectional schematic diagram of the semiconductor chip coating step according to the second embodiment, (A) is a diagram showing a state before coating, (B) is a diagram showing a state after coating. It is a cross-sectional schematic diagram of an example of the support substrate grinding process which concerns on 2nd Embodiment. It is explanatory drawing of an example of the rigid board | substrate which concerns on 3rd Embodiment, (A) is a plane schematic diagram, (B) is a Y1-Y1 cross-sectional schematic diagram of (A). It is a cross-sectional schematic diagram of an example of the rigid board | substrate formation process which concerns on 3rd Embodiment. It is a cross-sectional schematic diagram of an example of a semiconductor chip coating process according to the third embodiment, where (A) is a diagram showing a state before coating, and (B) is a diagram showing a state after coating. It is a cross-sectional schematic diagram of an example of the support substrate grinding process which concerns on 3rd Embodiment. It is a cross-sectional schematic diagram of an example of the via-hole formation process which concerns on 3rd Embodiment. It is a cross-sectional schematic diagram of an example of the via formation process according to the third embodiment. It is a cross-sectional schematic diagram of an example of the wiring groove | channel formation process which concerns on 3rd Embodiment. It is a cross-sectional schematic diagram of an example of the wiring formation process which concerns on 3rd Embodiment. It is a plane schematic diagram (the 1) of another example of the rigid board concerning a 3rd embodiment. It is a plane schematic diagram (the 2) of another example of the rigid board concerning a 3rd embodiment. It is a plane schematic diagram (the 3) of another example of the rigid board concerning a 3rd embodiment. It is explanatory drawing of an example of the rigid substrate grinding method, Comprising: (A) is a perspective schematic diagram of a grinding member, (B) is a principal part cross-sectional schematic diagram of the grinding process using a grinding member. It is explanatory drawing of an example of the rigid board | substrate which concerns on 4th Embodiment, (A) is a plane schematic diagram, (B) is a Z1-Z1 cross-sectional schematic diagram of (A). It is a cross-sectional schematic diagram of an example of the rigid board | substrate arrangement | positioning process which concerns on 4th Embodiment, (A) is a figure which shows the state before rigid board | substrate arrangement | positioning, (B) is a figure which shows the state after rigid board | substrate arrangement | positioning. is there. It is a cross-sectional schematic diagram of an example of the semiconductor chip arrangement | positioning process concerning 4th Embodiment. It is a cross-sectional schematic diagram of an example of the semiconductor chip coating process which concerns on 4th Embodiment. It is a cross-sectional schematic diagram of an example of the support substrate grinding process which concerns on 4th Embodiment. It is a cross-sectional schematic diagram of an example of the via formation process which concerns on 4th Embodiment. It is a cross-sectional schematic diagram of an example of the wiring formation process which concerns on 4th Embodiment. It is a plane schematic diagram of another example of the rigid board | substrate which concerns on 4th Embodiment.

Hereinafter, an example of forming the MCM will be described in detail with reference to the drawings.
First, the first embodiment will be described.
1A and 1B are explanatory views of an example of a support substrate, in which FIG. 1A is a schematic plan view, and FIG. 1B is a schematic cross-sectional view taken along line X1-X1 in FIG.

  FIG. 1 illustrates a support substrate 1 for arranging a plurality of semiconductor chips used for the MCM to be formed. As the support substrate 1, for example, a glass substrate can be used, and preferably, a transparent glass substrate with few metal impurity components such as alkali metal is used. For example, a glass substrate (for example, a thickness of 400 μm) such as quartz glass or crystallized glass is used as the support substrate 1.

  In the support substrate 1 illustrated in FIG. 1, alignment marks 1a are formed corresponding to respective positions where a plurality of semiconductor chips are arranged. The alignment mark 1a is formed by forming a recess on one surface of the support substrate 1 by using, for example, a photolithography technique and an etching technique (dry etching or wet etching). The formed recess can be used as the alignment mark 1a in that state, and the formed recess is filled with a material different from the main component of the support substrate 1, such as polysilicon or titanium (Ti), and the alignment mark is filled therewith. It can also be used as 1a. FIG. 1 illustrates a state in which the concave portion is filled with such a material.

A plurality of semiconductor chips used for the MCM to be formed are arranged on the support substrate 1 on which the alignment mark 1a is formed.
2A and 2B are explanatory views of an example of a semiconductor chip placement step, where FIG. 2A is a schematic plan view of a chip to be placed, FIG. 2B is a schematic plan view of a state in which a chip is placed, and FIG. It is X2-X2 cross-sectional schematic diagram.

  After the support substrate 1 illustrated in FIG. 1 is prepared, a plurality of two types of semiconductor chips 2a and 2b are provided on the support substrate 1 as illustrated in FIGS. 2A to 2C. Deploy.

  Each of the semiconductor chips 2a and 2b is an IC (Integrated Circuit) chip such as an LSI (Large Scale Integration), and as illustrated in FIG. 2A, a plurality of electrodes 2c for external connection are provided on one surface. I have. The electrode 2c is formed using a metal material such as tungsten (W), copper (Cu), or aluminum (Al), although it depends on the type of the semiconductor chips 2a and 2b. An insulating film (protective film) such as silicon oxide (SiO) or silicon nitride (SiN) is formed on the surface of the semiconductor chips 2a and 2b so as to expose at least a part of the electrode 2c. .

  The semiconductor chips 2a and 2b arranged on the support substrate 1 constitute one MCM by one set of semiconductor chips 2a and 2b as illustrated by a dotted line in FIG. That is, on the support substrate 1, a set of semiconductor chips 2 a and 2 b constituting one MCM is arranged aligned with a certain rule.

  The semiconductor chips 2a and 2b used here have different thicknesses as illustrated in FIG. 2C. As described above, the semiconductor chips 2a and 2b having different thicknesses are respectively arranged so that the surface on which the electrode 2c is formed is opposed to the surface on which the alignment mark 1a is formed on the support substrate 1, and the adhesive member 3 is positioned at a position corresponding to the alignment mark 1a. Adhere using.

  The adhesive member 3 can be formed on the entire surface of the support substrate 1 where the alignment mark 1a is formed, or can be formed only between the electrode 2c formation surface of the semiconductor chips 2a and 2b and the support substrate 1. FIG. 2C illustrates a case where the adhesive member 3 is formed on the entire surface of the support substrate 1 where the alignment mark 1a is formed and the semiconductor chips 2a and 2b are bonded. In addition, illustration of the adhesive member 3 is abbreviate | omitted in FIG.2 (B).

  As the adhesive member 3, an adhesive made of a resin containing epoxy resin, phenol resin, benzocyclobutene (BCB), or the like can be used. Depending on the composition of the adhesive, the epoxy resin is treated at 180 ° C. for about 1 hour, the phenol resin is treated at 150 ° C. for about 1 hour, and the BCB is treated at 250 ° C. for 1 hour. Each can be cured by a treatment for about an hour. Moreover, as the adhesive member 3, in addition to such an adhesive, a pressure-sensitive adhesive sheet containing polyvinyl alcohol (PVA) or the like can be used.

  When an adhesive is used for the adhesive member 3, the adhesive is applied to the alignment mark 1a formation surface side of the support substrate 1 or the electrode 2c formation surface side of the semiconductor chips 2a and 2b to support the semiconductor chips 2a and 2b. Adhere to the substrate 1. When an adhesive sheet is used for the adhesive member 3, an adhesive sheet is attached to the side of the support substrate 1 where the alignment mark 1a is formed or the surface of the semiconductor chip 2a, 2b where the electrode 2c is formed, thereby supporting the semiconductor chips 2a, 2b. Adhere to the substrate 1.

  Further, a material (SOG film material) for forming an inorganic or organic so-called SOG (Spin On Glass) film can be used as the adhesive member 3. In that case, for example, a coating film of a predetermined SOG film material is formed by spin coating or the like on the alignment mark 1a forming surface side of the support substrate 1, and the semiconductor chips 2a and 2b are formed on the support substrate 1 through the coating film. Adhere to.

  The arrangement of the semiconductor chips 2a and 2b using the alignment mark 1a is such that a predetermined adhesive member 3 is provided on the alignment mark 1a formation surface side of the support substrate 1 or on the electrode 2c formation surface side of the semiconductor chips 2a and 2b. Later, this can be done automatically using a device such as a chip bonder. When the semiconductor chips 2a and 2b are arranged using a relatively high precision device, the positional deviation of the semiconductor chips 2a and 2b with respect to the alignment mark 1a can be suppressed to a target value of ± 1 μm or less. is there.

  When a glass substrate is used as the support substrate 1 and the concave portion is filled with a material such as polysilicon or Ti to form the alignment mark 1a, such a material has a high reflectance with respect to the glass substrate. The alignment mark 1a can be easily detected optically. Therefore, when such an alignment mark 1a is used, the alignment mark 1a is easily detected when the semiconductor chips 2a and 2b are arranged, and the semiconductor chips 2a and 2b are accurately placed at positions corresponding to the alignment marks 1a. It becomes possible to arrange.

Note that the thickness of the adhesive member 3 between the support substrate 1 and the semiconductor chips 2a and 2b after the semiconductor chips 2a and 2b are arranged is approximately 15 μm or less.
After the semiconductor chips 2a and 2b having different thicknesses are disposed on the support substrate 1 as described above, the semiconductor chips 2a and 2b disposed on the support substrate 1 are covered with a covering member such as a resin.

FIG. 3 is a schematic cross-sectional view of an example of the semiconductor chip coating process according to the first embodiment, where (A) shows a state before coating, and (B) shows a state after coating. .
Here, a thermosetting resin substrate 4 containing an epoxy resin or the like is used as a covering member for covering the semiconductor chips 2a and 2b. For example, an epoxy resin-based resin that has flexibility with respect to the semiconductor chips 2a and 2b and the support substrate 1 and can be cured by heating at a predetermined heating condition, for example, 180 ° C. for 1 hour before thermosetting. A substrate 4 is used.

  When covering the semiconductor chips 2a and 2b using such a resin substrate 4, first, the resin substrate 4 (for example, a thickness of 625 μm) is prepared on the side of the support substrate 1 on which the semiconductor chips 2a and 2b are arranged. To do. Next, the support substrate 1 on which the semiconductor chips 2 a and 2 b are arranged is pressed against the resin substrate 4 to embed the semiconductor chips 2 a and 2 b in the resin substrate 4. Then, the resin substrate 4 is cured by raising the temperature to a predetermined temperature and holding the temperature for a predetermined time. Thereby, a base material (pseudo wafer) 10 in which the semiconductor chips 2a and 2b arranged on the support substrate 1 are covered with the resin substrate 4 as illustrated in FIG. 3B is obtained.

  After the resin substrate 4 is cured, the resin component flows to the side of the support substrate 1 and cures, or the exposed surface of the resin substrate 4 on the side opposite to the support substrate 1 side is uneven or inclined. Or the shape of the pseudo wafer 10 may be disturbed. In such a case, the cured resin substrate 4 is formed by grinding or the like, and the portion that flows to the side of the support substrate 1 is ground, or the exposed surface of the resin substrate 4 is flattened (leveled). In this manner, the shape of the pseudo wafer 10 may be adjusted.

Next, the support substrate 1 is thinned.
FIG. 4 is a schematic cross-sectional view of an example of a support substrate grinding process according to the first embodiment.
After the semiconductor chips 2a and 2b arranged on the support substrate 1 are coated with the resin substrate 4, the support substrate 1 of the pseudo wafer 10 is ground. The support substrate 1 is ground, for example, in a state where the pseudo wafer 10 is fixed with the resin substrate 4 side facing down on a table (chuck table or the like) of a grinding apparatus that performs the grinding.

  When grinding the support substrate 1, first, the difference between the thickness d1 of the pseudo wafer 10 immediately before grinding and the thickness d2 of the support substrate 1 is obtained, and the thicknesses of the adhesive member 3 and the resin substrate 4 on the pseudo wafer 10 are obtained. d3 (= d1-d2) is obtained (FIG. 3). This is because the thickness of the support substrate 1 does not substantially vary from the initial thickness, while the thickness of the adhesive member 3 and the resin substrate 4 varies from the initial thickness due to previous curing or subsequent grinding or the like. This is because there is a possibility. Then, the thickness d4 of the support substrate 1 to be finally obtained by grinding is added to the thickness d3 of the adhesive member 3 and the resin substrate 4 obtained in this way, and the pseudo wafer 10 has its thickness from the table surface of the grinding apparatus. Grinding is performed until d3 + d4. Thereby, the support substrate 1 thinned from the initial thickness d2 to the thickness d4 is obtained. Note that the thickness d4 of the support substrate 1 after grinding is desirably 5 μm or less, and this will be described later.

  The grinding of the support substrate 1 can control the grinding surface from the table surface of the grinding device to a target value of ± 1 μm or less. Further, the thickness variation in the grinding surface can be controlled to 1 μm or less by TTV (Total Thickness Variation).

  If grinding marks are generated on the ground surface after grinding of the support substrate 1, the ground surface is further removed by, for example, about 0.5 μm in thickness by CMP (Chemical Mechanical Polishing), etching, or the like. Then, grinding marks may be removed.

  After the support substrate 1 is thus ground, a wiring structure for electrically connecting the semiconductor chips 2a and 2b is formed, for example, as illustrated in FIGS. Go.

First, an example of forming vias electrically connected to the electrodes 2c of the semiconductor chips 2a and 2b will be described.
5 is a schematic cross-sectional view of an example of a via hole forming process according to the first embodiment, FIG. 6 is a schematic cross-sectional view of an example of a first conductive material forming process according to the first embodiment, and FIG. It is a cross-sectional schematic diagram of an example of the 1st grinding | polishing process which concerns on this embodiment.

  After grinding of the support substrate 1, via holes 6 reaching the semiconductor chips 2a and 2b (their electrodes 2c) are formed in the support substrate 1, as illustrated in FIG. 5, using photolithography technology and etching technology.

In that case, first, a resist is applied on the support substrate 1, and a resist pattern having an opening at a position where the via hole 6 is formed is formed by exposure / development processing. Then, etching is performed using the resist pattern as a mask. In the etching, for example, when a glass substrate is used as the support substrate 1, any one gas of tetrafluoromethane (CF ₄ ), sulfur hexafluoride (SF ₆ ), and octafluorocyclobutane (C ₄ F ₈ ) is used. It can be performed by the used RIE (Reactive Ion Etching).

  When RIE is performed as described above, and an organic material such as epoxy resin, phenol resin, BCB, PVA, or organic SOG film material as described above is used for the adhesive member 3 under the support substrate 1. The RIE can be stopped at the position of the adhesive member 3. Therefore, even if there is a variation in the thickness of the support substrate 1 after grinding in one pseudo wafer 10 or between different pseudo wafers 10, the semiconductor chips 2a and 2b (electrodes 2c) are exposed at the time of this etching. I will not let you.

  After the RIE of the support substrate 1 is performed and the adhesive member 3 is exposed, the exposed adhesive member 3 is subsequently subjected to oxygen and nitrogen as an etching gas under a pressure of 100 mTorr to 300 mTorr and a power of 1 kW. Etch. Note that nitrogen in the etching gas plays a role of protecting the side wall of the via hole 6 to be formed. When side wall protection is not necessary, nitrogen may not be added to the etching gas. By such etching of the adhesive member 3, the via hole 6 that penetrates the support substrate 1 and the adhesive member 3 and reaches the semiconductor chips 2 a and 2 b (electrode 2 c) can be formed. In addition, the resist formed on the support substrate 1 can be removed when the adhesive member 3 is etched.

  Further, when the adhesive member 3 is etched, the etching of the electrodes 2c (W, Cu, Al, etc.) of the semiconductor chips 2a, 2b and the surrounding protective film (SiO, SiN, etc.) is suppressed even after the adhesive member 3 is removed. (Etching selectivity 50 or more). Accordingly, even if the thickness of the bonding member 3 varies within one pseudo wafer 10 or between different pseudo wafers 10, the electrodes 2c and the protective film of the semiconductor chips 2a and 2b are excessively etched. Can be suppressed.

  As described above, here, the semiconductor chips 2a and 2b are disposed on the alignment mark 1a forming surface side of the support substrate 1, and the support substrate 1 is not removed, but the insulating film (interlayer insulating film) for forming the via hole 6 is formed. ).

  Therefore, the grinding of the support substrate 1 illustrated in FIG. 4 is preferably performed in consideration of forming the via hole 6 by etching in the ground support substrate 1 as illustrated in FIG. Formation of the via hole 6 by etching is easier as the via hole 6 has a lower aspect ratio. From such a viewpoint, the support substrate 1 is preferably ground to a thickness of 5 μm or less, although it depends on the diameter of the via hole 6 to be formed.

  However, depending on the accuracy of the grinding apparatus used and the thickness variation of the adhesive member 3, the thickness of the support substrate 1 after grinding may vary, and depending on the materials of the support substrate 1 and the resin substrate 4, Further, the pseudo wafer 10 may be warped by heating. Here, the grinding is performed based on the table surface of the grinding device (the surface of the pseudo wafer 10 on the side of the resin substrate 4). Therefore, if the thickness of the finally obtained support substrate 1 is set too thin, the grinding may be performed depending on the case. There is a possibility that the adhesive member 3 and the resin substrate 4 will be partially exposed later. In consideration of such a possibility, it is preferable that the support substrate 1 is ground with its thickness set in a range of 3 μm to 5 μm.

  When the resist pattern for forming the via hole 6 is formed by exposure / development, even if there is a variation in the surface position within the ground surface of the support substrate 1, the variation is within the depth of focus. Then, a resist pattern can be formed thereon with high accuracy. Therefore, even when the semiconductor chips 2a and 2b having different thicknesses are used, the via hole 6 can be formed with high accuracy.

  Further, when the resist pattern for forming the via hole 6 is formed, by using the alignment mark 1a formed on the support substrate 1, the arrangement position of the semiconductor chips 2a and 2b and the formation position of the via hole 6 are determined with high accuracy. can do. The alignment mark 1a is formed on the side opposite to the resist pattern forming surface side of the support substrate 1 (on the semiconductor chip 2a, 2b arrangement surface side). When a transparent glass substrate as described above is used, The alignment mark 1a can be detected from the resist pattern forming surface side.

  As described above, when the alignment mark 1a is shared by the placement of the semiconductor chips 2a and 2b and the formation of the via hole 6, the placement of the semiconductor chips 2a and 2b and the formation of the via hole 6 can be performed at desired positions. Compared to the case where such an alignment mark 1a is not formed on the support substrate 1 or the case where no one corresponding to the alignment mark 1a is formed on either the support substrate 1 or the semiconductor chips 2a and 2b. The throughput of MCM formation can be greatly improved.

  If a grinding mark is generated on the ground surface of the support substrate 1, an exposure light reflection abnormality may occur due to the grinding mark when the via hole 6 is exposed. In order not to cause such an exposure light reflection abnormality, it is preferable to remove the grinding traces by performing CMP or etching after the previous support substrate 1 is ground. However, even if there is a grinding mark, if it is possible to suppress such a reflection abnormality of the exposure light (for example, an antireflection film is separately formed on the resist underlayer), the support substrate 1 is not necessarily ground. It is not necessary to remove the grinding marks.

  After the via hole 6 is formed, a conductive material 7a for filling the via hole 6 is formed as illustrated in FIG. In this case, for example, a Ti barrier layer and a Cu seed layer are first formed by sputtering, and a Cu plating layer is deposited by electroplating using the seed layer as an electrode. Fill the via hole 6 with. Alternatively, a Ti barrier layer is first formed using a sputtering method, and then a W layer is deposited using a CVD method, and the via hole 6 is filled with these layers.

  After the via hole 6 is filled with the conductive material 7a, as illustrated in FIG. 7, CMP is performed so that the support substrate 1 is exposed, and excess conductive material 7a on the support substrate 1 is removed. Thereby, the via 7 penetrating the support substrate 1 and the adhesive member 3 and electrically connected to the electrodes 2c of the semiconductor chips 2a and 2b is formed.

  In addition, when the grinding trace has arisen on the grinding surface of the support substrate 1, the conductive material 7a may remain in the grinding trace after CMP. In order not to generate such a residue of the conductive material 7a, it is preferable to remove the grinding trace by performing CMP or etching after the previous support substrate 1 is ground. However, when such a residue of the conductive material 7a is generated, if it is possible to selectively remove the residue, it is not necessary to remove the grinding trace after grinding the support substrate 1. I don't need it.

Subsequently, an example of forming a wiring for electrically connecting the semiconductor chips 2a and 2b will be described.
8 is a schematic cross-sectional view of an example of an insulating layer forming process according to the first embodiment, FIG. 9 is a schematic cross-sectional view of an example of a wiring trench forming process according to the first embodiment, and FIG. FIG. 11 is a schematic cross-sectional view of an example of a second polishing process according to the first embodiment, and FIG. 11 is a schematic cross-sectional view of an example of a second polishing process according to the first embodiment. FIG. 12 is a schematic plan view of an essential part of an example of a state in which wiring is formed.

  After the via 7 is formed as illustrated in FIGS. 5 to 7, an insulating film (interlayer insulating film) 21 such as SiO is formed on the support substrate 1 as illustrated in FIG. 8. Then, a resist pattern having an opening for wiring between the semiconductor chips 2 a and 2 b is formed on the insulating film 21. Next, the insulating film 21 is etched using the resist pattern as a mask to form a wiring groove 22 in the insulating film 21 as illustrated in FIG. Here, the wiring trench 22 is formed so as to penetrate the insulating film 21 in a region including the formation region of the via 7 connected to the pair of semiconductor chips 2a and 2b.

  After the formation of the wiring groove 22, as illustrated in FIG. 10, a conductive material 23a that fills the wiring groove 22 is formed. In that case, for example, first, a Ti barrier layer and a Cu seed layer are formed by using a sputtering method, and then a Cu plating layer is deposited by using an electroplating method. fill in. Thereafter, CMP is performed to obtain a state in which the electrodes 2c of the semiconductor chips 2a and 2b are electrically connected by the wiring 23 via the vias 7 as illustrated in FIGS.

  After the via 7 and the wiring 23 are formed, for example, dicing is performed at a position as shown by a chain line D in FIGS. 11 and 12 to separate each MCM including a pair of semiconductor chips 2a and 2b. .

  As described above, according to the first embodiment, the semiconductor chips 2a and 2b are arranged on one surface side of the support substrate 1, and the support substrate 1 is thinned with good flatness from the other surface side. It is used as an insulating film. Therefore, even when the semiconductor chips 2a and 2b having different thicknesses are used, the via 7 can be formed with high accuracy in the support substrate 1, and the support substrate 1 (insulating film) having good flatness can be formed. On the upper layer, the wiring 23 can be formed with high accuracy. As a result, it is possible to cope with miniaturization and high density of the via 7 and the wiring 23, and it is possible to form a high-performance and high-reliability MCM.

  In the above description, as illustrated in FIG. 3, a flat substrate is used as the resin substrate 4 used for covering the semiconductor chips 2a and 2b. However, the shape of the resin substrate 4 is not limited to this. It is not something.

FIG. 13 is a schematic cross-sectional view of another example of the semiconductor chip covering step according to the first embodiment.
As the resin substrate 4, it is possible to use a resin substrate having recesses 4a formed in regions corresponding to the semiconductor chips 2a and 2b, as illustrated in FIG. The recesses 4a may all be formed in the same size, or the recesses 4a corresponding to relatively large semiconductor chips 2a may be formed large and the recesses 4a corresponding to relatively small semiconductor chips 2b may be formed small. Good. In FIG. 13, the case where the recessed part 4a of all the same size is formed is illustrated. The recess 4a is not necessarily the same size as the semiconductor chips 2a and 2b.

  By forming such a recess 4a in the resin substrate 4, it becomes possible to suppress the resin flow around the semiconductor chips 2a and 2b when the semiconductor chips 2a and 2b are embedded in the resin substrate 4. Disturbance of the shape of the wafer 10 can be suppressed.

Even when such a resin substrate 4 is used, the MCM including the via 7 and the wiring 23 can be formed by performing the same processing as described in FIGS.
Next, a second embodiment will be described.

  Also in the second embodiment, as in the first embodiment, after the semiconductor chips 2a and 2b are arranged on the support substrate 1 using the adhesive member 3, the semiconductor chip 2a is used using the resin substrate 4. , 2b.

14A and 14B are schematic cross-sectional views of a semiconductor chip coating process according to the second embodiment, in which FIG. 14A shows a state before coating, and FIG. 14B shows a state after coating.
In the second embodiment, as illustrated in FIG. 14, a rigid substrate (rigid substrate) 30 (for example, a thickness of 725 μm) is provided on the surface of the resin substrate 4 opposite to the side on which the support substrate 1 is disposed. ) Are further arranged to form a pseudo wafer 10a. As such a rigid substrate 30, a silicon (Si) substrate, a glass substrate such as quartz glass or crystallized glass, or a ceramic substrate such as SiO, aluminum oxide (AlO), or aluminum nitride (AlN) can be used.

  As described in the first embodiment, after the semiconductor chips 2a and 2b on the support substrate 1 are coated with the resin substrate 4, the resin substrate 4 is cured, and the insulating film and the conductive material after the support substrate 1 is ground. Material formation takes place, during which the simulated wafer 10 is exposed to heat. If the support substrate 1 and the resin substrate 4 are made of materials whose coefficients of thermal expansion are greatly different, the pseudo wafer 10 may be warped during the heating as it is. There is sex. For example, when such a warp occurs when the resin substrate 4 is cured, it becomes difficult to perform grinding of the support substrate 1 performed thereafter to a desired thickness with high accuracy. Further, if such warpage occurs during heating after grinding of the support substrate 1, it may happen that the thin support substrate 1 is damaged or that subsequent processes cannot be performed or cannot be performed accurately because of warping.

  On the other hand, in the case of the pseudo wafer 10a in which the rigid substrate 30 is arranged on the resin substrate 4 as illustrated in FIG. 14B, the warp of the pseudo wafer 10a is not affected by the material of the support substrate 1 and the resin substrate 4. Occurrence can be effectively suppressed.

FIG. 15 is a schematic cross-sectional view of an example of a support substrate grinding process according to the second embodiment.
After the formation of the pseudo wafer 10a on which the rigid substrate 30 is arranged, the support substrate 1 is ground as in the first embodiment. Here, first, using the thickness d1 of the pseudo wafer 10a immediately before grinding, the thickness d5 of the rigid substrate 30, and the thickness d2 of the support substrate 1, the thickness d3 (= d1) of the adhesive member 3 and the resin substrate 4 is used. -D2-d5) is obtained (FIG. 14). Then, the thickness d4 of the support substrate 1 to be finally obtained by grinding is added to the sum of the thickness d3 of the adhesive member 3 and the resin substrate 4 and the thickness d5 of the rigid substrate 30, and the pseudo wafer 10a becomes the grinding device. Grinding is performed from the table surface to the thickness d3 + d4 + d5. Thereby, the support substrate 1 thinned from the initial thickness d2 to the thickness d4 is obtained. Thereafter, CMP or etching may be performed on the ground surface to remove grinding marks.

  Then, after grinding of the support substrate 1 in this way, vias 7 and wirings 23 that electrically connect the semiconductor chips 2a and 2b are formed in the same manner as described above with reference to FIGS. You should do it.

  Also according to the second embodiment, it is possible to form the via 7 with high accuracy in the support substrate 1 by using the support substrate 1 thinned with good flatness as an insulating film and suppressing the occurrence of warpage. Further, the wiring 23 can be formed with high accuracy on the upper layer of the support substrate 1 on which the vias 7 are formed. As a result, it is possible to cope with miniaturization and high density of the via 7 and the wiring 23.

Next, a third embodiment will be described.
The third embodiment is different from the first embodiment in that a rigid substrate is disposed instead of the resin substrate 4 on the support substrate 1 on which the semiconductor chips 2a and 2b are disposed.

16A and 16B are explanatory views of an example of a rigid substrate according to the third embodiment, in which FIG. 16A is a schematic plan view and FIG. 16B is a schematic cross-sectional view along Y1-Y1 in FIG.
In the rigid substrate 40 illustrated in FIG. 16, a recess 40a that can accommodate the semiconductor chips 2a and 2b is formed in a region corresponding to the semiconductor chips 2a and 2b disposed on the support substrate 1, and further, the recess 40a. A groove 40b communicated with is formed. As the rigid substrate 40, in addition to a silicon (Si) substrate, a glass substrate such as quartz glass or crystallized glass, a ceramic substrate such as SiO, AlO, or AlN can be used.

FIG. 17 is a schematic cross-sectional view of an example of a rigid substrate forming process according to the third embodiment.
When the rigid substrate 40 as illustrated in FIG. 16 is formed, first, a region in which the recess 40a and the groove 40b are formed on the rigid substrate 41 (for example, a thickness of 725 μm) where the recess 40a and the groove 40b are not formed. A mask pattern 50 having openings 50a and 50b is formed. Then, etching (dry etching or wet etching) is performed using this as a mask to form the recesses 40a and the grooves 40b.

For example, when the rigid substrate 41 is an Si substrate, a resist pattern having an opening in a predetermined region is formed, and RIE using SF ₆ is performed using the resist pattern as a mask (for example, Si etching rate 30 μm / min). Thereby, the concave portion 40a and the groove 40b illustrated in FIG. 16 are formed in the rigid substrate 41. In addition, in order to protect the side wall of the recess 40a and the groove 40b to be formed, the supply of SF ₆ may be temporarily stopped during the RIE to supply C ₄ F ₈ .

When the rigid substrate 41 is a glass substrate, first, a tungsten silicide (WSi) hard mask having an opening in a predetermined region is formed (for example, WSi: glass substrate (SiO ₂ ) = 1: 16). Then, both trifluoromethane (CHF ₃ ) and carbon monoxide (CO) are supplied at 75 sccm, and RIE is performed with an ICP (Inductive Coupling Plasma) condition of 1000 W and a bias condition of 600 W (for example, an SiO ₂ etching rate of 430 nm / sec). min). Thereby, the concave portion 40a and the groove 40b illustrated in FIG. 16 are formed in the rigid substrate 41.

On the other hand, when the recess 40a and the groove 40b are formed by wet etching, for example, first, an SiN film is formed on the entire surface (including the front surface and the back surface) of the rigid substrate 41 using a CVD method or the like, and the SiN film A hard mask is formed by opening the predetermined region. Etching is performed using a solution containing nitric acid (HNO ₃ ), hydrogen fluoride (HF), and acetic acid (CH ₃ COOH) as an etchant. Thereby, the concave portion 40a and the groove 40b illustrated in FIG. 16 are formed in the rigid substrate 41.

18A and 18B are schematic cross-sectional views of an example of a semiconductor chip coating process according to the third embodiment, where FIG. 18A shows a state before coating, and FIG. 18B shows a state after coating. .
When the rigid substrate 40 is arranged on the support substrate 1 on which the semiconductor chips 2a and 2b are arranged, first, a resin (adhesive) 42 such as an epoxy resin or BCB is provided in the recess 40a and the groove 40b of the rigid substrate 40, for example. Put a predetermined amount. Further, an adhesive 43 such as an epoxy resin or BCB is applied to the formation surface side of the recess 40a and the groove 40b of the rigid substrate 40.

  Then, the support substrate 1 to which the semiconductor chips 2a and 2b are bonded using the bonding member 3 at the position corresponding to the alignment mark 1a is bonded to the rigid substrate 40 provided with the resin 42 and the adhesive 43, and both are bonded. A pseudo wafer 10b is obtained. At this time, the semiconductor chips 2a and 2b are accommodated in the recess 40a, and the accommodated semiconductor chips 2a and 2b are covered with the resin 42.

  At this time, for example, the resin 42 and the adhesive 43 can be bonded under such conditions that the support substrate 1 and the rigid substrate 40 do not peel off in the subsequent grinding step, and the gas does not generate much gas. It is preferable to make it harden | cure using.

  In addition, it is preferable to adjust the amount of the resin 42 to be put in the recess 40a in advance so that a good covering state of the semiconductor chips 2a and 2b with the resin 42 is obtained. Here, the resin 42 such as an epoxy resin is placed in the recess 40a and the groove 40b, but an SOG film material may be placed.

FIG. 19 is a schematic cross-sectional view of an example of a support substrate grinding process according to the third embodiment.
After the support substrate 1 and the rigid substrate 40 are bonded, the support substrate 1 is ground. In that case, the thickness of the support substrate 1 and the thickness of the rigid substrate 40 are grasped in advance, the thickness of the pseudo wafer 10b is measured, and the thickness of the adhesive 43 is obtained. In addition, the thickness of the adhesive 43 is approximately 10 μm to 100 μm. Then, the thickness of the support substrate 1 to be finally obtained by grinding is added to the sum of the thicknesses of the rigid substrate 40 and the adhesive 43, and grinding is performed until the pseudo wafer 10b reaches the thickness from the table surface of the grinding apparatus. I do.

At this time, for example, when a Si substrate is used as the rigid substrate 40, the thickness can be measured by a capacitance measuring device.
In addition, the grinding of this support substrate 1 can control the grinding surface to ± 1 micrometer or less of a target value from the table surface of a grinding apparatus, and can control the dispersion | variation in a grinding surface to 1 micrometer or less.

  The thickness of the adhesive 43 after bonding the support substrate 1 and the rigid substrate 40 is relatively thick, approximately 10 μm or more in order to ensure a predetermined adhesive strength, so depending on the variation in the thickness of the adhesive 43 The degree of grinding of the support substrate 1 may be limited. That is, depending on the thickness variation of the adhesive 43, the amount of grinding of the support substrate 1 is prevented so that the adhesive 43 and the like are not partially exposed when grinding is performed with reference to the table surface of the grinding device. It may be necessary to adjust.

Note that after grinding, CMP or etching may be performed on the ground surface to remove grinding traces.
FIG. 20 is a schematic cross-sectional view of an example of a via hole forming process according to the third embodiment.

  After the support substrate 1 is ground, a via hole 6 reaching the electrode 2c of the semiconductor chips 2a and 2b is formed, and here, a via hole 6a reaching the groove 40b is formed. After the formation of the via holes 6 and 6a, annealing for strengthening the adhesive force between the resin 42 and the adhesive 43 is performed. In this case, the gas generated from the resin 42 and the adhesive 43 by annealing is exhausted to the outside through the groove 40b and the via holes 6 and 6a.

  If the groove 40b and the via hole 6a are not formed, the internal pressure of the pseudo wafer 10b may be increased because there is little or no escape path for the gas generated from the resin 42 and the adhesive 43 by annealing. is there. As a result, the support substrate 1 and the rigid substrate 40 may be peeled off or the support substrate 1 may be damaged. By forming the groove 40 b in the rigid substrate 40 and forming the exhaust via hole 6 a in addition to the via hole 6 in the support substrate 1, the occurrence of such peeling and breakage can be suppressed.

Thereafter, the via 7 and the wiring 23 are formed in the same manner as in the first embodiment.
FIG. 21 is a schematic cross-sectional view of an example of a via forming process according to the third embodiment. FIG. 22 is a schematic cross-sectional view of an example of a wiring groove forming process according to the third embodiment, and FIG. 23 is a schematic cross-sectional view of an example of a wiring forming process according to the third embodiment.

  After the formation of the via holes 6 and 6a, as illustrated in FIG. 21, a conductive material is formed on the entire surface by using a sputtering method, a CVD method, an electroplating method or the like to fill the via holes 6 and 6a. The excess conductive material on the support substrate 1 is removed by performing CMP so as to be exposed. As a result, vias 7 and 7 b are formed in the support substrate 1.

  Next, as illustrated in FIG. 22, the insulating film 21 is formed on the support substrate 1 on which the vias 7 and 7 b are formed, and the wiring groove 22 is formed there. Then, after a conductive material is formed on the entire surface and the wiring trench 22 is filled, CMP is performed so that the insulating film 21 is exposed, and excess conductive material on the insulating film 21 is removed. As a result, as illustrated in FIG. 23, wirings 23 are formed that electrically connect the electrodes 2 c of the semiconductor chips 2 a and 2 b via the vias 7.

  Also according to the third embodiment, the support substrate 1 thinned with good flatness can be used as an insulating film, and the via 7 can be formed with high precision thereover, and the wiring 23 can be formed with high precision thereover. can do. As a result, it is possible to cope with miniaturization and high density of the via 7 and the wiring 23.

  In the third embodiment, since the rigid substrate 40 is bonded to the support substrate 1 on which the semiconductor chips 2a and 2b are arranged, the insulating film after the resin 42 and the adhesive 43 are cured or after the support substrate 1 is ground. Even if heating is performed during the formation of the conductive material, the occurrence of such warpage can be suppressed. For example, the warp that occurs when the resin substrate 4 is cured prevents the support substrate 1 from being ground to a desired thickness with high accuracy. Further, the warp generated during heating after grinding of the support substrate 1 can affect the thin support substrate 1 and subsequent processes. In the third embodiment, by using the rigid substrate 40, it is possible to effectively suppress the warpage of the support substrate 1 and the rigid substrate 40 that may cause such a cause.

  In the third embodiment, the grooves 40 b are formed in the rigid substrate 40 and the via holes 6 and 6 a are formed in the support substrate 1, thereby effectively exhausting the gas generated from the resin 42 and the adhesive 43. To do. As a result, the MCM can be formed while suppressing the peeling between the support substrate 1 and the rigid substrate 40, the breakage of the support substrate 1, and the like.

The rigid substrate 40 may be configured as illustrated in FIGS. 24 to 26 below in addition to the configuration illustrated in FIG.
24 to 26 are schematic plan views of other examples of the rigid substrate according to the third embodiment.

  The rigid substrate 44 illustrated in FIG. 24 has a configuration in which a plurality of recesses 44a that are linearly rectangular and extend linearly and can accommodate one or more pairs of semiconductor chips 2a and 2b are formed in parallel. .

  When using such a rigid substrate 44, first, the resin 42 is put into the recess 44a, the adhesive 43 is applied to the surface, and the rigid substrate 44 is attached to the support substrate 1 on which the semiconductor chips 2a and 2b are arranged. Paste. At this time, one or a plurality of sets of semiconductor chips 2a and 2b are accommodated in each recess 44a. Then, the via hole 6 reaching the semiconductor chips 2a and 2b (electrode 2c) may be formed, and the via hole 6a for exhausting the gas generated from the resin 42 and the like may be formed.

  Such a recess 44a can be formed by etching (dry etching or wet etching) in the same manner as the recess 40a and the groove 40b of the rigid substrate 40.

  25, in the same manner as the rigid substrate 44 illustrated in FIG. 24, a plurality of linear recesses 45a that can accommodate one or a plurality of sets of semiconductor chips 2a and 2b are formed in parallel. It has the structure which was made. Further, the rigid substrate 45 has a configuration in which both end portions of the concave portion 45a are curved, which is different from the rigid substrate 44 illustrated in FIG.

  Such a recess 45a of the rigid substrate 45 can be formed by etching (dry etching or wet etching), and can also be formed by using a grinding member as illustrated in FIG.

27A and 27B are explanatory views of an example of a rigid substrate grinding method, in which FIG. 27A is a schematic perspective view of a grinding member, and FIG. 27B is a schematic cross-sectional view of an essential part of a grinding process using the grinding member.
FIG. 27A illustrates a grinding member 60 in which a grinding blade 62 such as diamond is attached to the tip of a cylindrical body 61. The grinding member 60 can circulate liquid such as water toward the grinding blade 62 in the hollow portion of the cylindrical body 61. The cylindrical body 61 can be of a size corresponding to the size of the recess 45a to be formed. For example, a cylindrical body 61 having an outer diameter of 20 mm and an inner diameter of 10 mm is used.

  When grinding is performed, the grinding member 60 is disposed at a position where the recess 45a is formed, and the grinding member 60 is moved linearly while circulating water or the like, so that the recess 45a of the rigid substrate 45 is moved. Form.

  Also with the rigid substrate 45 formed in this manner, as with the rigid substrate 44 illustrated in FIG. 24, the resin 42 and the like existing between the support substrate 1 on which the semiconductor chips 2a and 2b are arranged and the rigid substrate 45 are used. It is possible to exhaust the generated gas effectively.

  In addition, the rigid substrate 46 illustrated in FIG. 26 has a configuration in which a single flat circular recess 46a that can accommodate all the semiconductor chips 2a and 2b disposed on the support substrate 1 is formed. .

  Such a recess 46a of the rigid substrate 46 can be formed by etching (dry etching or wet etching), or can be formed by using a grinding member 60 as illustrated in FIG. In particular, in the case of the rigid substrate 46 having such a relatively large-area recess 46a, it is preferable to form the recess 46a using a grinding member 60 of an appropriate size from the viewpoint of throughput.

  The rigid substrate 46 illustrated in FIG. 26 can also effectively exhaust the gas generated from the resin 42 and the like existing between the support substrate 1 on which the semiconductor chips 2a and 2b are arranged and the rigid substrate 45. Is possible.

Next, a fourth embodiment will be described.
The fourth embodiment is different from the third embodiment in that a rigid substrate having a through hole capable of accommodating the semiconductor chips 2a and 2b is disposed on the support substrate 1.

FIG. 28 is an explanatory diagram of an example of a rigid substrate according to the fourth embodiment. FIG. 28A is a schematic plan view, and FIG. 28B is a schematic cross-sectional view taken along Z1-Z1 in FIG.
The rigid substrate 47 illustrated in FIG. 28 has a plurality of planar rectangular through holes 47a that can accommodate the semiconductor chips 2a and 2b. As the rigid substrate 47, in addition to the Si substrate, a glass substrate such as quartz glass or crystallized glass, a ceramic substrate such as SiO, AlO, or AlN can be used in addition to the Si substrate.

  Further, the rigid substrate 47 can be formed by using a method similar to the method used for forming the rigid substrate 40. That is, as illustrated in FIG. 17, first, a mask pattern in which a region for forming the through hole 47 a is opened is formed on a rigid substrate in which the through hole 47 a is not formed. Then, etching (dry etching or wet etching) may be performed using this as a mask to form the through hole 47a.

FIG. 29 is a schematic cross-sectional view of an example of a rigid substrate placement process according to the fourth embodiment, where (A) shows a state before placement of the rigid substrate, and (B) shows a state after placement of the rigid substrate. FIG.
After preparing the rigid substrate 47 in which the through hole 47a is formed, the rigid substrate 47 is placed on the support substrate 1 with the alignment mark 1a in which the semiconductor chips 2a and 2b illustrated in FIG. Deploy. At this time, the rigid substrate 47 can be directly bonded to the support substrate 1 without using an adhesive. For example, when the rigid substrate 47 is placed on the side of the support substrate 1 where the alignment mark 1a is formed and heat treatment is performed in an oxygen-containing atmosphere at 800 ° C. for 30 minutes, the rigid substrate 47 is directly bonded onto the support substrate 1. Become so.

  Note that, depending on the type of the semiconductor chips 2a and 2b, their characteristics may deteriorate when exposed to heat of 400 ° C. or higher. Therefore, when the rigid substrate 47 is directly bonded on the support substrate 1 by such a high-temperature heat treatment such as 800 ° C., the rigid substrate 47 is mounted in a state where the semiconductor chips 2a and 2b are not disposed on the support substrate 1. Glue.

  As described above, when the rigid substrate 47 is directly bonded onto the support substrate 1 without using an adhesive, it is not necessary to consider the variation in the thickness of the adhesive, and the support substrate 1 is ground later. Sometimes, the support substrate 1 can be thin and processed with high accuracy. Further, the support substrate 1 and the rigid substrate 47 can be bonded very firmly.

FIG. 30 is a schematic cross-sectional view of an example of a semiconductor chip placement step according to the fourth embodiment.
After the rigid substrate 47 is directly bonded onto the support substrate 1, the semiconductor chips 2a and 2b are bonded onto the support substrate 1 in the through hole 47a of the rigid substrate 47, and the electrodes 2c are directed to the support substrate 1 side. Arrange using the member 3.

FIG. 31 is a schematic cross-sectional view of an example of a semiconductor chip covering step according to the fourth embodiment.
After the semiconductor chips 2a and 2b are arranged, the resin 48 that covers the semiconductor chips 2a and 2b is put into the through holes 47a of the rigid substrate 47 to obtain the pseudo wafer 10c.

  Here, an organic resin 48a such as an epoxy resin, a phenol resin, or BCB is first put to cover the semiconductor chips 2a and 2b, and after heat treatment, an inorganic resin 48b is put to coat the organic resin 48a, and further heat treatment is performed. As a result, the resin 48 is formed. The organic resin 48a put in the through hole 47a firmly covers the semiconductor chips 2a and 2b. The inorganic resin 48b formed on the surface of the organic resin 48a plays a role of protecting the organic resin 48a and the semiconductor chips 2a and 2b from chemicals and the like used when forming the via 7 and the wiring 23 to be performed later. Further, the gas generated from the organic resin 48a and the gas generated from the inorganic resin 48b during the heat treatment can be exhausted from the opening of the through hole 47a.

  Thus, by covering the semiconductor chips 2a and 2b arranged in the through hole 47a with the resin 48, the strength of the support substrate 1 in the through hole 47a portion can be ensured. Therefore, it becomes possible to prevent damage to the support substrate 1 starting from the through-hole 47a portion when the support substrate 1 is ground later.

FIG. 32 is a schematic cross-sectional view of an example of a support substrate grinding process according to the fourth embodiment.
After the semiconductor chips 2a and 2b in the through holes 47a are coated with the resin 48, the support substrate 1 is ground. Here, since the rigid substrate 47 is directly bonded onto the support substrate 1, there is no limitation due to variations in the thickness of the adhesive during grinding, and the support substrate 1 can be processed thinly and with high accuracy. . Prior to this grinding, the resin 48 is put into the through-hole 47a to ensure the strength of the support substrate 1, so that the support substrate 1 can be ground while preventing damage to the support substrate 1. Note that after grinding, CMP or etching may be performed on the ground surface to remove grinding traces.

FIG. 33 is a schematic cross-sectional view of an example of a via formation process according to the fourth embodiment.
After the support substrate 1 is ground, first, via holes 6 reaching the semiconductor chips 2a and 2b (electrodes 2c) are formed. Then, a conductive material is formed on the entire surface using a sputtering method, a CVD method, an electroplating method, etc., and the via hole 6 is filled. Then, CMP is performed so that the support substrate 1 is exposed, and surplus conductive material on the support substrate 1 is formed. Remove. As a result, the via 7 is formed in the support substrate 1.

FIG. 34 is a schematic cross-sectional view of an example of a wiring forming process according to the fourth embodiment.
After the via 7 is formed, first, the insulating film 21 is formed on the support substrate 1 on which the via 7 is formed, and the wiring groove 22 is formed there. Then, after a conductive material is formed on the entire surface and the wiring trench 22 is filled, CMP is performed so that the insulating film 21 is exposed, and excess conductive material on the insulating film 21 is removed. Thereby, the wiring 23 which electrically connects between the electrodes 2c of the semiconductor chips 2a and 2b via the vias 7 is formed.

  Also according to the fourth embodiment, the support substrate 1 thinned with good flatness can be used as an insulating film, and the via 7 can be formed therewith with high accuracy, and the wiring 23 can be formed thereover with high accuracy. can do. As a result, it is possible to cope with miniaturization and high density of the via 7 and the wiring 23. Further, by using the rigid substrate 47 in which the through holes 47a are formed, it becomes possible to form the MCM while suppressing the occurrence of warping and breakage.

  Although the case where the support substrate 1 and the rigid substrate 47 are directly bonded by heat treatment is illustrated here, the both may be bonded by an adhesive. In that case, the rigid substrate 47 in which the through-hole 47a is formed is bonded to the support substrate 1 on which the semiconductor chips 2a and 2b are arranged via an adhesive. Thereafter, as in the above, the resin 48 is put into the through hole 47a, the support substrate 1 is ground, and the via 7 and the wiring 23 are formed.

  Further, here, the case where the resin 48 is put into the through hole 47a before grinding is illustrated, but when the possibility that the support substrate 1 is damaged during grinding is low, the support substrate 1 is ground first. It is also possible to insert the resin into the through hole 47a after grinding.

The rigid substrate 47 may be configured as illustrated in FIG. 35 below in addition to the configuration illustrated in FIG.
FIG. 35 is a schematic plan view of another example of the rigid substrate according to the fourth embodiment.

  The rigid substrate 49 illustrated in FIG. 35 is illustrated in FIG. 28 in that planar circular through holes 49a that can accommodate the semiconductor chips 2a and 2b are formed in regions corresponding to the semiconductor chips 2a and 2b. This is different from the rigid substrate 47. Such a planar circular through hole 49a can be formed by etching (dry etching or wet etching), or can be formed by using a grinding member 60 as illustrated in FIG.

  Further, instead of the rigid substrate 47 illustrated in FIG. 28 and the rigid substrate 49 illustrated in FIG. 35, the recesses 44a to 46a of the rigid substrates 44 to 46 illustrated in FIGS. It is also possible to use a rigid substrate.

The first to fourth embodiments have been described above by taking the MCM formation method as an example.
Note that the support substrate 1 and the rigid substrates 30, 40, 44 to 47, 49 described in the first to fourth embodiments have shapes conforming to the SEMI (Semiconductor Equipment and Materials International) standard. Is preferred. Thereby, it becomes easy to apply the existing equipment in semiconductor device manufacture to the above MCM formation.

  In the above description, the case where the alignment mark 1a is formed on the support substrate 1 is exemplified. However, even when such an alignment mark 1a is not formed, it is possible to form the MCM similarly. . For example, when the semiconductor chips 2a and 2b can be arranged on the support substrate 1 with a certain accuracy without using the alignment mark 1a, or vias 7 can be formed in the support substrate 1 after grinding. In some cases, it is not always necessary to form the alignment mark 1a.

  In the above description, the case where the via 7 of the support substrate 1 is formed, the insulating film 21 is formed thereon, and the wiring 23 is formed in the insulating film 21 using the single damascene method is illustrated. In addition, the via 7 and the wiring 23 can be simultaneously formed using a dual damascene method. For example, first, after the support substrate 1 is ground, the insulating film 21 is formed. Then, a via hole 6 that penetrates the insulating film 21 and the support substrate 1 and reaches the electrodes 2c of the semiconductor chips 2a and 2b is formed, and further, a wiring groove 22 is formed in a predetermined region in the insulating film 21 including the region where the via hole 6 is formed. Form. By filling the formed via hole 6 and the wiring groove 22 with a conductive material and removing excess conductive material by CMP, the via 7 and the wiring 23 are formed simultaneously.

  In the above description, the formation of the MCM including the two types of semiconductor chips 2a and 2b has been exemplified. However, the above-described method can be applied to two or more types of semiconductor chips (whether or not their thicknesses are different from each other). It is widely applicable to the formation of MCMs including The present invention is also applicable to the formation of a single chip module (SCM) including only one type of semiconductor chip.

DESCRIPTION OF SYMBOLS 1 Support substrate 1a Alignment mark 2a, 2b Semiconductor chip 2c Electrode 3 Adhesive member 4 Resin substrate 4a, 40a, 44a, 45a, 46a Recess 6, 6a Via hole 7, 7b Via 7a, 23a Conductive material 10, 10a, 10b, 10c Pseudo wafer 21 Insulating film 22 Wiring groove 23 Wiring 30, 40, 41, 44, 45, 46, 47, 49 Rigid substrate 40b Groove 42 Resin 43 Adhesive 47a, 49a Through hole 48 Resin 48a Organic resin 48b Inorganic resin 50 Mask pattern 50a, 50b area 60 grinding member 61 cylindrical body 62 grinding blade

Claims (7)

Disposing a semiconductor chip via an adhesive member above the first main surface of the first substrate;
Disposing a second substrate covering the semiconductor chip above the first main surface;
Forming a conductive portion that penetrates the first substrate and the adhesive member and is electrically connected to the semiconductor chip;
A method for manufacturing a semiconductor device, comprising:   The step of disposing the second substrate includes disposing the second substrate and disposing a rigid third substrate on the side opposite to the first substrate side of the second substrate. 2. A method for manufacturing a semiconductor device according to 1.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a recess for accommodating the semiconductor chip in the second substrate before the second substrate is arranged. Disposing a second substrate having a through hole in which a semiconductor chip is accommodated above the first main surface of the first substrate;
Disposing the semiconductor chip via an adhesive member above the first main surface in the through hole;
Forming a conductive portion penetrating the first substrate and the adhesive member and electrically connected to the semiconductor chip;
A method for manufacturing a semiconductor device, comprising:   5. The method according to claim 1, further comprising a step of thinning the first substrate from a second main surface side opposite to the first main surface before forming the conductive portion. The manufacturing method of the semiconductor device of description. In the step of forming the conductive portion,
Forming a contact hole penetrating the first substrate and the adhesive member and reaching the semiconductor chip;
Forming a conductive material in the formed contact hole;
6. A method of manufacturing a semiconductor device according to claim 1, wherein the method is a semiconductor device manufacturing method. A first substrate;
A semiconductor chip disposed above the first main surface of the first substrate via an adhesive member;
A second substrate covering the semiconductor chip, disposed above the first main surface;
A conductive portion that penetrates the first substrate and the adhesive member and is electrically connected to the semiconductor chip;
A semiconductor device comprising:

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