JP2010177478A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a power MOSFET and a logic circuit which can be manufactured by using a production process directed for logic circuit. <P>SOLUTION: The semiconductor device has a power MOS and a logic circuit. A plurality of first regions are provided side by side in the first direction and in the second direction intersecting with the first direction at the right angle. A guard ring region is provided around to constitute the second region, and a plurality of second regions are further provided side by side in the first direction and the second direction to constitute the third region. The first region has a plurality of MOSFET extended to the first direction and having a plurality of gate electrodes, sources and drains arranged side by side in the second direction, a back gate region, and the first wiring layer connecting these regions each other. In the third region, a power MOSFET is formed where the second wiring layer extended to the second direction and connecting the respective first wiring layers mutually connecting the respective regions, and the third wiring layer extended to the first direction and connecting each of the second wiring layers. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when used for a power MOSFET that passes a relatively large current, such as a protection circuit for a secondary battery, and a logic circuit that forms a control signal thereof. .

  There exists Unexamined-Japanese-Patent No. 2003-282625 as an example of power MOSFET. FIG. 12 shows a power MOS pattern corresponding to FIG. 5 of the publication. The device structure is a power MOS and the base is all common, and the wiring pattern of the source S and drain D is formed only by the metal layer and connected to the PAD. In order to avoid fusing by concentrating current near the PAD, a trapezoidal wiring layout with a thick metal width is being studied near the PAD. It is considered that the current density can be made uniform near the PAD and the PAD counter electrode.

JP 2003-282625 A

  The inventor of the present application studied to configure a power MOSFET and its monitoring control circuit as a secondary battery protection circuit with a single semiconductor device. For example, a new element structure for a power MOS device as described in Japanese Patent Application Laid-Open No. 2003-282625 is developed by using a 0.35 μm standard CMOS metal three-layer process that constitutes the monitoring control circuit as described above. In addition, we examined the formation of a power MOS device on the same substrate as the supervisory control circuit that satisfies the on-resistance and prevents element destruction due to heat generation by devising the wiring pattern in the CMOS / metal three-layer process. .

  In addition, the electrode pattern of the power MOSFET shown in FIG. 12 aims to equalize the current and reduce the on-resistance by making the source and drain parasitic resistance components equal. However, there is a problem that the characteristic variation corresponding to the Vgs drop due to the wiring resistance is not taken into consideration. FIG. 13 shows an equivalent circuit of FIG. FIG. 12 shows an equivalent circuit represented by three MOSFETs M1 to M3 of the source side MOSFET M1, the intermediate side MOSFET M2 and the drain side MOSFET M3. Assuming that the parasitic resistance components on the source side and the drain side of these three MOSFETs M1 to M3 are Rs1, Rs2, Rs3, Rd1, Rd2, and Rd3, respectively, these relationships are expressed by the following equations (1) and (2). Conceivable.

M1 drain side wiring parasitic resistance> M3 drain side wiring parasitic resistance (1)
Here, M1 drain side wiring parasitic resistance = Rd1 + Rd2 + Rd3, and M3 drain side wiring parasitic resistance = Rd3.
M1 source side wiring parasitic resistance <M3 source side wiring parasitic resistance (2)
Here, M1 source side wiring parasitic resistance = Rs1, and M3 source side wiring parasitic resistance = Rs1 + Rs2 + Rs3.

From the above relationship, it can be seen that the influence of the Vgs drop is the smallest on the MOSFET M1 side near the source PAD, and the influence of the Vgs drop is the largest on the MOSFET M3 side near the drain PAD. Since the current driving capability increases as Vgs increases, the relationship of the following expression (3) is established.
I1>I2> I3 (3)
Here, as shown in the equivalent circuit of FIG. 13, I1 is a current flowing through the MOSFET M1, I2 is a current flowing through the MOSFET M2, and M3 is a current flowing through the MOSFET M3.

  Considering the upper wiring layer pattern of FIG. 12, the upper wiring layer lead-out location of the MOSFET M1 is in the lower part of the power MOS and the upper layer lead-out location of the MOSFET M3 is in the upper part. Considering these together, the distribution of the current amount as shown in FIG. 14 is expected. Therefore, in the electrode pattern as shown in FIG. 12, the current is concentrated in the vicinity of the lower part in the PAD arrangement direction, so that the heat generation points are concentrated and the destruction is likely to occur.

  An object of the present invention is to provide a power MOSFET that can be manufactured by a manufacturing process for a logic circuit and a semiconductor device having the logic circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The semiconductor device has a power MOSFET and a control logic circuit. A plurality of first regions are arranged side by side in a first direction and a second direction orthogonal to the first direction, a guard ring region is provided around the first region, and a second region is formed. A plurality of the regions are arranged in the second direction and are configured by the third region. The first region includes a plurality of MOSFETs having a plurality of gate electrodes and sources and drains extending in the first direction and arranged side by side in the second direction, a back gate region for supplying a back bias voltage to the well region, and the gate , A first wiring layer for connecting the source, drain and back gate regions to each other. In the third region, the second wiring layer that connects the first wiring layers that extend in the second direction and connects the gate, source, drain, and back gate regions in the first region to each other; and in the first direction A power MOSFET is formed by providing a third wiring layer that extends and connects the second wiring layers corresponding to the gate, source, drain, and back gate regions.

  A MOSFET formed by the same process as the logic circuit is connected in parallel in small first area units to provide a back gate, and a guard ring is arranged and latched in a relatively small second area unit in which a plurality of first areas are combined. In the large third region where a plurality of second regions are combined, the MOSFETs are connected to each other by a connection configuration of the second wiring layer and the third wiring layer to reduce the on-resistance, and current concentration due to wiring parasitic resistance Can be avoided.

It is a partial top view of one Example of power MOSFET mounted in the semiconductor device concerning this invention. It is a whole top view of one Example of power MOSFET mounted in the semiconductor device concerning this invention. It is a wiring pattern diagram by the second metal layer of the source / drain considering the current concentration of the power MOSFET according to the present invention. It is a wiring pattern diagram by the third metal layer of the source / drain considering the current concentration of the power MOSFET according to the present invention. It is structure explanatory drawing of one Example of power MOSFET which concerns on this invention. It is structural sectional drawing of other one Example of power MOSFET which concerns on this invention. FIG. 5 is an explanatory diagram in which the arrangement of power MOS cells in FIG. 4 is equivalently replaced. FIG. 8 is a current distribution diagram corresponding to FIG. 7. FIG. 6 is another pattern diagram in which the arrangement of the power MOS cells in FIG. 4 is equivalently replaced. It is a block diagram of one Example of the battery pack with which the semiconductor device to which this invention was applied was mounted. It is a block diagram of one Example of the monitoring part of FIG. It is a conventional power MOS pattern diagram. FIG. 13 is an equivalent circuit diagram of FIG. 12. FIG. 13 is a current distribution diagram of the power MOS of FIG. 12.

  A preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 shows a partial plan view of an embodiment of a power MOSFET mounted on a semiconductor device according to the present invention. FIG. 1A shows a minimum unit UNA as a first area, and FIG. 1B shows a second area configured by arranging two minimum units UNA in the horizontal direction and three in the vertical direction. An intermediate unit UNB is shown.

  In FIG. 1A, four gate electrodes G are arranged side by side in a second direction (vertical direction in the figure) orthogonal to the first direction so as to extend in the first direction (horizontal direction in the figure). The A source S, a drain D, a source S, a drain D, and a source S are arranged in order from the top across the gate G. One drain D has two sources S arranged on both sides with a gate G interposed therebetween, and two sources S are arranged on both sides of a gate S with respect to an intermediate source S. That is, the source S is arranged at both upper and lower ends. As a result, in the example of the figure, since four gates G are provided, four MOSFETs are formed correspondingly.

  Although not particularly limited, a back gate region BG that is rectangular so as to surround the periphery of the four MOSFETs is provided. When the MOSFET is a P-channel MOSFET, the source S and drain D are formed of a P + region and formed in an N-type well region. The back gate region BG is composed of an N + type region that supplies a back gate voltage having the same potential as the source S to the N type well region. The N-type well region is not particularly limited, but is formed on a P-type substrate.

  A first metal layer M1 is disposed along the source S and drain D, respectively, and is connected by a contact CNT1. The gate G is composed of a conductive polysilicon layer (PSi), and is connected in common by, for example, a first metal layer (M1) extending in the second direction, which is omitted in the figure. Further, a first metal layer (M1) is provided along the back gate region BG and connected by a contact CNT2. Although not particularly limited, the first metal layer (M1) connected to the source S and the back gate region BG may be connected to each other.

  In FIG. 1 (B), the intermediate unit UNB has two minimum units UNA shown in FIG. 1 (A) arranged in the first direction and three in the second direction as described above, for a total of 6 (2 × 3) Consists of pieces. The boundary between adjacent ones of the minimum unit UNA is divided by a common back gate region BG.

  A rectangular guard ring region GL is provided so as to capture the periphery of the intermediate unit UNB. This guard ring region GL includes a P-type well region formed so as to take in the N-type well region and a P + region formed in the P-type well region when the P-channel MOSFET as described above is used. Composed. The first metal layer (M1) is also provided on the guard ring region GL, and the first metal layer (M1) and the guard ring region GL are electrically connected by a contact.

  FIG. 2 shows an overall plan view of an embodiment of a power MOSFET mounted on a semiconductor device according to the present invention. 2B shows the same intermediate unit UNB as in FIG. 1B, and FIG. 2C is configured by arranging the intermediate unit UNB in the horizontal direction and two in the vertical direction. The entire power MOSFET as the third region is shown. Since FIG. 2B is the same as FIG. 1B, description thereof is omitted.

  In FIG. 2C, the power MOSFET as a whole has a total of 8 (4 × 4 × 4) in which the four intermediate units UNB shown in FIG. 1B are arranged in the first direction and two in the second direction as described above. 2) Consists of pieces. A boundary between adjacent ones of the intermediate units UNB is divided by a common guard ring region GL. Thus, the entire power MOSFET of this embodiment is composed of 4 × 6 × 8 = 192 MOSFETs as shown in FIG. That is, if the one MOSFET is, for example, an output MOSFET of a logic circuit, it can be operated as a power MOS capable of flowing a current about 200 times larger (two digits or more) than that.

  In this embodiment, a control logic circuit is formed by a 0.35 μm standard CMOS / metal three-layer process, and a power MOS is incorporated in the control logic circuit. Thus, in an environment where a power dedicated MOS device is not provided, a plurality of MOSFETs constituting a normal logic circuit are arranged in parallel and used as a power MOS cell. At that time, the guard ring GL is provided at a certain interval, that is, in units of the intermediate unit UNB as shown in FIGS.

  That is, as shown in FIG. 1A, in a minimum unit for forming a power MOS, a certain MOS size (four MOSFETs in the figure) is surrounded by a back gate BG, and a plurality of such patterns are formed. These are arranged side by side to constitute an intermediate unit UNB, and a guard ring GL for preventing latch-up is provided. As for the size of the intermediate unit UNB, if the number of the minimum units UNA is too small, the size of the power MOS cell is increased, and if it is too large, a latch-up failure may occur. Such an intermediate unit UNB is arranged so as to have a size that meets the circuit specifications, thereby completing a power MOS cell. Here, the cell size and the on-resistance of the device itself are sufficiently examined, and if there is an improvement, the minimum unit UNA and the intermediate unit UNB may be reviewed.

  FIGS. 3 and 4 show source / drain wiring patterns in consideration of current concentration of the power MOSFET according to the present invention. In FIG. 3, the source S and drain D of the MOSFET formed in the minimum unit UNA are connected to each other by the second metal layer M2 extending in the second direction (vertical direction). In FIG. 4, the source S and the drain D are connected to each other by the third metal layer M3 extending in the first direction with the interlayer insulating film interposed therebetween.

  That is, in FIG. 3, the same number of sources S and drains D are arranged in the first direction in the second metal layer M2. In the second metal layer M2, in addition to the sources, the first metal layers (M1) connected to the source S of each minimum unit and the first metal layer (M1) connected to the back gate region BG. They may be connected to each other. In FIG. 4, the source and drain D of the second metal layer M2 drawn out in the second direction (vertical direction) are drawn out by the metal 3 layer in the first direction (lateral direction), and the outer peripheral side (near the PAD) is thickened. It arranges with a simple pattern. That is, when the source side pad S-PAD is arranged on the right side of the drawing and the drain side pad D-PAD is arranged on the left side, the source wiring directed from the source side pad S-PAD to the left direction goes to the left. Accordingly, the number is reduced. In this configuration, the number of contacts connecting the second metal layer M2 and the third metal layer M3 is reduced from the right side toward the left side.

  This is because the source wiring and the drain wiring are formed by the third metal layer M3, so that the drain wiring that goes to the right from the drain side pad D-PAD has a pattern opposite to that of the source wiring and is on the right. It is formed so that the number decreases as it goes. In this configuration, the number of contacts connecting the second metal layer M2 and the third metal layer M3 is decreased from the left side toward the right side.

  When configuring a power MOSFET, the gates G must also be connected to each other, and thus omitted in FIGS. 3 and 4, but the second metal layer is provided as appropriate and the gates arranged in the vertical direction are connected to each other. The second metal layers connected to the gates G arranged in the lateral direction are connected by appropriately connecting the third metal layers. However, since the source and drain are arranged on both sides of FIG. 4 as described above, the gate pulls the second metal layer (M2) upward or downward, and above or below the source or drain. A gate electrode may be formed in

  Further, when the P-channel MOSFET as described above is configured, it is necessary to apply a bias voltage such as a ground potential (0 V) to the guard ring region GL. Therefore, the first metal layers (M1) connected to the guard ring region GL are connected to each other using a part of the second metal layer (M2), and the third metal layer (M3) connects them. May be connected to each other so as to give the ground potential of the circuit. When the ground potential is applied by the third metal layer (M3), for example, when the gate is provided above the source and drain, the third metal layer that applies the ground potential to the lower side opposite to the gate. (M3) may be arranged.

  FIG. 5 is a structural explanatory diagram of an embodiment of a power MOSFET according to the present invention. FIG. 5A shows a plan view of the intermediate unit, and FIG. 5B shows a partial cross-sectional view. FIG. 5B is a cross-sectional view taken along line AB in FIG.

  In FIG. 5A, the intermediate unit UNB in FIG. 5 is configured by combining six minimum units UNA corresponding to FIG. In the figure, one minimum unit UNA as shown in FIG. 1A is exemplarily shown as a representative, and the remaining five are shown as black boxes.

  In FIG. 5B, a source (S) and a drain (D) by a P + region are arranged in an N-type well NW formed as an element formation region on a P-type semiconductor substrate P-SUB, and the source (S) The gate (G) is disposed on the semiconductor region sandwiched between the drains (D) via a gate insulating film. Around the MOSFET composed of the source (S), drain (D) and gate (G), a back gate region (BG) composed of an N + region is disposed. A P-type well PW is provided so as to take in the intermediate unit UNB, and a P + region is provided in the P-type well PW to form a guard ring region (GL).

  A MOSFET constituting a logic circuit LOG is provided adjacent to the power MOSFET. For example, a P-channel MOSFET has an N-type well PW formed by being electrically isolated by the guard ring region (GL), and a source (S), a drain (D), and a gate (G) composed of a P + region. A back gate (BG) comprising an N + region for supplying a bias voltage to the N-type well PW is provided. As described above, the P-channel MOSFET constituting the logic circuit LOG and the P-channel MOSFET provided as the minimum unit of the power MOSFET are basically formed by the same manufacturing process, the source (S), the drain (D), It consists of a gate (G) and a back gate region (BG).

  FIG. 6 is a sectional view showing the structure of another embodiment of the power MOSFET according to the present invention. In the embodiment of FIG. 6, a back gate region (BG) composed of an N + region is disposed adjacent to the source (S). That is, in the source (S) in which the drain (D) is arranged on both sides except for the source (S) arranged at both ends of the minimum unit, the back gate region (BG) is sandwiched between the two in the middle portion. A source (S) is arranged. Correspondingly, in the MOSFET of the logic circuit LOG, a back gate region (BG) composed of an N + region is arranged adjacent to the source (S) as described above. In the power MOSFET, a plurality of such minimum units are combined to form an intermediate unit UNB. A P-type well PW is provided to take in the intermediate unit, and a P + region is provided in the P-type well PW to provide a guard ring region. (GL).

  In this embodiment, the concentration of current flowing through the source-drain path is adjusted in the third metal layer M3. As shown in FIGS. 1 to 4, when there is no dedicated power MOS device, a structure having a metal three-layer structure or more is required in consideration of uniform current density and latch-up countermeasures.

  In order to compare the wiring patterns of FIG. 4 in an easy-to-understand manner, the arrangement of the power MOS cells created in FIG. The structure of FIG. 7 is characterized in that a portion having a large wiring resistance component on the source side is disposed in the center of the power MOS and a portion having a small source side wiring resistance component is disposed in the peripheral portion.

  In FIG. 12, which is a conventional pattern, the source-side upper wiring structure and the drain-side upper wiring structure are exactly the same when rotated by 180 °. On the other hand, the pattern of the present invention is characterized in that the power MOSFET has a structure that is symmetric with respect to the center in the first direction (lateral direction), and the drain-side wiring pattern is arranged in the peripheral portion.

  The equivalent circuit is the same as in FIG. 13, and as described above, the influence of the Vgs drop is the smallest on the MOSFET M1 side near the source PAD, and the influence of the Vgs drop is the largest on the M3 side near the drain PAD. In the upper wiring layer pattern, a portion having a large wiring resistance component on the source side is arranged in the center of the power MOS, and a portion having a large drain side wiring resistance component is arranged in the peripheral portion. growing. Further, unlike the conventional pattern shown in FIG. 12, the upper wiring layer lead portion of the MOSFET has a lead structure that is symmetric with respect to the center in the horizontal direction (first direction). A current distribution as shown in FIG. 8 is expected. As these effects, current concentration points can be dispersed vertically, and heat generation points are expected to be dispersed.

  FIG. 9 is another pattern diagram equivalently replaced. This figure corresponds more faithfully to the arrangement of the power MOS cells in FIG. That is, two triangular electrode pattern structures are formed from the source side to the drain side. That is, FIG. 7 is a pattern corresponding to the upper or lower half of FIG. The source and drain electrode structures are determined by such a combination of one or more triangles. At this time, the outermost peripheral portion is characterized by being a drain electrode.

  Thus, the source and drain electrode patterns of the above embodiment are not limited to the case where a power MOSFET is configured by combining MOSFET cells formed by a standard CMOS process as shown in FIG. It can be directly used as a source / drain electrode pattern of a power MOSFET formed by a power MOS process. That is, the equivalently replaced pattern according to the present invention is used as it is as the source and drain electrodes of the power MOS device, and is useful for preventing element breakdown due to current concentration as shown in FIG. It becomes.

  FIG. 10 is a block diagram showing one embodiment of a battery pack on which a semiconductor device to which the present invention is applied is mounted. This embodiment is applied to a battery pack such as a lithium ion secondary battery. The battery pack of this embodiment includes a battery cell CELL, a fuse FS, the monitoring unit, charge / discharge control switches MOSFETQ1, Q2, and resistors Rvcc, Ridt, capacitors C1, C2 as additional circuits. The monitoring unit and the switch MOSFETs Q1 and Q2 are mounted on one semiconductor device LSI. Such a semiconductor device is formed by a standard CMOS process.

  The charge / discharge control switch MOSFETs Q1 and Q2 are composed of two power MOSFETs connected in series. In this embodiment, an N-channel MOSFET is used. The positive electrode + of the battery cell CELL is connected to the positive electrode terminal (+) of the battery pack via the fuse FS. The negative electrode-of the battery cell CELL is connected to the source of the power MOSFET Q1 and the ground terminal GND of the monitoring unit. The drain of the power MOSFET Q1 is connected to the drain of the power MOSFET Q2. The source of the power MOSFET Q2 is connected to the negative terminal (−) of the battery pack.

  The MOSFET Q1 is used to cut off a discharge current, and a discharge control signal DCH formed by the monitoring unit is supplied to the gate. The MOSFET Q2 is used to cut off a charging (charging) current, and a charge control signal CHG formed by the monitoring unit is supplied to the gate. The source of the MOSFET Q2 is connected to the second ground terminal IDT of the monitoring unit via a resistor Ridt. The positive terminal (+) of the battery pack is connected to the power supply terminal VCC of the monitoring chip 3 via a resistor Rvcc. A capacitor C1 for power supply stabilization is connected between the power supply terminal VCC and the ground terminal GND of the monitoring unit. Further, a capacitor C2 is connected between the ground terminal GND of the monitoring unit and the negative terminal (−) of the battery pack.

  A charger or a load circuit is connected to the positive terminal (+) and the negative terminal (−) of the battery pack. For example, the load circuit is an electronic device such as a mobile phone device. In the charging operation, a charger is connected, current flows from the positive electrode terminal (+) of the battery pack toward the positive electrode (+) of the battery cell CELL, and the negative electrode (−) of the battery cell CELL is negative electrode terminal (−). Current flows toward In this case, since a current always flows through the body diode in the MOSFET Q1, the charging operation is stopped by turning off the MOSFET Q2. In the discharging operation, a load circuit is connected, a current flows from the positive electrode (+) of the battery cell CELL to the positive electrode terminal (+) of the battery pack, and the negative electrode of the battery cell CELL from the negative electrode terminal (−) of the battery pack. Current flows toward (-). In this case, since a current always flows through the body diode through the MOSFET Q2, the discharging operation is stopped by turning off the MOSFET Q1. A protective diode is provided between the gates and sources of the MOSFETs Q1 and Q2.

  The IDT terminal (detection terminal) is a negative (ground potential) side power supply terminal for the overcurrent voltage detection input, the charge overcurrent detection input, and the CHG output. The discharge current increases and the input voltage at the IDT terminal becomes the overcurrent detection voltage. When the short circuit current detection voltage is exceeded, the DCH output becomes low level (ground side voltage), and the MOSFET Q1 is turned off. Thereafter, when the input voltage becomes equal to or lower than the overcurrent detection voltage, the DCH output becomes a high level (power supply voltage), and the MOSFET Q1 is turned on to recover from the overcurrent state.

  The DCH signal is a control signal of the MOSFET Q1 supplied to the gate for cutting off the discharge path as described above. When the voltage of the battery cell CELL is normal, the DCH signal becomes high level (VCC), and the MOSFET Q1 is turned on to overdischarge. When a state or an overcurrent state is detected, it becomes low level (ground potential), and the MOSFET Q1 is turned off.

  The CHG signal is a control signal for the MOSFET Q2 supplied to the gate for cutting off the charging path as described above. When the voltage of the battery cell CELL is normal, the CHG signal is set to the high level (VCC), and the MOSFET Q2 is turned on to overcharge. When a state or an excessive charging voltage is detected, it becomes low level (IDT), and the MOSFET Q2 is turned off.

  FIG. 11 is a block diagram showing an example of the monitoring unit. The monitoring unit of this embodiment is not particularly limited, but includes a reference voltage generation circuit, a control circuit, a drive circuit corresponding to the DCH signal and the CHG signal, an upper limit voltage detection circuit, a lower limit voltage detection circuit, an oscillator, and an oscillation pulse of the oscillator. It consists of an overcharge timer, an overdischarge timer, an overcurrent timer, a charger voltage detection circuit, a discharge current, a charge current detection circuit, and the like that operate. The reference voltage formed by the reference voltage generation circuit is used as a reference for detection operations of the upper limit voltage detection circuit, the lower limit voltage detection circuit, the charger voltage, the discharge current, and the charge current voltage detection circuit.

  When the P-channel MOSFET described with reference to FIGS. 1 to 6 is used, the switch is inserted in series in the current path on the positive electrode + side. When the control signals CGG and DCH supplied to the gate are at a low level, the P-channel MOSFET is turned on, and when it is at a high level, the control signals CGG and DCH are turned off.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, the monitoring unit 3 may be anything as long as it performs charge / discharge control as described above. The semiconductor device may be anything as long as a control logic circuit and a power MOSFET are mounted in addition to the one for monitoring the secondary battery.

  The present invention can be widely used for a semiconductor device having a power MOSFET and a logic circuit capable of flowing a relatively large current.

  UNA: minimum unit (first region), UNB: intermediate unit (second region), S: source, D: drain, G ... gate, BG ... back gate region, GL: guard ring region, P-SUB ... semiconductor substrate , NW ... N-type well, PW ... P-type well, Q1, Q2 ... Power MOSFET, CELL ... Battery cell, FS ... Fuse, C1, C2 ... Capacitor, Rvcc, Ridt ... Resistance.

Claims (5)

A first region;
A plurality of first regions arranged side by side in a first direction and a second direction orthogonal to the first direction, and a second region provided with a guard ring region around;
A third region in which a plurality of the second regions are arranged side by side in the first direction and the second direction;
A fourth region,
The first region is
A plurality of MOSFETs extending in the first direction and having a plurality of gate electrodes and sources and drains arranged side by side in the second direction;
A back gate region for supplying a back bias voltage to a well region in which the MOSFET is formed;
A first wiring layer connecting the gate, source, drain and back gate regions to each other;
In the third region,
First wiring layers extending in the second direction and interconnecting the gate, source, drain and back gate regions in the first region are connected to each other, and an insulating film is interposed on the first wiring layer. A formed second wiring layer;
A third wiring layer that extends in the first direction, connects the second wiring layers corresponding to the gate, source, drain, and back gate regions, and is formed on the second wiring layer via an insulating film. And
One switch MOSFET is constituted by the third region,
A semiconductor device in which the fourth region is provided with a plurality of MOSFETs which are formed in the same manufacturing process as the switch MOSFET and constitute a logic circuit. In claim 1,
The back gate region is a semiconductor device formed so as to surround the first region. In claim 1,
The back gate region is a semiconductor device disposed adjacent to the source region of the first region. In claim 2 or 3,
The source and drain formed of the third wiring layer are
One end side in the first direction in the third region is a source side configured in common,
The other end side in the first direction in the third region is configured in common as a drain side,
The third wiring layer on the source side is connected to the second wiring layer from one end side to the other end side, and the number of contacts arranged in the second direction is reduced.
The semiconductor device in which the third wiring layer on the drain side is disposed opposite to the source side. In claim 4,
The switch MOSFET is a protection switch provided in the charge / discharge path of the secondary battery,
The semiconductor device, wherein the logic circuit detects a current or voltage of the secondary battery and performs switch control of the protection switch.

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