JP5532631B2 - Semiconductor device, method for controlling semiconductor device, and protection circuit for secondary battery - Google Patents

Description

  The present invention relates to a semiconductor device, a method for controlling the semiconductor device, and a protection circuit for a secondary battery using the semiconductor device.

  Battery packs that can be handled relatively easily are widely used for portable electronic devices. The battery pack is obtained by storing at least one secondary battery in one package. As the secondary battery, a lithium ion battery, a lithium polymer battery, a nickel-hydride battery, or the like having a higher energy density than a conventional secondary battery is used. However, the higher the energy density, the greater the risk of overheating, overdischarging, or overcurrent of the secondary battery, and sometimes fires. For this reason, in general, a battery pack includes a protection circuit for protecting a secondary battery from overcharge, overdischarge, charge overcurrent, discharge overcurrent, short-circuit current, abnormal overheating, and the like. When it is detected that such protection is necessary, the connection between the secondary battery and the charger or the load device is cut off to prevent the secondary battery from being heated and ignited and to prevent the secondary battery from deteriorating. It is configured.

  FIG. 4 is a block diagram showing a configuration of a battery pack 1A including the protection circuit 2A according to the first conventional technique. In FIG. 4, the battery pack 1A includes a secondary battery 3 and a protection circuit 2A connected to the secondary battery 3, and is connected to a load 4 such as a mobile phone via terminals T1 and T2. When the secondary battery 3 is charged, the charger 5 is connected to the battery pack 1A via the switches SW1 and SW2.

  The protection circuit 2A includes a switch circuit 20A and a control circuit 10A that controls the operation of the switch circuit 20A. The control circuit 10A includes an overcharge detection circuit 11, an overdischarge detection circuit 12, a control signal generation circuit 13A, terminals Vdd and Vss, a discharge control terminal Dout, a charge control terminal Cout, and a terminal V-. Configured. The overcharge detection circuit 11 is connected to the positive terminal and the negative terminal of the secondary battery 3 via the terminal Vdd and the terminal Vss, and the voltage between the positive terminal and the negative terminal of the secondary battery 3 is equal to or higher than a predetermined threshold value. When this is detected, a detection signal S11 indicating the detection result is generated and output to the control signal generation circuit 13A. The overdischarge detection circuit 12 is connected to the positive terminal and the negative terminal of the secondary battery 3 via the terminal Vdd and the terminal Vss, and the voltage between the positive terminal and the negative terminal of the secondary battery 3 is below a predetermined threshold value. Is detected, a detection signal S12 indicating the detection result is generated and output to the control signal generation circuit 13A. Further, the control signal generation circuit 13A generates a predetermined control signal based on the input detection signals S11 and S12 as will be described in detail later, and supplies the control circuit 20A to the switch circuit 20A via the discharge control terminal Dout and the charge control terminal Cout. Output.

  In FIG. 4, a switch circuit 20A formed of a semiconductor device includes N-channel MOS field effect transistors M1 and M2, diodes Di1 and Di2, source terminals TS1 and TS2, and gate terminals TG1 and TG2. The Here, the gate of the N-channel MOS field effect transistor M1 is connected to the discharge control terminal Dout through the gate terminal TG1, the source is connected to the negative terminal of the secondary battery 3 through the source terminal TS1, and the diode Di1. The drain is connected to the drain of the N-channel MOS field effect transistor M2 and the cathodes of the diodes Di1 and Di2. The gate of the N-channel MOS field effect transistor M2 is connected to the charge control terminal Cout via the gate terminal TG2, the source is connected to the terminals V− and T2 via the source terminal TS2, and the anode of the diode Di2 is connected. The drain is connected to the drain of the N-channel MOS field effect transistor M1 and the cathodes of the diodes Di1 and Di2. The diodes Di1 and Di2 are parasitic diodes generated when the semiconductor device of the switch circuit 20A is formed.

  Next, the operation of the battery pack 1A configured as described above will be described. When the state of the secondary battery 3 is a normal state that is not an abnormal state such as overcharge and overdischarge, the control signal generation circuit 13A outputs each control signal for turning on the N-channel MOS field effect transistors M1 and M2. Generated and output to the switch circuit 20A. In a normal state, when the secondary battery 3 is charged, a charging current flows from the left to the right in FIG. 4 via the source terminal TS1, the diode Di1, the N-channel MOS field effect transistor M2, and the source terminal TS2, and at the time of discharging, the source terminal TS2 The discharge current flows from right to left in FIG. 4 through the diode Di2, the N-channel MOS field effect transistor M1, and the source terminal TS2.

  The control signal generation circuit 13A is a control signal for turning off the N-channel MOS field effect transistor M2 in response to the detection signal S11 from the overcharge detection circuit 11 indicating that the secondary battery 3 is overcharged. Is output to the gate terminal TG2, and in response to this, the N-channel MOS field effect transistor M2 is turned off and charging is stopped. Even if the charging is stopped in this way, the discharge current flows through the source terminal TS2, the diode Di2, the N-channel MOS field effect transistor M1, and the source terminal TS1, so that the operation of the load 4 is not stopped. The control signal generation circuit 13A is for turning off the N-channel MOS field effect transistor M1 in response to the detection signal S12 from the overdischarge detection circuit 12 indicating that the secondary battery 3 is overdischarged. A control signal is generated and output to the gate terminal TG1, and in response to this, the N-channel MOS field effect transistor M1 is turned off and the discharge is stopped. Even if the discharge stops in this way, the charging current flows through the source terminal TS1, the diode Di1, the N-channel MOS field effect transistor M2, and the source terminal TS2, so that the secondary battery 3 can be charged.

  Patent Documents 1 and 2 disclose a semiconductor device of a switch circuit 20A that can switch bidirectional current paths used in such a protection circuit 2A.

  Generally, the semiconductor device of the switch circuit 20A used in the protection circuit 2A of the secondary battery 3 has a trench gate structure in which a gate electrode is embedded in a plurality of trenches dug in a semiconductor layer through a gate insulating film. FIG. 5 is a cross-sectional view of the semiconductor device of the switch circuit 20A of FIG. In FIG. 5, a drain region 51 that is an N-type well diffusion region is formed in a semiconductor substrate 50. Further, two channel layers 52 a and 52 b which are P-type conductive regions are formed on the drain region 51. A gate electrode G1 is embedded in each of the four trenches 61 dug to a depth reaching the drain region 51 from the surface of the channel layer 52a via a gate insulating film 62. A gate electrode G2 is embedded in each of the four trenches 63 dug up to the depth reaching the drain region 51 from the surface of the channel layer 52b via the gate insulating film 64. Further, source regions S1 and S2 which are N-type conductive regions are formed on the respective surfaces of the channel layers 52a and 52b. The four gate electrodes G1 are connected to the gate terminal TG1 through the wiring WG1, and the four gate electrodes G2 are connected to the gate terminal TG2 through the wiring WG2. Each source region S1 is connected to the source terminal TS1 via the wiring WS1, and each source region S2 is connected to the source terminal TS2 via the wiring WS2. As described above, in FIG. 5, the N-channel MOS field effect transistors M <b> 1 and M <b> 2 are arranged separately on the semiconductor substrate 50.

  FIG. 5 shows a current path 43 when both N-channel MOS field effect transistors M1 and M2 are on. In FIG. 5, the longitudinal direction (the direction parallel to the drain region 51) of the semiconductor device of the switch circuit 20A and the direction perpendicular to the drain region 51 are defined as an x direction and a y direction, respectively. When the secondary battery 3 is discharged, the discharge current flows from the source region S2 to the source region S1 via the current path 43. Specifically, the discharge current flows in the y direction from all the source regions S2 of the N-channel MOS field effect transistor M2 toward the drain region 51, and the discharge current reaching the drain region 51 passes through the drain region 51 through the N channel. Flows in the x direction from the n-type MOS field effect transistor M2 side toward the n-channel type MOS field effect transistor M1 side, and further in the y direction from the drain region 51 toward all the source regions S1 of the n-channel type MOS field effect transistor M1. Flowing. Further, when charging the secondary battery 3, the charging current flows from the source region S 1 to the source region S 2 via the current path 43. Specifically, the charging current flows in the y direction from all the source regions S1 to the drain region 51 of the N-channel MOS field effect transistor M1, and the charging current reaching the drain region 51 flows through the drain region 51 through the N channel. Flows in the x direction from the n-type MOS field effect transistor M1 side toward the n-channel type MOS field effect transistor M2 side, and further in the y direction from the drain region 51 toward all the source regions S2 of the n-channel type MOS field effect transistor M2. Flowing.

  Since the secondary battery 3 is consumed as the ON resistance of the switch circuit 20A increases, the switch circuit 20A is required to have a smaller ON resistance. In general, in a semiconductor device having a trench gate structure, since the channel layers 52a and 52b are extremely thin, the contribution of the channel layers 52a and 52b to the on-resistance can be made extremely small. However, in the semiconductor device of FIG. 5, the N-channel MOS field effect transistors M1 and M2 are arranged separately on the semiconductor substrate 50, so that the path length in the drain region 51 with respect to the entire path length of the current path 43. Is relatively large, and most of the on-resistance depends on the path length of the current path 43 in the drain region 11. For this reason, it has been difficult to reduce the on-resistance.

  FIG. 6 is a cross-sectional view of the semiconductor device of the switch circuit 20B according to the second prior art. The equivalent circuit of the switch circuit 20B is the same as the equivalent circuit (see FIG. 4) of the switch circuit 20A in FIG. In FIG. 6, a drain region 51 that is an N-type well diffusion region is formed in a semiconductor substrate 50. Further, a channel layer 52 which is a P-type conductive region is formed on the drain region 51, and three trenches dug so as to divide across the channel layer 52 from the surface of the channel layer 52 to a depth reaching the drain region 51. Gate electrodes G 1 and G 2 are embedded in each of 71 through a gate insulating film 72. Here, as shown in FIG. 6, the gate electrode G <b> 1 is formed on one side wall of the inner walls of the trench 71, and the gate electrode G <b> 2 is formed on the other side wall of the inner walls of the trench 71. Further, source regions S1 and S2 which are N-type conductive regions are alternately formed on the surface of the channel layer 52 between the trenches 71. The three gate electrodes G1 are connected to the gate terminal TG1 through the wiring WG1, and the three gate electrodes G2 are connected to the gate terminal TG2 through the wiring WG2. Each source region S1 is connected to the source terminal TS1 via the wiring WS1, and each source region S2 is connected to the source terminal TS2 via the wiring WS2.

  FIG. 6 shows the current path 44 when both N-channel MOS field effect transistors M1 and M2 are on. In FIG. 6, when the secondary battery 3 is discharged, the discharge current flows from the source region S2 to the source region S1 via the current path 44. Specifically, the discharge current flows in the y direction from each source region S2 of the N-channel MOS field effect transistor M2 toward the drain region 51, and the discharge current reaching the drain region 51 is drain region below the trench 71. It flows in the x direction through 51, and flows in the y direction toward the source region S1 formed on the opposite side of the trench 71. Further, when the secondary battery 3 is charged, the charging current flows from the source region S1 to the source region S2 via the current path 44. Specifically, the charging current flows in the y direction from each source region S1 of the N-channel MOS field effect transistor M1 toward the drain region 51, and the charging current that has reached the drain region 51 is drain region below the trench 71. It flows in the x direction through 51 and flows in the y direction toward the source region S2 formed on the opposite side of the trench 71.

  According to the switching circuit 20B according to the second prior art, the on-resistance can be reduced by shortening the length of the current path 44 in the drain region 51 as compared with the switching circuit 20A according to the first prior art. Be expected. However, in the semiconductor device of the switching circuit 20B according to the second prior art, different gate electrodes G1 and G2 for the N-channel MOS field effect transistors M1 and M2 are formed on the two inner walls of one trench 71. It is necessary to make the width of the trench 71 wider than the trenches 61 and 63 of the switching circuit 20A according to the first prior art. For this reason, the length of the current path 44 in the drain region 51 cannot be significantly reduced as compared with the switching circuit 20A according to the first prior art, and the on-resistance cannot be sufficiently reduced. .

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and to further reduce the on-resistance by reducing the length of the current path of the current flowing through the semiconductor device as compared with the prior art, a method for controlling the semiconductor device, and An object of the present invention is to provide a secondary battery protection circuit using the semiconductor device.

  According to a first aspect of the present invention, there is provided a semiconductor device including a plurality of blocks having the same configuration and formed repeatedly in a longitudinal direction on a semiconductor substrate, wherein each of the blocks is formed on the semiconductor substrate. A drain region; a channel layer formed on the drain region; and first to fourth trenches formed to penetrate the channel layer to reach the drain region and to be divided across the channel layer. The first to fourth gate electrodes respectively formed through the gate insulating film and the channel layer between the trenches are formed to correspond to the first to fourth trenches, respectively. First to fourth source regions, all the second gate electrodes are electrically connected to each other, and all the fourth gate electrodes are electrically connected to each other. All the first and third gate electrodes are electrically connected to each other, all the first and second source regions are electrically connected to each other, and all the third and fourth source regions are connected. Are electrically connected to each other.

  According to a second aspect of the present invention, there is provided a control method for a semiconductor device that operates as a switch circuit, wherein the switch circuit includes a gate that is the second gate electrode, and the second gate electrode. A first N-channel MOS field effect transistor having a source that is the first and second source regions and a drain that is the drain region, and a gate that is the fourth gate electrode. A second N-channel MOS field effect transistor having a source as the third and fourth source regions and a drain as the drain region formed on both sides of the fourth gate electrode, A third gate having a gate as the first and third gate electrodes, a source as the first and second source regions, and a drain as the drain region. A fourth N-channel having a channel-type MOS field-effect transistor, a gate that is the first and third gate electrodes, a source that is the third and fourth source regions, and a drain that is the drain region And a first MOS field effect transistor for generating first, second, and third control signals and applying them to the second gate electrode, the fourth gate electrode, and the first and third gate electrodes, respectively. Thus, the first to fourth N-channel MOS field effect transistors are on / off controlled.

  In the method for controlling a semiconductor device, the first and second source regions are connected to a negative electrode terminal of a secondary battery, and the third and fourth source regions are connected to a load connected to the secondary battery. The first, second and third control signals are generated based on at least the voltage of the secondary battery.

  In the method of controlling the semiconductor device, when the voltage abnormality or voltage normality of the secondary battery is detected based on the voltage of the secondary battery, and the voltage normal state is detected, the first to fourth The first to third control signals are generated so as to turn on the N-channel MOS field effect transistor.

  Further, in the method for controlling the semiconductor device, when the voltage abnormality or voltage normality of the secondary battery is detected based on the voltage of the secondary battery, and the voltage abnormality state is detected, the first and second The first to third control signals are generated so as to turn off at least one of the N-channel MOS field effect transistors and turn off the third and fourth N-channel MOS field effect transistors. And

  A protection circuit for a secondary battery according to a third invention comprises the semiconductor device, and is connected between the secondary battery and a load connected to the secondary battery, and the secondary battery. And a control circuit connected in parallel to each other, wherein the first and second source regions are connected to a negative electrode terminal of the secondary battery, and the third and fourth source regions are The switch circuit connected to the load includes a gate as the second gate electrode, a source as the first and second source regions formed on both sides of the second gate electrode, and the drain. A first N-channel MOS field effect transistor having a drain as a region; a gate as the fourth gate electrode; and the third and fourth sources formed on both sides of the fourth gate electrode. The source that is the area, and above A second N-channel MOS field effect transistor having a drain which is a drain region; a gate which is the first and third gate electrodes; a source which is the first and second source regions; and the drain. A third N-channel MOS field effect transistor having a drain as a region; a gate as the first and third gate electrodes; a source as the third and fourth source regions; and the drain region. A fourth N-channel MOS field effect transistor having a drain, and the control circuit generates first, second, and third control signals based on at least the voltage of the secondary battery. The first to fourth N-channels are applied to the second gate electrode, the fourth gate electrode, and the first and third gate electrodes, respectively. Characterized by on-off control type MOS field-effect transistor.

  In the protection circuit for the secondary battery, the control circuit detects the voltage abnormality or voltage normality of the secondary battery based on the voltage of the secondary battery, and detects the voltage normal state when the first voltage is detected. The first to third control signals are generated to turn on the fourth to fourth N-channel MOS field effect transistors.

  Further, in the protection circuit for the secondary battery, the control circuit detects the voltage abnormality or voltage normality of the secondary battery based on the voltage of the secondary battery, and detects the voltage abnormality state. The first to third control signals so as to turn off at least one of the first and second N-channel MOS field effect transistors and turn off the third and fourth N-channel MOS field effect transistors. It is characterized by generating.

  According to the semiconductor device of the present invention, in the semiconductor device including a plurality of blocks having the same configuration, which are repeatedly formed in the longitudinal direction on the semiconductor substrate, each of the blocks is formed on the semiconductor substrate. A drain region; a channel layer formed on the drain region; and first to fourth trenches formed to penetrate the channel layer to reach the drain region and to be divided across the channel layer. The first to fourth gate electrodes respectively formed through the gate insulating film and the channel layer between the trenches are formed to correspond to the first to fourth trenches, respectively. First to fourth source regions, all the second gate electrodes are electrically connected to each other, and all the fourth gate electrodes are electrically connected to each other. All the first and third gate electrodes are electrically connected to each other, all the first and second source regions are electrically connected to each other, and all the third and fourth sources are connected to each other. The regions are electrically connected to each other. Therefore, since only one gate electrode is formed in each trench, the width of each trench can be narrowed compared to the prior art, the current path passing under the trench can be shortened, and the on-resistance of the semiconductor device can be reduced.

  Further, according to the method for controlling a semiconductor device and the protection circuit for a secondary battery according to the present invention, since the semiconductor device is used as a switch circuit connected between the secondary battery and a load, compared with the prior art. The secondary battery can be charged and discharged with a large current, and the charging time can be shortened and the charging efficiency and discharging efficiency can be improved. Furthermore, it is possible to provide a protection circuit that has a small amount of heat generation and is easy to use for the user as compared with the prior art.

It is a block diagram which shows the structure of the battery pack 1 provided with the protection circuit 2 which concerns on embodiment of this invention. FIG. 2 is a plan view of the semiconductor device of the switch circuit 20 in FIG. 1. FIG. 3 is a cross-sectional view taken along line AB of the semiconductor device of FIG. 2. It is a block diagram which shows the structure of 1 A of battery packs provided with the protection circuit 2A based on 1st prior art. FIG. 5 is a cross-sectional view of the semiconductor device of the switch circuit 20A of FIG. It is sectional drawing of the semiconductor device of the switch circuit 20B based on 2nd prior art.

  Hereinafter, embodiments according to the present invention will be described with reference to the drawings. In addition, in each following embodiment, the same code | symbol is attached | subjected about the same component. Note that in this specification, the number number of the black brackets in which the mathematical formula is input and the mathematical formula number of the square brackets in which the mathematical formula is input are mixedly used.

Embodiment.
FIG. 1 is a block diagram showing a configuration of a battery pack 1 including a protection circuit 2 according to an embodiment of the present invention. 1 is a plan view of the semiconductor device of the switch circuit 20 in FIG. 1, and FIG. 3 is a cross-sectional view taken along line AB of the semiconductor device in FIG. 2 and 3, the longitudinal direction (the direction parallel to the drain region 51) of the semiconductor device of the switch circuit 20A and the direction perpendicular to the drain region 51 are defined as an x direction and a y direction, respectively.

  In FIG. 1, a battery pack 1 includes a secondary battery 3 and a protection circuit 2 connected to the secondary battery 3, and is connected to a load 4 such as a mobile phone via terminals T1 and T2. When the secondary battery 3 is charged, the charger 5 is connected to the battery pack 1 via the switches SW1 and SW2.

  The protection circuit 2 includes a switch circuit 20 and a protection circuit 10 that controls the operation of the switch circuit 20. The control circuit 10 includes an overcharge detection circuit 11, an overdischarge detection circuit 12, a failure detection circuit 14, a control signal generation circuit 13, terminals Vdd and Vss, a discharge control terminal Dout, and a charge control terminal Cout. A gate control terminal Gout and a terminal V− are provided.

  The overcharge detection circuit 11 is connected to the positive terminal and the negative terminal of the secondary battery 3 via the terminal Vdd and the terminal Vss. When the overcharge detection circuit 11 detects that the voltage between the positive electrode terminal and the negative electrode terminal of the secondary battery 3 is equal to or higher than a predetermined first threshold value, the overcharge detection circuit 11 generates a high level detection signal S11 indicating the detection result. On the other hand, when it is detected that the voltage between the positive terminal and the negative terminal of the secondary battery 3 is less than the first threshold value, the low level detection signal indicating the detection result is output to the control signal generation circuit 13. S11 is generated and output to the control signal generation circuit 13. Here, the first threshold value is set to a value corresponding to the voltage when the secondary battery 3 is overcharged or overcharged.

  Further, the overdischarge detection circuit 12 is connected to the positive terminal and the negative terminal of the secondary battery 3 through the terminal Vdd and the terminal Vss. When the overdischarge detection circuit 12 detects that the voltage between the positive terminal and the negative terminal of the secondary battery 3 is equal to or lower than a predetermined second threshold value, it generates a high level detection signal S12 indicating the detection result. On the other hand, when it is detected that the voltage between the positive terminal and the negative terminal of the secondary battery 3 is larger than the second threshold value, the low level detection signal S12 indicating the detection result is output. Is output to the control signal generation circuit 13. Here, the second threshold value is set to a value corresponding to the voltage at the time of overdischarge or overdischarge current of the secondary battery 3.

  Further, the failure detection circuit 14 is connected to the negative terminal of the secondary battery 3 via the terminal Vss, and is connected to the terminal TS2 of the switch circuit via the terminal V−. When the overdischarge detection circuit 12 detects that the voltage between the terminals Vss and V− is equal to or higher than a predetermined third threshold value, the overdischarge detection circuit 12 generates a high level detection signal S14 indicating the detection result and generates a control signal. On the other hand, when it is detected that the voltage between the terminals Vss and V− is less than the third threshold value, the control signal generating circuit 13 generates a low level detection signal S14 indicating the detection result. Output to. Here, the third threshold value is set to a value corresponding to a voltage when a fatal failure such as a short circuit occurs in the secondary battery 3.

  The control signal generation circuit 13 generates predetermined control signals Cd, Cc, and Cg based on the input detection signals S11, S12, and S14, as will be described in detail later, and includes a discharge control terminal Dout, a charge control terminal Cout, and a gate. Each is output to the switch circuit 20 via the control terminal Gout.

  In FIG. 1, a switch circuit 20 made of a semiconductor device includes N-channel MOS field effect transistors M1 to M4, diodes Di1 and Di2, source terminals TS1 and TS2, and gate terminals TG1 to TG3. The As will be described in detail later, the switch circuit 20 is a circuit that can switch bidirectional current paths. Here, the gate G1 of the N-channel MOS field effect transistor M1 is connected to the discharge control terminal Dout through the gate terminal TG1, and the source S1 is connected to the negative terminal of the secondary battery 3 through the source terminal TS1. Connected to the anode of the diode Di1. The gate G2 of the N-channel MOS field effect transistor M2 is connected to the charge control terminal Cout via the gate terminal TG2, the source S2 is connected to the terminals V− and T2 via the source terminal TS2, and the diode Di2 is connected. Connected to the anode. Further, the gate G3 of the N-channel MOS field effect transistor M3 is connected to the gate control terminal Gout via the gate terminal TG3, and the source S3 is connected to the negative electrode terminal of the secondary battery 3 via the source terminal TS1 and a diode. Connected to the anode of Di1. Furthermore, the gate G4 of the N-channel MOS field effect transistor M4 is connected to the gate control terminal Gout through the gate terminal TG3, the source S4 is connected to the terminals V− and T2 through the source terminal TS2, and the diode Di2. Connected to the anode. The diodes Di1 and Di2 are parasitic diodes generated when the semiconductor device of the switch circuit 20 is formed, and the cathodes of the diodes Di1 and Di2 and the drains of the N-channel MOS field effect transistors M1 to M4 are commonly drained. It is connected to a region 51 (details will be described later with reference to FIG. 3).

  2 and 3, the semiconductor device of the switch circuit 20 includes a plurality of N blocks Bn (n = 1, n) having the same configuration and formed repeatedly in the longitudinal direction (x direction) of the semiconductor device. 2, ..., N). Each block Bn includes a drain region 51 that is an N-type well diffusion region formed on the semiconductor substrate 50, a channel layer 52 that is a P-type conductive region formed on the drain region 51, and a channel layer 52. Formed in four trenches 53a, 53b, 53c, 53d formed so as to penetrate through to the drain region 51 and to be divided across the channel layer 52 via gate insulating films 54a, 54b, 54c, 54d, respectively. Gate electrode E1, E2, E3, E4, source region 56a formed on channel layer 52 between trench 53a and trench 53b, and channel layer 52 between trench 53b and trench 53c. Source region 56b formed and source region 5 formed on channel layer 52 between trench 53c and trench 53d. And c, constructed and a source region 56d formed on the channel layer 52 between the block Bn + 1 of the trench 53a of the trench 53d and the adjacent. A parasitic diode Di1 is formed between the source regions 56a and 56b and the drain region 51, and a parasitic diode Di2 is formed between the source regions 56c and 56d and the drain region 51. Source regions 56a to 56d are N-type conductive regions. Further, as shown in FIG. 2, on each channel layer 52 divided by the trenches 53a to 53d, source regions 56a to 56d, which are N-type conductive regions, and two P-type conductive regions 55 are formed by photolithography. Is formed. The P-type conductive region 55 is formed to take out the potential of the channel layer 52. The total number N of the blocks Bn is determined based on the maximum values of the discharge current and the charging current flowing through the switch circuit 20, and the total number N is set to a larger value as the maximum value is larger.

  Further, in FIG. 3, the gate electrodes E2 of all the blocks B1 to BN are electrically connected to each other using the wiring WG1, and the wiring WG1 is connected to the gate terminal TG1. Further, the gate electrodes E4 of all the blocks B1 to BN are electrically connected to each other using the wiring WG2, and the wiring WG2 is connected to the gate terminal TG2. The gate electrodes E1 and E3 of all the blocks B1 to BN are electrically connected to each other using the wiring WG3, and the wiring WG3 is connected to the gate terminal TG3. Further, the source regions 56a and 56b of all the blocks B1 to BN are electrically connected to each other using the wiring WS1, and the wiring WS1 is connected to the source terminal TS1. Furthermore, the source regions 56c and 56d of all the blocks B1 to BN are electrically connected to each other using the wiring WS2, and the wiring WS2 is connected to the source terminal TS2.

By configuring the semiconductor device of the switch circuit 20A as described above, the following four N-channel MOS field effect transistors M1 to M4 are repeatedly formed on the semiconductor substrate 50.
(A) an N-channel MOS field effect transistor M1 having a gate G1 that is the gate electrode E2, a source S1 that is the source regions 56a and 56b formed on both sides of the gate electrode E2, and a drain that is the drain region 51;
(B) an N-channel MOS field effect transistor M2 having a gate G2 as the gate electrode E4, a source S2 as the source regions 56c and 56d formed on both sides of the gate electrode E4, and a drain as the drain region 51;
(C) an N-channel MOS field effect transistor M3 having a gate G3 as the gate electrodes E1 and E3, a source S3 as the source regions 56a and 56b, and a drain as the drain region 51;
(D) An N-channel MOS field effect transistor M4... Having a gate G4 as the gate electrodes E1 and E3, a source S4 as the source regions 56d and 56c, and a drain as the drain region 51.

  That is, as shown in FIGS. 2 and 3, each N-channel MOS field effect transistor M1 is formed on both sides of the gate electrode E2, and each N-channel MOS field effect transistor M2 is formed on both sides of the gate electrode E4. Each N channel type MOS field effect transistor M3 is formed on the N channel type MOS field effect transistor M1 side of the gate electrodes E1 and E3, and each N channel type MOS field effect transistor M4 is an N channel type of the gate electrodes E1 and E3. It is formed on the MOS field effect transistor M2 side.

  Next, the operation of the switch circuit 20 configured as described above will be described. Table 1 shows the relationship between the state of the switch circuit 20, the voltage levels of the gate terminals TG1 to TG3, the on / off states of the N-channel MOS field effect transistors M1 to M4, and the on resistance value Rs between the terminals TS1 and TS2. It is a table | surface which shows. In Table 1, the high-level and low-level voltage levels are described as “H” and “L”. The on-resistance values of the channel-type MOS field effect transistors M1 to M4 are defined as R1 to R4, respectively, and the on-resistance values of the diodes Ri1 and Ri2 are defined as Rd1 and Rd2, respectively.

(1) First state.
In the first state, the voltage levels of all the gate terminals TG1 to TG3 are set to a high level. At this time, all the N-channel MOS field effect transistors M1 to M4 are turned on. Therefore, the on-resistance value Rs during charging when current flows from the terminal TS1 to the terminal TS2 and during discharging when current flows from the terminal TS2 to the terminal TS1 is expressed by the following equations, and the on-resistance value Rs in each of the first to eighth states. The smallest of them.

  FIG. 3 shows a current path 41 between the N-channel MOS field effect transistors M1 and M2 and a current path 422 between the N-channel MOS field effect transistors M3 and M4 in the first state. Since the sources S1 and S2 of the N-channel MOS field effect transistors M1 and M2 are formed on both sides of the gate electrode E1 and on both sides of the gate electrode E3, the current paths 41 and 42 in the drain region 51 are connected to the gate electrodes E1 and E3. Passes only under the trenches 53a and 53b formed respectively. Specifically, the current path 41 passes through the vicinity of the trench 53b from the source region 56a to the drain region 51 in the y direction, passes through the drain region 11 in the x direction, and passes through the trench 53d from the drain region 51 to the source region 56d. The path passing in the y direction, the vicinity of the trench 53b from the source region 56b to the drain region 51 in the y direction, the drain region 11 through the x direction, and the vicinity of the trench 53d from the drain region 51 to the source region 56c in the y direction And a route through. The current path 42 passes in the y direction from the source region 56d to the drain region 51 in the vicinity of the trench 53a, passes through the drain region 11 in the x direction, and passes in the y direction from the drain region 51 to the source region 56a in the vicinity of the trench 53a. A path passing through the vicinity of the trench 53c from the source region 56b to the drain region 51 in the y direction, a path passing through the drain region 11 in the x direction, and a path passing through the vicinity of the trench 53c from the drain region 51 to the source region 56c in the y direction. including.

(2) Second state.
In the second state, the voltage levels of the gate terminals TG2 and TG3 are set to a high level, and the voltage level of the gate terminal TG1 is set to a low level. At this time, the N-channel MOS field effect transistors M2 to M4 are turned on, and the N-channel MOS field effect transistor M1 is turned off. Therefore, the on-resistance value Rs during charging and discharging is expressed by the following equations, respectively.

(3) Third state.
In the third state, the voltage levels of the gate terminals TG1 and TG3 are set to a high level, and the voltage level of the gate terminal TG2 is set to a low level. At this time, the N-channel MOS field effect transistors M1, M3, and M4 are turned on, and the N-channel MOS field effect transistor M2 is turned off. Therefore, the on-resistance value Rs during charging and discharging is expressed by the following equations, respectively.

(4) Fourth state.
In the fourth state, the voltage level of the gate terminal TG3 is set to a high level, and the voltage levels of the gate terminals TG1 and TG2 are set to a low level. At this time, the N-channel MOS field effect transistors M3 and M4 are turned on, and the N-channel MOS field effect transistors M1 and M2 are turned off. Therefore, the on-resistance value Rs during charging and discharging is expressed by the following equations, respectively.

[Equation 1]
Rs = R3 + R4

(5) Fifth state.
In the fifth state, the voltage levels of the gate terminals TG1 and TG2 are set to a high level, and the voltage level of the gate terminal TG3 is set to a low level. At this time, the N-channel MOS field effect transistors M1 and M2 are turned on, and the N-channel MOS field effect transistors M3 and M4 are turned off. Therefore, the on-resistance value Rs during charging and discharging is expressed by the following equations, respectively.

[Equation 2]
Rs = R1 + R2

(6) Sixth state.
In the sixth state, the voltage level of the gate terminal TG2 is set to a high level, and the voltage levels of the gate terminals TG1 and TG3 are set to a low level. At this time, the N-channel MOS field effect transistor M2 is turned on, and the N-channel MOS field effect transistors M1, M3, and M4 are turned off. Accordingly, in the sixth state, the on-resistance value Rs during charging is expressed by the following equation. On the other hand, since the parasitic diode D1 prevents current flow from the source S2 to the source S1, no discharge current flows.

[Equation 3]
Rs = Rd1 + R2

(7) Seventh state.
In the seventh state, the voltage level of the gate terminal TG1 is set to a high level, and the voltage levels of the gate terminals TG2 and TG3 are set to a low level. At this time, the N-channel MOS field effect transistor M1 is turned on, and the N-channel MOS field effect transistors M2, M3, and M4 are turned off. Accordingly, in the seventh state, the on-resistance value Rs during discharge is expressed by the following equation. On the other hand, since the current flow from the source S1 to the source S2 is blocked by the parasitic diode D2, no charging current flows.

[Equation 4]
Rs = R1 + Rd2

(8) Eighth state.
In the eighth state, each voltage level of all the gate terminals TG1 to TG3 is set to a low level. At this time, all the N-channel MOS field effect transistors M1 to M4 are turned off. Therefore, no current flows between the terminals TS1 and TS2.

  Next, a method for controlling the operation of the switch circuit 20 by the control signal generation circuit 13 will be described. The control signal generation circuit 13 switches the state of the switch circuit 20 to one of the first, sixth, seventh, and eighth states based on the input detection signals S11, S12, and S14. Control. Specifically, in response to the low level detection signals S11, S12, S14, the control signal generation circuit 13 generates the high level control signals Cd, Cc, Cg and outputs them to the gate terminals TG1, TG2, TG3, respectively. Thus, the state of the switch circuit 20 is switched to the first state. Further, in response to the high level detection signal S12, the control signal generation circuit 13 generates the low level control signal Cd, the high level control signal Cc, and the low level control signal Cg to generate the gate terminal TG1. , TG2, and TG3, respectively, to switch the state of the switch circuit 20 to the sixth state. Further, in response to the high level detection signal S11, the control signal generation circuit 13 generates the high level control signal Cd, the low level control signal Cc, and the low level control signal Cg to generate the gate terminal TG1. , TG2, and TG3, respectively, thereby switching the state of the switch circuit 20 to the seventh state. In response to the high level detection signal S14, the control signal generation circuit 13 generates the low level control signals Cd, Cc, Cg and outputs them to the gate terminals TG1, TG2, TG3, respectively. The 20 state is switched to the eighth state. The control voltage generation circuit 13 does not switch the state of the switch circuit 20 to the second to fifth states.

  That is, the control circuit 10 uses the overcharge detection circuit 11 and the overdischarge detection circuit 12 to normal voltage between the positive and negative terminals of the secondary battery 3 that is greater than the second threshold value and smaller than the first threshold value. Is detected, the switch circuit 20 is switched to the first state to control the N-channel MOS field effect transistors M1 to M4 to be turned on. When the control circuit 10 (a) detects an abnormal voltage between the positive and negative terminals of the secondary battery 3 that is equal to or higher than the first threshold by the overcharge detection circuit 11, (b) the overdischarge detection circuit 11 When a voltage abnormality between the positive electrode and negative electrode terminal of the secondary battery 3 below the second threshold is detected by (c), or (c) the voltage between the terminals Vss and V− is set to the third threshold by the failure detection circuit 14. When a voltage abnormality of the secondary battery 3 that is greater than or equal to the value is detected, at least one of the N-channel MOS field effect transistors M1 and M2 is turned off and the N-channel MOS field effect transistors M3 and M4 are turned off. To control.

  For example, when the load 4 is connected to the battery pack 1 and the secondary battery 3 is in a discharge state, if the secondary battery 3 is in an overdischarge state, the overdischarge detection circuit 12 causes the positive terminal of the secondary battery 3 and It is detected that the voltage between the negative terminals is equal to or lower than the second threshold value, and a high level detection signal S12 is generated. In response to this, the control signal generation circuit 13 switches the state of the switch circuit 20 to the sixth state. As a result, the N-channel MOS field effect transistor M2 is set to be on, and the N-channel MOS field effect transistors M1, M3, and M4 are switched off. As a result, the current flowing from the terminal TS2 to the terminal TS1 is cut off, so that the power supply from the secondary battery 3 to the load 4 is cut off. However, since the current from the terminal TS1 to the terminal TS2 can flow through the parasitic diode Di1 and the N-channel MOS field effect transistor M2, the secondary battery 3 can be charged.

  Next, in this state, when the charger 5 is connected to the battery pack 1 via the switches SW1 and SW2, the direction of the current flowing through the switch circuit 20A is reversed, and the parasitic diode Di1 and the N-channel MOS field effect transistor are reversed. A charging current flows from the terminal TS1 toward the terminal TS2 via M2. Then, the overdischarge detection circuit 12 detects that the voltage between the positive terminal and the negative terminal of the secondary battery 3 has become larger than the second threshold value, and generates a low level detection signal S12. In response to this, the control signal generation circuit 13 switches the state of the switch circuit 20 to the first state. As a result, since all the N-channel MOS field effect transistors are turned on, the on-resistance value Rs between the terminals TS1 and TS2 is minimized. For this reason, the secondary battery 3 can be charged with a large current. Immediately after the charger 5 is connected to the battery pack 1, only the N-channel MOS field effect transistor M2 is turned on, but the parasitic diode Di1 is compared with the on-resistance value R2 of the N-channel MOS field effect transistor. Since the on-resistance value Rd1 is overwhelmingly large, the charging current flows.

  Furthermore, when the secondary battery 3 is overcharged when the charger 5 is connected to the battery pack 1 and the secondary battery 3 is in a charged state, the overcharge detection circuit 11 causes the positive terminal of the secondary battery 3 to be connected. When the voltage between the negative terminal and the negative terminal is equal to or higher than the first threshold value, a high level detection signal S11 is generated. In response to this, the control signal generation circuit 13 switches the state of the switch circuit 20 to the seventh state. As a result, the N-channel MOS field effect transistor M1 is set to remain on, and the N-channel MOS field effect transistors M2, M3, and M4 are switched off. As a result, the current flowing from the terminal TS1 to the terminal TS2 is cut off, so that the charging current from the charger 5 to the secondary battery 3 is cut off. However, since the current from the terminal TS2 to the terminal TS1 can flow through the parasitic diode Di2 and the N-channel MOS field effect transistor M1, the secondary battery 3 can be discharged.

  Next, when the load 4 is connected to the secondary battery 3 in this state, a discharge current flows. Then, the overcharge detection circuit 11 detects that the voltage between the positive terminal and the negative terminal of the secondary battery 3 has become less than the first threshold value, and generates a low level detection signal S11. In response to this, the control signal generation circuit 13 switches the state of the switch circuit 20 to the first state. As a result, since all the N-channel MOS field effect transistors M1 to M4 are turned on, the on-resistance value Rs between the terminals TS1 and TS2 is minimized. For this reason, the secondary battery 3 can be discharged with a large current.

  Further, when a fatal failure such as a short circuit that cannot charge / discharge the battery pack 1 occurs, the failure detection circuit 14 detects that the voltage between the terminals Vss and V− is equal to or higher than the third threshold value. Thus, a high level detection signal S14 is generated. In response to this, the control signal generation circuit 13 switches the state of the switch circuit 20 to the eighth state. As a result, all N-channel MOS field effect transistors M1 to M4 are turned off and the terminals TS1 and TS2 are completely cut off, so that the secondary battery 3 is neither charged nor discharged.

  As described above in detail, according to the semiconductor device of the switch circuit 20 according to the present embodiment, since only one gate electrode is formed in each of the trenches 53a to 53d, the switch according to the second prior art in FIG. Compared with the semiconductor device of the circuit 20B, the width of each of the trenches 53a to 53d can be made extremely narrow. For this reason, the length of the current paths 41 and 43 passing under the trenches 53a and 53c is shortened, and the on-resistance of the switch circuit 20 can be reduced. In addition, since the width of each of the trenches 53a to 53d can be reduced as compared with the prior art, more N-channel MOS field effect transistors can be formed on the same semiconductor substrate 50, and the on-resistance of the switch circuit 20 can be reduced. Furthermore, since the on-resistance of the switch circuit 20 can be reduced as compared with the prior art, heat generation in the switch circuit 20 can be reduced.

  According to the protection circuit 2 according to the present embodiment, since the above-described switch circuit 20A is used, the secondary battery 3 can be charged / discharged with a large current as compared with the prior art, and the charging time and the charging efficiency and discharge can be shortened. Efficiency can be improved. Furthermore, it is possible to provide the protection circuit 2 that has a smaller calorific value than the prior art and is easy to use for the user.

  As described above in detail, according to the semiconductor device of the present invention, in each of the semiconductor devices including a plurality of blocks having the same configuration, which are repeatedly formed in the longitudinal direction on the semiconductor substrate, each of the blocks is A drain region formed on the semiconductor substrate, a channel layer formed on the drain region, and formed so as to penetrate the channel layer to reach the drain region and to be divided across the channel layer. The first to fourth trenches are formed on the channel layers between the first to fourth gate electrodes formed in the first to fourth trenches through the gate insulating film, and between the trenches. First to fourth source regions formed so as to correspond to each other, all the second gate electrodes are electrically connected to each other, and all the fourth gate electrodes are connected to each other. All the first and third gate electrodes are electrically connected to each other, all the first and second source regions are electrically connected to each other, and all the first and third gate electrodes are electrically connected to each other. The third and fourth source regions are electrically connected to each other. Therefore, since only one gate electrode is formed in each trench, the width of each trench can be narrowed compared to the prior art, the current path passing under the trench can be shortened, and the on-resistance of the semiconductor device can be reduced.

  Further, according to the method for controlling a semiconductor device and the protection circuit for a secondary battery according to the present invention, since the semiconductor device is used as a switch circuit connected between the secondary battery and a load, compared with the prior art. The secondary battery can be charged and discharged with a large current, and the charging time can be shortened and the charging efficiency and discharging efficiency can be improved. Furthermore, it is possible to provide a protection circuit that has a small amount of heat generation and is easy to use for the user as compared with the prior art.

1 ... Battery pack,
2 ... Protection circuit,
3 ... secondary battery,
4 ... Load,
5 ... Charger,
10: Control circuit,
11 ... Overcharge detection circuit,
12: Overdischarge detection circuit,
13 ... control signal generation circuit,
14 ... Fault detection circuit,
20 ... Switch circuit,
41, 42 ... current path,
50 ... Semiconductor substrate,
51 ... drain region,
52 ... Channel layer (P-type conductive region),
53a, 53b, 53c, 53d ... trench,
54a, 54b, 54c, 54d ... gate insulating film,
55 ... P-type conductive region,
56a, 56b, 56c, 56d ... Source region (N-type conductive region)
Di1, Di2 ... diodes,
E1, E2, E3, E4 ... gate electrodes,
M1, M2, M3, M4... N-channel MOS field effect transistors.

Japanese Patent No. 4115084. JP2003-201228A.

Claims (13)

A method for controlling a semiconductor device connected to a secondary battery,
The semiconductor device includes a plurality of blocks having the same configuration and formed repeatedly in the longitudinal direction on a semiconductor substrate ,
Each block above
A drain region formed on the semiconductor substrate;
A channel layer formed on the drain region;
First to fourth trenches are formed through gate insulating films in first to fourth trenches formed so as to penetrate the channel layer, reach the drain region, and are divided across the channel layer. A fourth gate electrode;
First to fourth source regions formed on the channel layer between the trenches so as to correspond to the first to fourth trenches, respectively.
Upper Symbol second gate electrode are electrically connected to each other,
Fourth gate electrode above SL are electrically connected to each other,
The first and third gate electrodes above SL are electrically connected to each other,
It said first and second source regions are electrically connected to each other,
A source region of the third and fourth are electrically connected to each other,
The semiconductor device is
A first N having a gate as the second gate electrode, a source as the first and second source regions formed on both sides of the second gate electrode, and a drain as the drain region. A channel MOS field effect transistor;
A second N having a gate as the fourth gate electrode, a source as the third and fourth source regions formed on both sides of the fourth gate electrode, and a drain as the drain region. A channel MOS field effect transistor;
A third N-channel MOS field effect transistor having a gate which is the first and third gate electrodes, a source which is the first and second source regions, and a drain which is the drain region;
A fourth N-channel MOS field effect transistor having a gate as the first and third gate electrodes, a source as the third and fourth source regions, and a drain as the drain region. ,
First, second, and third control signals are generated and applied to the second gate electrode, the fourth gate electrode, and the first and third gate electrodes, respectively. 4 N-channel MOS field effect transistors are turned on and off,
The first and second source regions are connected to the negative electrode terminal of the secondary battery,
The third and fourth source regions are connected to a load connected to the secondary battery,
A method for controlling a semiconductor device , characterized in that the first, second and third control signals are generated based on at least the voltage of the secondary battery . Based on the voltage of the secondary battery, abnormal voltage or normal voltage of the secondary battery is detected, and when the normal voltage state is detected, the first to fourth N-channel MOS field effect transistors are turned on. 2. The method of controlling a semiconductor device according to claim 1 , wherein the first to third control signals are generated as described above. Based on the voltage of the secondary battery, the voltage abnormality or voltage normality of the secondary battery is detected, and when the voltage abnormality state is detected, the first and second N-channel MOS field effect transistors are detected. 3. The semiconductor according to claim 1, wherein the first to third control signals are generated so that at least one of them is turned off and the third and fourth N-channel MOS field effect transistors are turned off. Device control method. All the second gate electrodes are electrically connected to each other;
All the fourth gate electrodes are electrically connected to each other;
All the first and third gate electrodes are electrically connected to each other;
All the first and second source regions are electrically connected to each other;
4. The method of controlling a semiconductor device according to claim 1, wherein all the third and fourth source regions are electrically connected to each other. A semiconductor device connected to a secondary battery,
In a semiconductor device provided with a plurality of blocks having the same configuration mutually formed in the longitudinal direction on a semiconductor substrate,
Each block above
A drain region formed on the semiconductor substrate;
A channel layer formed on the drain region;
First to fourth trenches are formed through gate insulating films in first to fourth trenches formed so as to penetrate the channel layer, reach the drain region, and are divided across the channel layer. A fourth gate electrode;
First to fourth source regions formed on the channel layer between the trenches so as to correspond to the first to fourth trenches, respectively.
The second gate electrodes are electrically connected to each other;
The fourth gate electrodes are electrically connected to each other;
The first and third gate electrodes are electrically connected to each other;
It said first and second source regions are electrically connected to each other,
A source region of the third and fourth are electrically connected to each other,
The first and second source regions are connected to the negative electrode terminal of the secondary battery,
The third and fourth source regions are connected to a load connected to the secondary battery,
A semiconductor device which generates a control signal based on at least the voltage of the secondary battery . The semiconductor device is
A gate upper SL is a second gate electrode, and a source is the second of said first and second source regions formed on both sides of the gate electrode, a first having a drain and a said drain region An N-channel MOS field effect transistor;
A second N having a gate as the fourth gate electrode, a source as the third and fourth source regions formed on both sides of the fourth gate electrode, and a drain as the drain region. A channel MOS field effect transistor;
A third N-channel MOS field effect transistor having a gate which is the first and third gate electrodes, a source which is the first and second source regions, and a drain which is the drain region;
A fourth N-channel MOS field effect transistor having a gate as the first and third gate electrodes, a source as the third and fourth source regions, and a drain as the drain region. ,
First as the control signal, generates a second and a third control signal, the second gate electrode, a fourth gate electrode, and by applying to the first and third gate electrodes, the 6. The semiconductor device according to claim 5, wherein the first to fourth N-channel MOS field effect transistors are on / off controlled . Based on the voltage of the secondary battery, abnormal voltage or normal voltage of the secondary battery is detected, and when the normal voltage state is detected, the first to fourth N-channel MOS field effect transistors are turned on. 7. The semiconductor device according to claim 6 , wherein the first to third control signals are generated as described above . Based on the voltage of the secondary battery, the voltage abnormality or voltage normality of the secondary battery is detected, and when the voltage abnormality state is detected, the first and second N-channel MOS field effect transistors are detected. 8. The semiconductor according to claim 6 , wherein the first to third control signals are generated so that at least one of them is turned off and the third and fourth N-channel MOS field effect transistors are turned off. Equipment . All the second gate electrodes are electrically connected to each other;
All the fourth gate electrodes are electrically connected to each other;
All the first and third gate electrodes are electrically connected to each other;
All the first and second source regions are electrically connected to each other;
The semiconductor device according to claim 5, wherein all the third and fourth source regions are electrically connected to each other. A secondary battery protection circuit,
A switch circuit connected between the load connected to the secondary battery,
A control circuit connected in parallel to the secondary battery ,
The semiconductor device constituting the switch circuit includes a plurality of blocks having the same configuration and formed repeatedly in the longitudinal direction on the semiconductor substrate ,
Each block above
A drain region formed on the semiconductor substrate;
A channel layer formed on the drain region;
First to fourth trenches are formed through gate insulating films in first to fourth trenches formed so as to penetrate the channel layer, reach the drain region, and are divided across the channel layer. A fourth gate electrode;
First to fourth source regions formed on the channel layer between the trenches so as to correspond to the first to fourth trenches, respectively.
Upper Symbol second gate electrode are electrically connected to each other,
Fourth gate electrode above SL are electrically connected to each other,
The first and third gate electrodes above SL are electrically connected to each other,
It said first and second source regions are electrically connected to each other,
A source region of the third and fourth are electrically connected to each other,
The first and second source regions are connected to the negative terminal of the secondary battery, and the third and fourth source regions are connected to the load,
The switch circuit is
A first N having a gate as the second gate electrode, a source as the first and second source regions formed on both sides of the second gate electrode, and a drain as the drain region. A channel MOS field effect transistor;
A second N having a gate as the fourth gate electrode, a source as the third and fourth source regions formed on both sides of the fourth gate electrode, and a drain as the drain region. A channel MOS field effect transistor;
A third N-channel MOS field effect transistor having a gate which is the first and third gate electrodes, a source which is the first and second source regions, and a drain which is the drain region;
A fourth N-channel MOS field effect transistor having a gate as the first and third gate electrodes, a source as the third and fourth source regions, and a drain as the drain region. ,
The control circuit generates first, second, and third control signals based on at least the voltage of the secondary battery, and generates the second gate electrode, the fourth gate electrode, and the first and second A protection circuit for a secondary battery, wherein the first to fourth N-channel MOS field effect transistors are controlled to be turned on and off by being respectively applied to three gate electrodes . The control circuit detects an abnormal voltage or normal voltage of the secondary battery based on the voltage of the secondary battery, and when the normal voltage state is detected, the first to fourth N-channel MOS electric fields are detected. 11. The protection circuit for a secondary battery according to claim 10, wherein the first to third control signals are generated so as to turn on the effect transistor. The control circuit detects voltage abnormality or voltage normality of the secondary battery based on the voltage of the secondary battery, and detects the voltage abnormality state when the first and second N-channel MOS electric fields are detected. claim, characterized in that for generating the first to third control signals so as to turn off the off vital said third and fourth N-channel type MOS field effect transistor at least one of the effect transistor 10 Or the protection circuit of the secondary battery of 11 . All the second gate electrodes are electrically connected to each other;
All the fourth gate electrodes are electrically connected to each other;
All the first and third gate electrodes are electrically connected to each other;
All the first and second source regions are electrically connected to each other;
The secondary battery protection circuit according to claim 10, wherein all the third and fourth source regions are electrically connected to each other.

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