JP2010165778A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing semiconductor device that can improve the planarity of an interlayer insulating film, without causing increase in the number of manufacturing steps, by forming an interlayer insulating film having the optimum film thickness, according to the height and interval of a pattern. <P>SOLUTION: The method of manufacturing semiconductor device includes an interlayer insulating film forming step of forming on a substrate 1, an interlayer insulating film 3 of an optimum film thickness T for covering a pattern 2, by computing the optimum film thickness T of the interlayer insulating film 3 to be formed on the substrate 1, according to the vertical and longitudinal ratio K=S/h of pattern interval S and a pattern height h in the pattern 2 of the predetermined shape formed on the substrate 1, and a planarization step of achieving reflow planarization with the heat treatment of the interlayer insulating film 3 formed on the substrate 1. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of smoothing a pattern by covering it with an interlayer insulating film.

In a manufacturing method of a semiconductor device using an atmospheric pressure CVD apparatus having a single dispersion head, a BPSG (Boro-phospho silicate glass) film is conventionally used as an interlayer insulating film.
In the manufacture of a semiconductor device using a BPSG film, for example, as shown in FIG. 4A, a BPSG film 3 is formed on the semiconductor substrate 1 on which the wiring 2 is formed, and then shown in FIG. As described above, heat treatment is performed to flatten the BPSG film 3 by reflow. Next, as shown in FIG. 4C, conductor wiring 4 is formed on the BPSG film 3 (Prior Art 1). Note that a plurality of arrows in FIG. 4B represent heating.

As another method for manufacturing a semiconductor device using a BPSG film, for example, a method described in Patent Document 1 has been proposed.
In this method, a first BPSG film and a second BPSG film are sequentially formed on a semiconductor substrate on which wiring is formed, and then heat treatment is performed to reflow planarize the first and second BPSG films. Then, at least the second BPSG film portion is etched back and planarized, and then conductor wiring is formed on the planarized BPSG film (prior art 2).

JP-A-6-236847

The inventor investigated the relationship between the wiring interval and the flatness of the BPSG film in the semiconductor device manufactured by the prior art 1, and the result is shown in FIG. In the graph of FIG. 5, the horizontal axis is the wiring spacing S, the vertical axis is the flatness H of the BPSG film, ◆ is the case of boron concentration 3.4% and phosphorus concentration 4.5%, ■ is boron concentration 3.4%, phosphorus The concentration is 5.3%, Δ is the case of boron concentration 3.4% and phosphorus concentration 6.2%, and × is the case of boron concentration 3.6% and phosphorus concentration 6.9%.
6 is a diagram for explaining the flatness H in FIG. 5, where a is the minimum height from the substrate 1 to the lowest position of the surface of the BPSG film 3, and b is the highest of the surface of the BPSG film 3 from the substrate 1. It is the maximum height up to a high position, and the flatness H of the BPSG film 3 is expressed by H = a / b × 100%. FIG. 5 is a graph when the height h of the wiring 2 shown in FIG. 4A is 270 nm, and the maximum height h ₁ of the BPSG film 3 after film formation (before reflow) is 1.5 h = 405 nm. It is.

FIG. 5 shows that the flatness H of the BPSG film 3 can be improved by increasing the concentration of impurities (phosphorus concentration and boron concentration) contained in the BPSG film 3.
However, in the case of the prior art 1, even if the impurity concentration is increased, the flatness tends to deteriorate when the distance S between the wirings 2 exceeds about 0.8 μm, and in the region of 2.0 μm or more, the BPSG film thickness 3 Even if the impurity concentration of the BPSG film is increased to the maximum at which precipitation does not occur, the flatness H is not improved.

  The inventor also examined the relationship between the wiring interval and the flatness of the PSG film (phosphorus concentration 9%) in the semiconductor device manufactured by the prior art 1, and the result is shown in FIG. For comparison, FIG. 7 also shows the relationship between the wiring interval and the flatness of the BPSG film (boron concentration 3.4%, phosphorus concentration 5.3%). In the graph of FIG. 7, ◯ is the data of the PSG film, and ◆ is the data of the BPSG film. From FIG. 7, it can be seen that the PSG film, like the BPSG film, tends to deteriorate the flatness when the distance S between the wirings 2 exceeds about 1 μm.

  Therefore, in the prior art 1, the flatness of the BPSG film 3 and the PSG film has not been improved even in the region where the distance S between the wirings 2 exceeds about 0.8 μm, and the conductor wiring 4 is not BPSG film 3 or PSG. Problems remain such as missing in the recesses of the film, the conductor wiring 4 being disconnected and the quality of the semiconductor device being deteriorated, the yield is lowered, and the productivity is also lowered (see FIG. 4C).

  In the case of the prior art 1, even if the impurity concentration is optimized and the heat treatment conditions are optimized in order to improve the flatness H of the BPSG film 3 and the PSG film, the generation of precipitates, the fluctuation of the characteristics of the semiconductor product, etc. There are limitations due to the occurrence of side effects. Further, for example, even when the BPSG film 3 having a low flatness after reflowing is to be improved by etching back, the unevenness of the BPSG film is reflected as it is, so that it is difficult to increase the flatness.

In the prior art 2, the first and second BPSG films are formed to increase the total film thickness, thereby improving the flatness of the entire BPSG film by reflow planarization and further improving the flatness by etch back. However, since the BPSG film forming process needs to be performed twice, there is a problem that the manufacturing process increases.
Further, in the prior art 2, an optimum film thickness of the BPSG film according to the height and interval of the wiring, that is, a film thickness that can improve the flatness while being as thin as possible is not studied.

When etching back the BPSG film after reflow until the flatness reaches 100%, the higher the etching amount, the more the material and film formation time of the BPSG film will be wasted, and the etch back time will be longer. Therefore, it is advantageous to increase the flatness as much as possible during reflow.
If a thick BPSG film is formed as in prior art 2, the flatness after reflow is improved, but if the BPSG film is formed thick, material and film formation time are wasted. In addition, in order to reduce the thickness of the entire semiconductor device to be manufactured, the thick BPSG film after reflow must be thinned, so that the etching amount increases and the etch back time also increases.

  The present invention has been made to solve such problems, and by increasing the number of manufacturing steps by forming an interlayer insulating film with an optimum film thickness according to the height and interval of the pattern. An object of the present invention is to provide a method of manufacturing a semiconductor device that can improve the flatness of an interlayer insulating film.

  Thus, according to the present invention, the optimum interlayer insulating film to be formed on the substrate according to the aspect ratio K = S / h between the pattern interval S and the pattern height h in the pattern of a predetermined shape formed on the substrate. A thickness T is calculated, and an interlayer insulating film forming step for forming an interlayer insulating film on the substrate with the optimum film thickness T so as to cover the pattern, and a flat for reflow flattening by heat-treating the interlayer insulating film on the substrate There is provided a method for manufacturing a semiconductor device including a manufacturing step.

According to the present invention, when an interlayer insulating film is formed on a pattern formed on a substrate to cover the pattern, an optimum film thickness that provides high flatness while being as thin as possible according to the aspect ratio K of the pattern. An interlayer insulating film can be formed with T.
As a result, it is possible to reduce the amount of material for the interlayer insulating film and shorten the time for thinning, improve the yield and productivity of the semiconductor device, and manufacture a high-quality semiconductor device.

1A to 1D are schematic process diagrams showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention. It is a graph which shows the basic data regarding this invention for calculating | requiring the optimal film thickness of the BPSG film | membrane required in order to obtain the BPSG film | membrane of 90% or more of flatness. 3A to 3C are schematic process diagrams showing Embodiment 2 of the method for manufacturing a semiconductor device of the present invention. 4A to 4C are schematic process diagrams showing a method of manufacturing a semiconductor device according to Prior Art 1. FIG. It is a graph regarding this invention which shows the correlation with wiring space | interval and the flatness of a BPSG film | membrane. It is explanatory drawing which defines the flatness of an interlayer insulation film. It is a graph regarding this invention which shows the correlation with wiring space | interval and the flatness of a PSG film | membrane.

According to the method of manufacturing a semiconductor device of the present invention, an interlayer insulating film to be formed on a substrate according to an aspect ratio K = S / h between a pattern interval S and a pattern height h in a pattern having a predetermined shape formed on the substrate. An optimum film thickness T is calculated, an interlayer insulation film forming step for forming an interlayer insulation film on the substrate with the optimum film thickness T so as to cover the pattern, and a reflow planarization by heat-treating the interlayer insulation film on the substrate And a planarization step.

Here, the “semiconductor device” is a semiconductor device in which elements such as a transistor, a thyristor, a diode, a memory, a capacitor, a resistor, and a coil are formed on a substrate, and the “pattern” is a wiring pattern, an element pattern, and a wiring. A composite pattern in which a pattern and an element pattern are mixed is included.
In the present invention, the substrate is not particularly limited, and examples thereof include a semiconductor substrate, an SOI substrate, a glass substrate, and a ceramic substrate.
In this semiconductor device manufacturing method, the material of the interlayer insulating film is not particularly limited, but a BPSG film and a PSG (Phospho-silicate Glass) film are applicable, and the BPSG film can be formed and reflowed at a lower temperature than the PSG film. Is preferred. These can be generally formed by chemical vapor deposition (CVD).

In the process of manufacturing a semiconductor device having a pattern on the above-described various substrates, the present invention provides a pattern height and interval, and a flatness of the interlayer insulating film in the flattening step to facilitate flattening of 90% or more. An interlayer insulating film is formed on the substrate so as to cover the pattern with an optimum film thickness T in consideration of the flatness of the interlayer insulating film obtained by reflow planarization. Here, the optimum film thickness T means the height of an arbitrary position on the surface of the interlayer insulating film from the substrate, for example, the highest height or the lowest height of the surface of the interlayer insulating film from the substrate.
That is, the present invention pays attention to the relationship between the pattern aspect ratio K (= pattern interval S / pattern height h) and the flatness H of the interlayer insulating film obtained by the reflow flattening, thereby making the film thickness as thin as possible. This is a method of manufacturing a semiconductor device in which an interlayer insulating film is formed with (optimum film thickness T), and the flatness H of the interlayer insulating film can be planarized to 90% or more by reflow planarization.
Hereinafter, a semiconductor device and a manufacturing method thereof according to the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
1A to 1D are schematic process diagrams showing a first embodiment of a method of manufacturing a semiconductor device according to the present invention. In FIG. 1, the same elements as those in FIG. 4 are denoted by the same reference numerals.

<Interlayer insulating film formation process>
In this method of manufacturing a semiconductor device, as shown in FIG. 1A, first, a pattern interval S and a height h in an aspect ratio K = S / h in a pattern 2 of a predetermined shape formed on a substrate 1 are set. Accordingly, the optimum film thickness T of the interlayer insulation film 3 to be formed on the substrate 1 is calculated, and the interlayer insulation film 3 is formed on the substrate 1 with the optimum film thickness T so as to cover the pattern 2.

In the first embodiment, a wiring (for example, a gate wiring) is formed as the pattern 2, and a BPSG film (boron concentration: 3.4%, phosphorus concentration) is used as the interlayer insulating film 3 by using an atmospheric pressure CVD apparatus having a single dispersion head. The optimum film thickness T of the BPSG film to be formed is calculated as the maximum height from the substrate 1 to the highest position on the surface of the BPSG film 3.
The optimum film thickness T of the BPSG film having the impurity concentration is calculated based on the data shown in FIG.

  The data shown in FIG. 2 is based on the data shown in FIG. 5, and a BPSG film having a flatness H of 90% or more (including 100%) with respect to the aspect ratio K = S / h of the wiring 2 is used. It is a graph which calculates | requires the optimal film thickness T of the BPSG film | membrane required in order to obtain. In FIG. 2, the vertical axis represents the ratio T / h between the optimum film thickness T and the height h of the wiring 2, and the horizontal axis represents the aspect ratio K = S / h of the wiring 2. Here, the flatness H is represented by H = a / b × 100 (%) as described in FIG. 2 representatively illustrates the case of a BPSG film having a boron concentration of 3.4% and a phosphorous concentration of 5.3%. In the present invention, data as shown in FIG. 2 is shown depending on the boron and phosphorus concentrations. To get.

As shown in FIG. 2, in the present invention, when the aspect ratio K of the wiring 2 is less than 3 (K <3), the optimum film thickness T of the BPSG film 3 (see FIG. 1A) in the interlayer insulating film forming step. ) At least 1.5 times the wiring height h (T / h ≧ 1.5), the BPSG film 3 can be reflow flattened to a flatness of 90% or higher in the subsequent flattening step.
Therefore, in order to form a BPSG film as thin as possible when K <3, the optimum film thickness T = 1.5 h is set. For example, when the wiring height h is 0.4 μm, the optimum film thickness T of the BPSG film is set. Is 0.4 × 1.5 = 0.6 (μm).

As shown in FIG. 2, in the present invention, when the aspect ratio K of the wiring 2 is 3 to 10 (3 ≦ K ≦ 10), the optimum film thickness T of the BPSG film is set to T = By setting to h × (K−1.5), the BPSG film 3 can be reflow planarized to a flatness of 90% or more by a subsequent planarization process.
Therefore, for example, when the aspect ratio K is 5 and the wiring height h is 0.4 μm, the optimum film thickness T of the BPSG film is set to 0.4 × (5-1.5) = 1.4 (μm).
If the BPSG film 3 having a thickness of 1.4 μm cannot be formed at a time due to the performance of the atmospheric pressure CVD apparatus, the BPSG film having a total film thickness of 1.4 μm may be formed in two steps.

As shown in FIG. 2, when K <3, the ratio T / h between the maximum thickness T of the BPSG film 3 and the height h of the wiring 2 when 3 ≦ K ≦ 10 and K <10. It is known that cracks occur in the formed BPSG film 3 when the value exceeds 8.5.
Therefore, in the case of K <3 and 3 ≦ K ≦ 10, the upper limit of the maximum thickness b of the BPSG film is a value satisfying the ratio T / h <8.5. For example, the height h of the wiring 2 is The maximum thickness of the BPSG film 3 allowed at 0.4 μm is less than 21.3 μm.
In addition, when the wiring aspect ratio K exceeds 10, even if the optimum film thickness T of the BPSG film 3 is applied to the calculation formula of T = h × (K−1.5), generation of cracks cannot be avoided. This case is dealt with by the method of Embodiment 2 described later.

<Planarization process>
As shown in FIG. 1A, after forming a BPSG film 3 with an optimum film thickness T on a substrate 1 having wirings 2, the BPSG film 3 is heat-treated at 900 to 950 ° C. for 10 to 30 minutes, for example. As shown in FIG. 1B, the BPSG film 3 is reflow flattened. The flattened BPSG film 3 has a flatness H of 90% or more. Note that a plurality of arrows in FIG. 1B represent heating.
Since the BPSG film 3 is formed with the optimum film thickness T corresponding to the aspect ratio K = S / h which is the ratio of the height h of the wiring 2 which is the base step and the interval S between the wirings 2, the BPSG film is formed by this heat treatment. Since 3 has a sufficient amount that can be liquefied and flattened, a high flatness H of 90% or more can be obtained.

<Other processes>
After the planarization step, as shown in FIG. 1C, a thinning step for thinning the BPSG film 3 to a predetermined thickness may be performed. For the thinning treatment, for example, etching or chemical mechanical polishing can be used. If the thickness of the BPSG film 3 after the flattening step is thin to a predetermined thickness, the thinning step is omitted.
Further, after the thinning step, the conductor wiring 4 may be formed on the BPSG film 3 as shown in FIG.

  In the first embodiment, when the pattern interval S of the wiring 2 on the substrate includes both K <3 and 3 ≦ K ≦ 10, the BPSG film having the optimum film thickness T corresponding to the widest pattern interval S 3 may be formed.

(Embodiment 2)
3A to 3C are schematic process diagrams showing Embodiment 2 of the method for manufacturing a semiconductor device of the present invention. In FIG. 3, the same elements as those in FIG. 1 are denoted by the same reference numerals.
In the second embodiment, as shown in FIG. 3A, when the pattern of the wiring 2 has a pattern interval S that satisfies K> 10, before the interlayer insulating film forming step, between the patterns that satisfy K> 10. An inter-pattern adjustment process is performed in which the dummy pattern 2a is formed and K ≦ 10 is adjusted. As a result, the interval S ₁ between the wiring 2 and the dummy pattern 2a satisfies K ≦ 10.
If K ≦ 10 is not satisfied with one dummy pattern 2a, two or more dummy patterns are formed between the wirings 2 and 2, or the width of one dummy pattern is widened to satisfy K ≦ 10. You can do it.

The dummy pattern 2a can be formed simultaneously with the formation of the wiring 2 on the substrate 1 and at the same height h as the wiring 2. However, the dummy pattern 2a is formed only in the region where the active element is disposed. It's okay.
In other words, when active elements such as transistors, thyristors, memories, diodes, capacitors, resistors, and coils are arranged in the region where the wiring 2 is formed on the substrate 1, the BPSG film 3 is required to have a high flatness. A dummy pattern 2a is formed in a wiring formation region in which elements are arranged. In this case, the active element includes at least one of a case where the active element is arranged on the same plane as the wiring 2 and a case where the active element is arranged in a layer above the wiring 2.
On the other hand, in the case where the active element is not arranged and the wiring pattern satisfies K> 10, the BPSG film formed thereon is not required to have a flatness of 90% or more by reflow. It is not necessary to form a pattern.

Thereafter, as shown in FIG. 3B, a BPSG film 3 is formed on the substrate 1 so as to cover the wiring 2 and the dummy pattern 2a. Since the distance S ₁ between the wiring 2 and the dummy pattern 2 a is adjusted so that K ≦ 10, the BPSG film 3 can be formed with an optimum film thickness T that does not cause cracks in the BPSG film 3.
Next, as shown in FIG. 3C, the BPSG film 3 is heat-treated and reflow planarized.
Thereafter, as in FIGS. 1C and 1D, the BPSG film 3 may be thinned and the conductor wiring 4 may be formed thereon.

(Other embodiments)
1. In the above embodiment, the case where the BPSG film is used as the interlayer insulating film has been described. However, the present invention is not limited to this, and other insulating films (for example, PSG films) may be used.
2. In the above embodiment, the case where the atmospheric pressure CVD apparatus is used as the CVD apparatus has been described. However, the present invention is not limited to this, and it is needless to say that the present invention can be similarly applied to other CVD apparatuses (for example, a low pressure CVD apparatus). . The CVD apparatus may have a single dispersion head or a plurality of dispersion heads.
3. In the above embodiment, the wiring pattern is exemplified as the pattern on the substrate. However, the present invention is not limited to this, and an element pattern or a composite pattern in which the wiring pattern and the element pattern are mixed may be used.
4). In the above-described embodiment, the case where the pattern on the substrate is covered flat with the interlayer insulating film is exemplified. However, the present invention is also applicable to the case where a semiconductor device having a multilayer structure in which the pattern and the interlayer insulating film are further formed thereon is formed. The invention is applicable.

  The method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device having an element pattern of a transistor, a thyristor, a diode, a memory, a capacitor, a resistor, a coil or the like, a wiring pattern, and a composite pattern in which the element pattern and the wiring pattern are mixed. It is applicable to.

1 substrate 2 pattern (wiring)
2a Dummy pattern 3 Interlayer insulating film (BPSG film)
4 Conductor wiring h Height S, S ₁ interval T Optimal film thickness

Claims (8)

The optimum film thickness T of the interlayer insulating film to be formed on the substrate is calculated according to the aspect ratio K = S / h of the pattern interval S and the pattern height h in the pattern of a predetermined shape formed on the substrate, An interlayer insulating film forming step of forming an interlayer insulating film on the substrate with the optimum film thickness T so as to cover a pattern;
A method of manufacturing a semiconductor device, comprising: a planarization step of performing a reflow planarization by heat-treating an interlayer insulating film on a substrate.   2. The semiconductor device manufacturing method according to claim 1, wherein the optimum film thickness T is T = 1.5 h when K <3 and T = h × (K−1.5) when K = 3-10. Method.   In the case where the pattern has a pattern interval that satisfies K> 10, an inter-pattern adjusting step for adjusting K ≦ 10 by forming a dummy pattern between the patterns that satisfies K> 10 is further performed before the interlayer insulating film forming step. The manufacturing method of the semiconductor device of Claim 1 or 2 containing.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the region where the dummy pattern is formed is a region where an active element is disposed.   The optimum film thickness T is such that the flatness H = a / b × 100, which is the ratio of the lowest height a to the highest height b of the surface of the interlayer insulating film from the substrate, is 90% or more. The manufacturing method of the semiconductor device as described in any one of Claims 1-4.   The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is a BPSG film or a PSG film.   The method for manufacturing a semiconductor device according to claim 1, wherein the interlayer insulating film is formed by a chemical vapor deposition method.   The method for manufacturing a semiconductor device according to claim 1, further comprising a thinning step of thinning the interlayer insulating film to a predetermined thickness after the planarization step.

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