TW533542B - Manufacturing method of damascene copper wire - Google Patents

Abstract

The present invention provides a manufacturing method of damascene copper wire, which comprises first providing a semiconductor substrate having a surface formed thereon a dielectric layer which has a trench; then, forming a diffused barrier layer in the trench and using an electro-chemical depositing method to form a copper layer filled in the trench; next, forming a nucleation layer on the surface of the copper layer to provide nucleation sites for the copper layer; and making the copper layer nucleate and crystallize from the nucleation sites, thereby forming a copper layer with crystal. In accordance with the manufacturing method of the present invention, it is able to make the copper crystal structure more complete and fine, thereby solving the problem of having defects on the surface of copper wire.

Description

533542 V. Description of the invention (1) The present invention relates to a semiconductor (semicon (Juctor) product ", (integrated circuits; ICS) process technology, especially two types of damascene copper line (damascene copper line) manufacturing method, At-mounting makes the crystal structure of copper metal more complete and dense, so as to solve the problem of excessive surface defects on wires. 'The copper wire, which is used to transmit telecommunications, is indispensable for any electronic component. The same is true for circuit components. Each component must be connected as an electrical connection in order to achieve what it wants to achieve. In the multi-layer interconnection process, in addition to making the conductor patterns of each layer, the contact via ) To be used as a communication channel between the component contact area and the conductors of the disk or between the multiple layers of conductors. Furthermore, with the integration of the conductors: the degree of accumulation continues to increase, and the size of the circuit design is gradually reduced to 0 1 8, down , A damascene Cu process capable of simultaneously forming a trench-to-contact hole in a dielectric material by etching, and then filling it with a copper metal material It is the current mainstream. The following is a cross-sectional view of the process of forming a mosaic copper wire shown in Figures 1A to 1C to explain one of the conventional techniques. First, please refer to Figure S1A, the symbol 1 () in the figure Representing the bottom of the semiconductor, the above-mentioned 2 conductors / Λ10 and 8 form an intermetal dielectric layer (12: d: e ^ ctric) 12. Next, a damascene trench 15 is formed at a predetermined position of the intermetal dielectric layer 12. Then, a diffusion barrier layer (·, ·,… ^ ^ vairtusion barrier 1 ayer) is formed. 14 ° Secondly, referring to FIG. 1B, an electrochemical deposition method (electro-chemicai deP0sition; ECD) is used to form a Copper metal layer

533542

16, because this copper metal layer 16 is similar to amorphous (post 〇1_ 灿 〇1 ^), it must be tempered at 200 ~ 300 ° C and then cracked Annealing was performed for about 30 minutes to perform a copper metal nucleation crystallization procedure. Then, referring to FIG. Ic, the traditional chemical mechanical polishing method = effllcal mechanical polishing (CMp) is used to planarize the copper metal sound 16 to leave the copper metal located in the above-mentioned trench 15 as a ^ Copper wire 1 6 a. However, the conventional technology only provides the nucleation site by the diffusion barrier layer. Therefore, the crystal structure of the above-mentioned embedded copper wire 16a is not complete and dense.

In the case that the copper wire gradually shrinks, there are still many defects, such as damage (colonosn), elimination, holes, etc. on the surface of the copper wire. ). The inventor has found that, according to the manufacturing method described in the above-mentioned conventional technique, each piece of copper wire on a circle has, for example, 753 defects. In view of this, the object of the present invention is to provide a method for manufacturing embedded copper wires with a narrow line width, so that the crystal structure of copper metal is more complete and dense, thereby solving the problem of excessive surface defects of the copper wires.

According to the above object, the present invention provides a method for manufacturing a mosaic copper wire, including the following steps: (a) providing a semiconductor substrate having a dielectric layer on its surface, and the dielectric layer is formed with a trench; (b) using electrochemical Forming a copper metal layer filled with the above-mentioned trenches by chemical deposition method; (c) forming a crystal nucleation layer on the surface of the copper metal u layer to provide the nucleation sites of the copper metal layer ); And (d) nucleating and crystallizing the copper metal layer from the nucleation site to form a

533542 V. Description of the invention (3) Copper metal layer of crystal Furthermore, the above may further include a diffusion barrier formed by the above, and the above layer may be a nitrided layer. Furthermore, the above layers may use chemistry. Furthermore, the above-mentioned layers may further include and after that, more copper-clad copper wires may be included. For the purpose of understanding the present invention, the following is specifically described as follows: The method of manufacturing a damascene copper wire, wherein step (b) is a step of forming a tantalum nitride layer on the bottom surface and the sidewall of the trench, for example. The method of manufacturing copper wires, wherein the crystal nucleation layer is a nitrided layer, the oxynitride layer or copper silicide, the method of manufacturing embedded copper wires, wherein the crystal nucleation rolling phase deposition method is 350 ~ 40 0 . (: Formed at a temperature. A method for manufacturing an inlaid copper wire, wherein step (d) is subjected to a thermal tempering process at a temperature of 2? To 3? C, including a planarization step to leave a trench. The inlays: 2 The purpose, characteristics, and advantages can be more clearly described in the preferred embodiment, and in conjunction with the attached drawings, a brief description of the drawings is given in detail: / / Figure ~ s1G is based on f Known technology-a schematic cross-sectional view of the process of forming the inlaid copper wire. The green guide = 2A to 2D is a schematic cross-sectional view of the process of forming the inlaid steel twilight line according to the embodiment of the present invention. Explanation of the eight outline guide symbols

533542

V. Description of the invention (4) 10, 100 ~ semiconductor substrate; 12, 20 ~ intermetal dielectric layer 14, 140 ~ diffusion barrier layer; 15, 150 ~ trench; 16, 160 ~ copper metal layer; 160a ~ A copper metal layer with a crystal; and 16a, 160b ~ a damascene copper wire. EXAMPLES The following is a cross-sectional view of a process for forming a mosaic copper wire shown in FIGS. 2A to 2D to describe a preferred embodiment of the present invention in more detail. First, please refer to FIG. 2A. The symbol 100 in this figure represents, for example, a semiconductor substrate 100 composed of white silicon, T. " ", and a plurality of semiconductor substrates 100 formed as described above. Semiconductor elements such as transistors, capacitors and resistors. A low dielectric material made of, for example, an organic material is formed on the semiconductor substrate 100 to serve as an inter-metal dielectric 120. Next, a conventional photolithography process and an etching process are used to form a damascene trench 150 at a predetermined position of the intermetallic dielectric layer 120. Then, for example, low pressure chemical vapor deposition (CVD) or physical vapor deposition (PVD) is used to form a nitride group layer as a diffusion barrier 1 ayer) 140 ° Secondly, please refer to FIG. 2B, use an electro-chemical deposition (ECD) method, and form a copper metal layer 16 with a suitable current density, a suitable electro-mineral fluid, and an additive.

0503-5 329TWF; TSMC2000-0009 Jessica.ptd Page 7 533542 V. Description of the invention (5) Here the copper metal layer 16 is similar to amorphous (am〇rph〇us), and then, the CVD method is used again at 350 Deposited on the surface of the copper metal layer 16 () for several seconds to several tens of seconds at a temperature of ~ 400 C to form a crystal nucleation layer 180 for providing a large number of nucleation sites of the copper metal layer 16 ( nucleation sites) to facilitate subsequent nucleation and crystallization steps. The crystal nucleation layer is, for example, a nitride group layer (TaNJ, nitride nitride layer (3)), an oxynitride layer (SiOxNy), or a copper silicide layer ( CuSU, etc. Then, a thermal annealing process is performed at a temperature of 200 to 300 ° C for about 30 minutes to perform a copper metal nucleation and crystallization process. After that, a layer is formed to form a layer having a shape as shown in the figure. A complete and dense crystalline copper metal layer 16a. Then, referring to FIG. 2D, use conventional chemical mechanical polishing (CMP) to perform copper-gold 1 > 60 Flattening to leave copper located at the above-mentioned trench 15 The metal is regarded as a watch-type copper wire 160b. Tian Invention Features and Effects The present invention provides a method for manufacturing a mosaic copper wire. A crystal nucleation layer is deposited on the surface of a copper metal layer to increase the nucleation level. In addition to the barrier diffusion layer, a crystal nucleation layer can provide a large nuclei position, which can make the growth of the copper metal crystal structure more dense-so as to solve the above-mentioned problem of excessive surface defects of the copper wire. 70 $ This inventor It is found that according to the method described in the embodiment of the present invention, there are only 64 defects in the copper wires on each wafer, for example, wm 0503-5329TWF; TSMC2000-0009; jessica.ptd 533542 5. Description of the invention ( 6) The invention has a greatly improved effect on the corrosion, disappearance, holes, etc. of the surface of narrow copper wires. Although the present invention has been disclosed above in the preferred embodiment, it is not intended to limit the present invention. Anyone familiar with this technology However, without departing from the spirit and scope of the present invention, modifications and retouching can be made. Therefore, the protection scope of the present invention shall be defined as the scope of the appended patent application as defined below. .

0503-53 29TWF; TSMC2000-0009 Jessica.ptd page 9

Claims (1)

533542 VI. Application for patent scope 1. Manufacturing of a mosaic copper wire (a) Providing a semiconductor with a dielectric layer on the surface includes the following steps: The electrical layer is formed with a trench; ~ and the above dielectric (b) uses electrochemical Formation of a deposition method-layer; copper metal filling the trench (c) formed on the surface of the copper metal layer-crystal nucleation nuclea :: 〇n layer) 'to provide the above copper gold (nucleation sites); And (d) performing the copper metal layer from the nucleation site to form a copper metal layer having crystals. Wind core ~ said, 2. The inlaid copper conductive method as described in item 丨 of the patent application scope, wherein before the step (b) further includes the step of forming a diffusion barrier layer on the above === side wall. The bottom surface of Dan ~ and the pushing method as described in item 2 of the scope of the patent application, wherein the diffusion barrier layer is a nitride button. Manufacture of 5 V wires 4. The stomach-embedded copper conductor method described in item i of the patent application scope, wherein the crystal nucleation layer is a nitrided button layer. The method of manufacturing a "type copper wire" according to item 1 of the I, W patent scope, wherein the crystal nucleation layer is a silicon nitride layer. Mk 6 · Inlaid copper according to item 1 of the patent scope Method, wherein the above-mentioned crystal nucleation layer is an oxynitride layer. The method of making & • 7. It is a Shixihua copper layer. ^ 乂 8 · Inlaid copper according to the scope of patent application No. 4, 5, 6, or 7 0503-5329TWF; TSMC2000-0009; jessica.ptd 533542 The method of manufacturing a lead product is a method in which the crystal nucleation layer is formed at a temperature of 350 to 400 ° C by chemical vapor deposition. / b, 9 · Method 2 of the inlaid copper wire as described in item 丨 of the patent application scope, wherein step (d) further includes a heat-tempering process at a temperature of 200 to 300 t. Also known is a method for manufacturing a mosaic copper wire, including the following steps: (a) providing a semiconductor substrate; (b) forming a dielectric layer on the surface of the semiconductor substrate, and forming an upper eight electrical layer with a Trench; (c) forming a diffusion barrier layer on the side wall and the bottom surface of the trench; (d) forming a copper metal servant filling the trench by an electrochemical deposition method (6) forming the surface of the copper metal layer A crystal nucleation layer to provide the copper metal layer nucleation position; (f) nucleating and crystallizing the copper metal layer from the nucleation position to form a copper metal layer having crystals; (g) applying heat Tempering process; and (h) planarizing the copper metal layer with crystals by using a chemical mechanical polishing method to leave a mosaic copper wire in the trench. 11 · The method of making an inlaid copper wire as described in item 10 of the scope of the patent application, wherein the diffusion barrier layer is a vaporization group layer. 1 2 · The method for manufacturing a mosaic copper wire as described in item No. 0 of the patent application scope, wherein the crystal nucleation layer is a nitrided button layer. 1 3 · Manufacturing of inlaid copper wires as described in item 10 of the scope of patent application