JP2010154449A - Oscillation circuit, integrated circuit device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an oscillation circuit, integrated circuit device and electronic apparatus, in which a clock signal can be generated by selecting a desired frequency from among a plurality of frequencies. <P>SOLUTION: The oscillation circuit includes: first to n-th inverting circuits INV1-INVn including a first inverting circuit to the input of which one terminal of a capacitor 10, one terminal of a first resistor 20 and one terminal of a second resistor 30 are connected, and the n-th (n is an even number of ≥2) inverting circuit to the output of which the other terminal of the capacitor 10 is connected; a first drive inverting circuit DR1 to which the output of the n-th inverting circuit INVn is input, for driving the other terminal of the first resistor 20; and a second drive inverting circuit DR2, to which the output of the n-th inverting circuit INVn is input, for driving the other terminal of the second resistor 30. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an oscillation circuit, an integrated circuit device, an electronic device, and the like.

In an electronic device (such as a portable information terminal) including a CR oscillation circuit for generating a clock signal, there is a problem of switching and operating a plurality of clock frequencies. For example, Patent Document 1 discloses a technique for dividing a maximum frequency clock signal to obtain a plurality of clock frequencies. However, this method is limited to a frequency that is an integral number of the highest frequency, and there is a problem that the frequency cannot be freely selected. Further, there is a method of providing a number of CR oscillation circuits corresponding to a necessary frequency, but there is a problem that the number of elements and the number of terminals are increased.
JP 09-201045 A

  According to some aspects of the present invention, it is possible to provide an oscillation circuit, an integrated circuit device, and an electronic device that can generate a clock signal by selecting a desired frequency from a plurality of frequencies.

  One embodiment of the present invention is an oscillation circuit that outputs a clock signal, and includes a first inversion circuit in which one end of a capacitor, one end of a first resistance element, and one end of a second resistance element are connected to its input The first to nth inverting circuits having the nth (n is an even number of 2 or more) inverting circuit connected to the output of the other end of the capacitor, and the output of the nth inverting circuit are input. The first driving inversion circuit for driving the other end of the first resistance element and the second driving for driving the other end of the second resistance element by inputting the output of the nth inversion circuit. And an inverting circuit.

  According to one embodiment of the present invention, it is possible to select one of two set frequencies and output a clock signal. Furthermore, the number of elements and the number of terminals can be reduced as compared with a method in which an oscillation circuit is provided for each desired frequency. In addition, the frequency can be set freely and the power consumption can be further reduced as compared with a method of dividing the highest frequency to obtain a desired frequency.

  In the aspect of the invention, the clock signal having a variable frequency may be output by setting the first and second driving inversion circuits to the enable state or the disenable state.

  In this way, it is possible to select the desired frequency by controlling the driving inversion circuit by the control signal from the control circuit.

  In one aspect of the present invention, when the resistance value of the first resistance element is set larger than the resistance value of the second resistance element, and the frequency of the clock signal is set to the first frequency, When the first driving inversion circuit is enabled and the frequency of the clock signal is set to a second frequency higher than the first frequency, the second driving inversion circuit is enabled. The state may be set.

  In this way, the resistance values of the two resistance elements can be set to values corresponding to the desired frequencies, respectively, and either one of the two set frequencies can be selected to output the clock signal. .

  In one aspect of the present invention, when the frequency of the clock signal is set to a third frequency higher than the second frequency, both the first and second driving inversion circuits are set to an enabled state. May be.

  In this way, it is possible to select one of the three frequencies and output the clock signal without providing the third resistance element.

  In one aspect of the present invention, when the frequency of the clock signal is set to a first frequency, one of the first and second driving inversion circuits is set to an enabled state, When the frequency of the clock signal is set to a third frequency higher than the first frequency, both the first and second driving inversion circuits may be set to an enabled state.

  In this way, one of the two frequencies, one frequency and a higher frequency, can be selected to output the clock signal.

  In one embodiment of the present invention, a selector for selecting either one of the output of the first driving inversion circuit and the output of the second driving inversion circuit and outputting the clock signal. May be included.

  In this way, by controlling the selector with the control signal, it is possible to select a desired frequency from a plurality of set frequencies and output the clock signal.

  In one embodiment of the present invention, the clock signal may be output based on an output of any one of the first to nth inverting circuits.

  In this way, a clock signal can be output by selecting a desired frequency from a plurality of set frequencies without providing a selector.

  Another aspect of the present invention is the oscillation circuit according to any one of the above, a first terminal for connecting one end of the capacitor, one end of the first resistance element, and one end of the second resistance element; A second terminal for connecting the other end of the capacitor, a third terminal for connecting the other end of the first resistive element, and a second terminal of the second resistive element. And a fourth terminal of the integrated circuit device.

  According to another aspect of the present invention, a clock signal having a desired frequency can be selected and output from a plurality of set frequencies, so that the clock frequency can be optimized according to conditions.

  Another aspect of the present invention relates to an electronic apparatus including the integrated circuit device described above.

  Hereinafter, preferred embodiments of the present invention will be described in detail. The present embodiment described below does not unduly limit the contents of the present invention described in the claims, and all the configurations described in the present embodiment are indispensable as means for solving the present invention. Not necessarily.

1. First Configuration Example of Oscillation Circuit FIG. 1 shows a first configuration example of the oscillation circuit of this embodiment. This configuration example is an oscillation circuit that outputs a clock signal CLK and includes first and second inversion circuits INV1 and INV2 (first to nth inversion circuits INV1 to INVn (n is an even number of 2 or more) in a broad sense). ) And first and second driving inversion circuits DR1 and DR2. The oscillation circuit of this configuration example can output the clock signal CLK based on the output of the inverting circuits INV1 and INV2 (INV1 to INVn) or the first and second driving inverting circuits DR1 and DR2. Further, this configuration example includes a selector 40, a control signal inverting inverter SIV, and an output buffer circuit OBF. Note that the oscillation circuit of the present embodiment is not limited to the configuration shown in FIG. 1, and various modifications may be made such as omitting some of the components, replacing them with other components, and adding other components. Is possible.

  In this configuration example, the inverting circuits INV1 and INV2 (INV1 to INVn) are composed of inverters, but may be composed of NAND circuits or other logic circuits (logic circuits, logic gates, etc.).

  One end of the capacitor 10, one end of the first resistance element 20, and one end of the second resistance element 30 are connected to the input of the first inverting circuit INV1. The other end of the capacitor 10 is connected to the output of the second inversion circuit INV2 (in a broad sense, the nth inversion circuit INVn).

  The first driving inversion circuit DR1 receives the output of the second inversion circuit INV2 (in a broad sense, the nth inversion circuit INVn) and drives the other end of the first resistance element 20. The second driving inversion circuit DR2 receives the output of the second inversion circuit INV2 (nth inversion circuit INVn in a broad sense) and drives the other end of the second resistance element 30.

  The capacitor 10 and the first and second resistance elements 20 and 30 are provided inside an integrated circuit device including the inverter circuits INV1 and INV2 (INV1 to INVn) and the first and second driving inverter circuits DR1 and DR2. Alternatively, it may be provided outside.

  In this configuration example, the first and second driving inversion circuits DR1 and DR2 are set to the enable state or the disenable state by the control signal SEL from the control circuit, thereby outputting the clock signal CLK having a variable frequency. . Specifically, the resistance value of the first resistance element 20 is set larger than the resistance value of the second resistance element 30. When the frequency of the clock signal CLK is set to the first frequency f1, the first driving inversion circuit DR1 is set to the enable state and set to the second frequency f2 higher than the first frequency f1. In this case, the second driving inversion circuit DR2 is set to the enable state.

  More specifically, when the frequency of the clock signal CLK is set to the first frequency f1, the control signal SEL is set to the H level (high potential level). At this time, the first driving inversion circuit DR1 is set to the enabled state, and the second driving inversion circuit DR2 is set to the disabled state. On the other hand, when the second frequency f2 is set, the control signal SEL is set to the L level (low potential level). At this time, DR1 is set to the disabled state, and DR2 is set to the enabled state.

  Based on the control signal SEL, the selector 40 selects either one of the output of the first driving inversion circuit DR1 and the output of the second driving inversion circuit DR2. Based on the signal selected by the selector 40, the output buffer circuit OBF outputs a clock signal CLK.

  The oscillation circuit of FIG. 1 operates as follows. The case where the control signal SEL is set to the H level, that is, the case where the first driving inversion circuit DR1 is set to the enable state will be described. When the input node N4 of the first inverting circuit INV1 is at L level, the output node N3 of the second inverting circuit INV2 is at L level and the output node N1 of the first driving inverting circuit DR1 is at H level. Then, a current flows from N1 to N4 through the first resistance element 20. This current increases the potential of N4 while charging the capacitor 10, and INV1 is inverted when the potential of N4 becomes higher than the logical threshold value of INV1. When INV1 is inverted, N3 becomes H level and N1 becomes L level. Therefore, a current flows from N4 to N1, and the capacitor 10 is discharged. When the potential of N4 drops and becomes lower than the logical threshold value of INV1, INV1 is inverted, N3 becomes L level and N1 becomes H level, and charging of the capacitor 10 starts again. In this way, oscillation is performed at a constant frequency by repeating charging and discharging. In this case, since the second driving inversion circuit DR2 is in a disabled state, its output node N2 becomes high impedance (Hi-Z) and does not affect the above operation.

  The time required for charging or discharging the capacitor 10 is substantially determined by the RC time constant, that is, the product of the resistance value and the capacitance value. Specifically, for example, when the resistance value of the first resistance element 20 is RA1 and the capacitance value of the capacitor 10 is CA, the period T1 corresponding to the first frequency f1 of CLK is approximately T1 = 2 × RA1. X CA is given. The first frequency f1 is given by the reciprocal of T1, that is, f1 = 1 / T1.

  Although the case where DR1 is set to the enable state has been described above, the second frequency f2 is determined in the same manner as described above also when DR2 is set to the enable state. Specifically, when the resistance value of the second resistance element 30 is RA2, the period T2 corresponding to f2 is approximately given by T2 = 2 × RA2 × CA, and f2 is given by f2 = 1 / T2. . Accordingly, when RA1> RA2, T1> T2 and f1 <f2.

  FIG. 2 shows an example of a signal waveform of the first configuration example of the oscillation circuit. FIG. 2 shows the waveforms of the voltages V1, V2, and V4 of the nodes N1, N2, and N4 and the clock signal CLK when the first driving inversion circuit DR1 is set to the enable state. Hereinafter, the operation of the oscillation circuit of this configuration example will be described with reference to FIG.

  First, assuming that the input voltage of V4, that is, INV1, is at L level as indicated by A1, the output voltage of V1, that is, DR1, becomes H level, as indicated by B1. In this state, current flows from N1 to N4 through the first resistance element 20 to charge the capacitor 10, so that the voltage of V4 gradually increases as indicated by A2. When V4 reaches the logical threshold value of INV1, INV1 is inverted, and INV2 is also inverted, and N3 transitions from the L level to the H level. For this reason, V4 rises steeply as indicated by A3 to A4. On the other hand, at this time, V1 transitions from the H level to the L level as indicated by B2 to B3. In this state, current flows from N4 to N1 through the first resistance element 20 to discharge the capacitor 10, so that V4 gradually decreases as indicated by A5. When V4 reaches the logical threshold value of INV1, INV1 is inverted, and INV2 is also inverted, and N3 transitions from the H level to the L level. For this reason, V4 falls steeply as shown from A6 to A7. Then, charging of the capacitor 10 is started again, and A1 to A7 are repeated.

  As can be seen from the waveform of V4 in FIG. 2, the period T is given by the sum of the charging time tr and the discharging time tf. Both the charging time tr and the discharging time tf are substantially determined by the RC time constant, that is, the product of the resistance value and the capacitance value. For example, when the resistance value of the first resistance element 20 is RA1 and the capacitance value of the capacitor 10 is CA, the period T1 is given by approximately T1 = 2 × RA1 × CA. In an actual oscillation circuit, it is necessary to obtain the period T1 in consideration of the parasitic capacitance included in the gate of the transistor used. According to a more detailed circuit simulation, for example, when RA1 = 120 kΩ and CA = 10 pF, T1 = 2.83 μs.

  FIG. 3 shows a configuration example of the driving inverting circuits DR1 and DR2. This configuration example includes P-type transistors TP1 and TP2, N-type transistors TN1 and TN2, and an inverter IVA.

  When the control signal SEL is set to H level (high potential level), TP1 and TN2 are turned on, so that TP2 and TN1 operate as normal inverters. This state can be enabled. On the other hand, when the control signal SEL is set to L level (low potential level), TP1 and TN2 are turned off, so that the output QA becomes high impedance (Hi-Z) regardless of the level of the input IA. This state can be disabled.

  Note that the driving inverter circuit of the present embodiment is not limited to the configuration shown in FIG. 3, and various components such as omitting some of the components, replacing them with other components, and adding other components. Variations are possible.

  As described above, according to the first configuration example of the oscillation circuit shown in FIG. 1, the resistance values of the first and second resistance elements 20 and 30 are set to values corresponding to desired frequencies, respectively. By controlling with the signal SEL, one of the two set frequencies can be selected and a clock signal can be output. Furthermore, the number of elements and the number of terminals can be reduced as compared with the method of providing an oscillation circuit for each desired frequency. Further, there are advantages in that the frequency can be set freely and the power consumption can be reduced as compared with the method of dividing the highest frequency to obtain a desired frequency.

  In this configuration example, two resistance elements and two driving inversion circuits are provided, but three or more resistance elements and a corresponding number of driving inversion circuits may be provided. In this way, a desired frequency can be selected from three or more frequencies and a clock signal can be output.

2. Second Configuration Example of Oscillation Circuit FIG. 4 shows a second configuration example of the oscillation circuit of this embodiment. This configuration example includes first and second inversion circuits INV1 and INV2 (in a broad sense, first to nth inversion circuits INV1 to INVn (n is an even number of 2 or more)), and first and second inversions for driving. Circuits DR1 and DR2 and an output buffer circuit OBF are included.

  One end of the capacitor 10, one end of the first resistance element 20, and one end of the second resistance element 30 are connected to the input of the first inverting circuit INV1. The other end of the capacitor 10 is connected to the output of the second inversion circuit INV2 (in a broad sense, the nth inversion circuit INVn).

  The first driving inversion circuit DR1 receives the output of the second inversion circuit INV2 (in a broad sense, the nth inversion circuit INVn) and drives the other end of the first resistance element 20. The second driving inversion circuit DR2 receives the output of the second inversion circuit INV2 (nth inversion circuit INVn in a broad sense) and drives the other end of the second resistance element 30. DR1 and DR2 are set to an enabled state or a disabled state by control signals SEL1 and SEL2, respectively. Note that the oscillation circuit of the present embodiment is not limited to the configuration shown in FIG. 4, and various modifications may be made such as omitting some of the components, replacing them with other components, and adding other components. Is possible.

  In this configuration example, the inverting circuits INV1 and INV2 (INV1 to INVn) are composed of inverters, but may be composed of NAND circuits or other logic circuits (logic circuits, logic gates, etc.).

  The capacitor 10 and the first and second resistance elements 20 and 30 are provided inside an integrated circuit device including the inverter circuits INV1 and INV2 (INV1 to INVn) and the first and second driving inverter circuits DR1 and DR2. Alternatively, it may be provided outside.

  In FIG. 4, the clock signal CLK is output based on the output of the second inverting circuit INV2, but the clock signal CLK may be output based on the output of the first inverting circuit INV1. In the case of including n number of inverter circuits, the clock signal CLK may be output based on the output of any one of the first to nth inverter circuits INV1 to INVn.

  In the second configuration example, the first and second driving inversion circuits DR1 and DR2 are set to the enable state or the disenable state by the control signals SEL1 and SEL2 from the control circuit, so that the clock signal having a variable frequency is set. Output CLK. Specifically, when the resistance value RA1 of the first resistance element 20 is set larger than the resistance value RA2 of the second resistance element 30, and the frequency of the clock signal CLK is set to the first frequency f1, The first driving inversion circuit DR1 is set to the enable state. When the second frequency f2 higher than the first frequency f1 is set, the second driving inversion circuit DR2 is set to the enable state. Further, when the frequency of the clock signal CLK is set to the third frequency f3 higher than the second frequency f2, the first and second driving inversion circuits DR1 and DR2 are both set to the enable state.

  More specifically, for example, when the frequency of the clock signal CLK is set to f1, the first control signal SEL1 is set to the H level, and the first driving inversion circuit DR1 is set to the enable state. Further, the second control signal SEL2 is set to the L level, and the second driving inversion circuit DR2 is set to the disabled state. As described above, the period T1 corresponding to f1 at this time is substantially given by T1 = 2 × RA1 × CA.

  When the frequency of the clock signal CLK is set to f2, SEL1 is set to H level and DR1 is set to an enable state. In addition, SEL2 is set to L level and DR2 is set to a disable state. As described above, the period T2 corresponding to f2 at this time is approximately given by T2 = 2 × RA2 × CA.

  Further, when the frequency of the clock signal CLK is set to f3, both SEL1 and SEL2 are set to the H level, and both DR1 and DR2 are set to the enable state. In this case, the capacitor 10 is charged or discharged through both the first and second resistance elements 20 and 30. Therefore, when the combined resistance value obtained by connecting the first and second resistance elements 20 and 30 in parallel is R12, the period T3 corresponding to f3 is given by approximately T3 = 2 × R12 × CA. Here, the combined resistance value R12 is given by R12 = RA1 × RA2 / (RA1 + RA2) when the resistance value of the first resistance element 20 is RA1 and the resistance value of the second resistance element 30 is RA2. When RA1> RA2 is set, RA1> RA2> R12, so that T1> T2> T3, and therefore f1 <f2 <f3.

  Furthermore, according to the second configuration example, when the frequency of the clock signal CLK is set to the first frequency f1, one of the first and second driving inversion circuits DR1 and DR2 is enabled. Set to When the third frequency f3 higher than f1 is set, the first and second driving inversion circuits DR1 and DR2 are both set to the enabled state.

  Specifically, when the frequency of the clock signal CLK is set to f1, SEL1 may be set to H level, SEL2 may be set to L level, or SEL1 is set to L level and SEL2 is set to H level. May be set. In this case, one of DR1 and DR2 is set to the enabled state. On the other hand, when the frequency of the clock signal CLK is set to f3, both SEL1 and SEL2 are set to the H level, and both DR1 and DR2 are set to the enable state. As described above, when the combined resistance value obtained by connecting the first and second resistance elements 20 and 30 in parallel is R12, the period T3 corresponding to f3 is given by approximately T3 = 2 × R12 × CA. Therefore, when the frequency of CLK is set to f1, regardless of which of DR1 and DR2 is set to the enabled state, R12 <RA1 and R12 <RA2, so that f3> f1.

  As described above, according to the second configuration example of the oscillation circuit shown in FIG. 4, the resistance values of the first and second resistance elements 20 and 30 are set to appropriate values, and the two control signals SEL1, By controlling with SEL2, it is possible to select one of a maximum of three frequencies and output a clock signal. Furthermore, the number of elements can be reduced as compared with a method in which an oscillation circuit is provided for each desired frequency. Further, there are advantages in that the frequency can be freely selected and the power consumption can be reduced as compared with the method of dividing the highest frequency to obtain a desired frequency.

  In this configuration example, two resistance elements and two driving inversion circuits are provided. However, three or more resistance elements, a corresponding number of driving inversion circuits, and a corresponding number of control signals are provided. It may be provided. In this way, a desired frequency can be selected from a larger number of frequencies.

3. Integrated Circuit Device FIG. 5 shows a configuration example of an integrated circuit device including the oscillation circuit of this embodiment. The integrated circuit device 200 of FIG. 5 includes the oscillation circuit 100 of the present embodiment, a first terminal P1 for connecting one end of the capacitor 10, one end of the first resistance element 20, and one end of the second resistance element 30; The second terminal P2 for connecting the other end of the capacitor 10, the third terminal P3 for connecting the other end of the first resistance element 20, and the other end of the second resistance element 30 are connected. And a fourth terminal P4. The capacitor 10 and the first and second resistance elements 20 and 30 can also be provided inside the integrated circuit device.

  Further, the integrated circuit device 200 of this configuration example includes a control circuit 110, a PLL (Phase-Locked Loop) circuit (clock generation circuit in a broad sense) 130, a logic circuit 140, and an analog circuit 150. The control circuit 110 includes a register 120.

  In the integrated circuit device 200 of this configuration example, the control circuit 110 outputs the control signals SEL1 and SEL2 to the oscillation circuit 100 based on the data stored in the register 120. The oscillation circuit 100 sets the frequency of the clock signal CLK to any one of the first to third frequencies f1 to f3 in accordance with the control signals SEL1 and SEL2, and outputs it. The PLL circuit 130 further generates a desired clock signal based on the clock signal CLK and supplies it to the logic circuit 140 and the analog circuit 150.

  As described above, according to the integrated circuit device 200 of this configuration example, a clock signal having a desired frequency can be selected and generated from a plurality of set frequencies. Can be optimized. Furthermore, the number of elements and the number of terminals can be reduced as compared with the method of providing an oscillation circuit for each desired frequency. Further, there are advantages in that the frequency can be freely selected and the power consumption can be reduced as compared with the method of dividing the highest frequency to obtain a desired frequency.

4). Electronic Device FIG. 6 shows an example of an electronic device (portable information terminal) including the integrated circuit device of this embodiment. Note that the electronic device of the present embodiment is not limited to a portable information terminal, and may be a mobile phone, a PDA, or the like.

  6 includes a transmission / reception circuit (an integrated circuit device in a broad sense) 200 including an oscillation circuit of the present embodiment, a CPU (Central Processing Unit) 210, a display unit 220, an operation input unit 230, a memory unit 240, an antenna. 250. The transmission / reception circuit 200 demodulates a signal received by the antenna 250 and outputs the demodulated signal to the CPU 210, and modulates data from the CPU 210 and transmits it from the antenna 250. Based on the operation information from the operation input unit 230, the CPU 210 exchanges data with the transmission / reception circuit 200 and the memory unit 240, and performs necessary data processing. The display unit 220 displays data from the CPU 210.

  Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Accordingly, all such modifications are intended to be included in the scope of the present invention. For example, a term described together with a different term having a broader meaning or the same meaning at least once in the specification or the drawings can be replaced with the different term anywhere in the specification or the drawings. Further, the configurations and operations of the integrated circuit device and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

1 is a first configuration example of an oscillation circuit. An example of a signal waveform. 2 shows a configuration example of a driving inverting circuit. 2 shows a second configuration example of an oscillation circuit. 2 shows a configuration example of an integrated circuit device. An example of an electronic device.

Explanation of symbols

INV1, INV2 first and second inverting circuits,
DR1, DR2 first and second drive inverters, SIV control signal inverters,
OBF output buffer circuit, SEL control signal, CLK clock signal,
10 capacitors, 20 first resistance elements, 30 second resistance elements,
40 selector, 100 oscillation circuit, 110 control circuit, 120 register,
130 PLL circuit, 140 logic circuit, 150 analog circuit,
200 integrated circuit device, 210 CPU, 220 display unit, 230 operation input unit,
240 memory, 250 antenna

Claims (9)

An oscillation circuit that outputs a clock signal,
A first inverting circuit in which one end of the capacitor, one end of the first resistance element, and one end of the second resistance element are connected to its input; and an nth (n is the other end of the capacitor connected to its output) First to n-th inverting circuits having an even number of inverting circuits of 2 or more;
A first driving inversion circuit that receives the output of the nth inversion circuit and drives the other end of the first resistance element;
An oscillation circuit comprising: a second driving inversion circuit that receives the output of the nth inversion circuit and drives the other end of the second resistance element. In claim 1,
An oscillation circuit characterized in that the clock signal having a variable frequency is output by setting the first and second driving inversion circuits to an enable state or a disenable state. In claim 2,
A resistance value of the first resistance element is set larger than a resistance value of the second resistance element;
When the frequency of the clock signal is set to the first frequency, the first driving inversion circuit is set to an enabled state,
An oscillation circuit, wherein when the frequency of the clock signal is set to a second frequency higher than the first frequency, the second driving inversion circuit is set to an enable state. In claim 3,
When the frequency of the clock signal is set to a third frequency higher than the second frequency, the first and second driving inversion circuits are both enabled. circuit. In claim 2,
When the frequency of the clock signal is set to the first frequency, one of the first and second driving inversion circuits is set to an enabled state,
When the frequency of the clock signal is set to a third frequency higher than the first frequency, the first and second driving inversion circuits are both enabled. circuit. In any one of Claims 1 thru | or 5,
An oscillator comprising: a selector for selecting one of the output of the first driving inversion circuit and the output of the second driving inversion circuit and outputting the clock signal. circuit. In any one of Claims 1 thru | or 5,
An oscillation circuit, wherein the clock signal is output based on an output of any one of the first to n-th inversion circuits. An oscillation circuit according to any one of claims 1 to 7,
A first terminal for connecting one end of the capacitor, one end of the first resistance element, and one end of the second resistance element;
A second terminal for connecting the other end of the capacitor;
A third terminal for connecting the other end of the first resistance element;
An integrated circuit device comprising: a fourth terminal for connecting the other end of the second resistance element.   An electronic apparatus comprising the integrated circuit device according to claim 8.

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