JPS63313909A - Cr oscillating circuit - Google Patents

Abstract

PURPOSE:To stabilize a circuit operation and to stabilize an oscillation frequency by providing a constant voltage generation circuit, which generates two reference voltages with different potentials by splitting a resistance, two voltage comparators, an output selection circuit to invert the logical level of an output signal, and a CR time constant circuit. CONSTITUTION:The terminal voltage Vc of a capacitor C ascends like an exponential function according to the time constant of the CR time constant circuit, consisting of the capacitor C and a resistor R. In the process of this ascent, at first, the terminal voltage Vc of the capacitor C exceeds a reference voltage V2, and the output node 5 of the second voltage comparator 4 is inverted from a high level into a low level. Next, the terminal voltage Vc of the capacitor C exceeds the reference voltage V1, and the output node 3 of the first voltage comparator 2 is inverted from the high level into the low level. By repeating above-mentioned operations, an oscillation operation is performed. In this case, the two reference voltages V1, V2 are generated by splitting the resistance, and because the value of Schmidt voltage width/ power source voltage is kept constant extending over the wide range of the power source voltage, the circuit operation is stabilized, and the oscillation frequency is stabilized as well.

Description

[Detailed Description of the Invention] [Purpose of the Invention (Industrial Application Field) The present invention relates to a CRR oscillator circuit, and particularly to a CRR circuit that is integrated circuit.
The present invention relates to a Schmitt type CRR swing circuit using a MOS (insulated dart type) Schmitt circuit.

(Prior art) Conventionally, CRR swing circuits have been of a three-stage inverter type in which CMOS inverters 41 to 43 are connected in three stages and capacitors C1 and RK are connected, as shown in FIG. A Schmitt type circuit in which a CMOS Schmitt circuit 51 is connected to a capacitor C1 and a resistor R is known.

In the circuit shown in FIG. 4 above, the threshold voltage of the P-channel transistor of the 0MO8 inverter! If the power supply voltage is lower than the sum of vTHPI and the threshold voltage vTHN of the N-channel transistor (for example, about 2V), a voltage region occurs where both the P-channel transistor and the N-channel transistor are turned off, and the circuit operation becomes unstable. Unable to obtain excavation frequency.

Furthermore, in the circuit shown in FIG.
The Schmitt width of 1 is determined using the ratio of the current driving power of the MOS transistor.Since the current driving power change ratio of the P-channel transistor and the N-channel transistor differs depending on the change in the power supply voltage, the Schmitt width is determined by using the ratio of the current driving power of the MOS transistor. It has voltage dependence, and the excavation frequency changes depending on the source voltage.

(Problems to be Solved by the Invention) The present invention has been made to solve the above-mentioned problem that the oscillation frequency and the stability of circuit operation depend on the power supply voltage, so there is a large restriction on the usable voltage range. With something that
Stable excavation even at low power supply voltage, wide range! #Objective is to provide an OR excavation circuit that enables oscillation operation with little frequency fluctuation under constant voltage.

[Configuration of the Invention (Preliminary Means to Solve Problems) The OR excavation circuit of the present invention consists of a constant voltage generation circuit that generates two reference voltages with different potentials by resistor division, and a constant voltage generation circuit that generates two reference voltages with different potentials by resistor division. are respectively given as circuit thresholds, two voltage comparators waveform shape the mutually common input voltage, each output of these two voltage comparators is led as an input, and these two inputs It has an output selection circuit that switches the input selection and inverts the logic level of the output signal at the timing when each logic level of A CR that supplies the voltage at one end of the capacitor to the two voltage comparators as a common input voltage.
The main feature is that it is equipped with a time constant circuit.

(Function) The Schmitt voltage width of a Schmitt circuit consisting of two voltage comparators and an output selection circuit is determined by the voltage difference between two reference voltages, and the two reference voltages are generated by resistor division, and can be applied over a wide range. Schmitt voltage @/ under the supply voltage of
Since the value of the power supply voltage is kept constant, the circuit operation is stable and the excavation frequency is also stable. Also, since the common input voltage is compared with separate reference voltages using two voltage comparators, the OR excavation circuit can be used as a low voltage. It becomes possible to operate the oscillation with I[voltage.

(Embodiment) Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a 90R excavation circuit provided in a CMOS integrated circuit, and a capacitor C and a resistor R are externally connected to the integrated circuit. Note that capacitor C and resistor R
may be built into an integrated circuit. 1 is a constant voltage generation circuit, and a resistor R1* is connected between the vDD power supply terminal and the ground terminal.
R1 and R1 are connected in series, and two reference voltages V1 and Vt (Vl > Vl) are generated by resistance division. 2 is the reference voltage v1 and the terminal ν of the capacitor C.
A first voltage comparator that performs magnitude comparison with LIEvc, and an N-channel transistor Nl for reference voltage input;
N-channel transistor Nx for comparison voltage input and P-channel transistor l-p as current mirror load
! CMO3'Narita comparison, J5, which consists of , and its output node is set to 3. This voltage comparator 2 performs an inverter operation using the reference voltage Vl'' as a threshold, and outputs a high level (vDD power supply potential) when the comparative human power V is lower than the reference human power v1, and vice versa. A level (ground potential) is output. 4 is a second voltage ratio that makes a difference between the reference voltage v2 and the terminal voltage vc of the capacitor C, and a P-channel transistor s for inputting the reference voltage; A P-channel transistor P4 for comparison voltage input and an N-channel transistor N serving as a current mirror load.
, , N4, and is represented by a total of five output nodes. This voltage comparator 4 has a reference voltage v! ? It performs inverter operation based on the threshold value.
When the comparative human power VC is lower than the reference voltage VC, a high level is output, and in the opposite case, a low level is output. 6 is an output selection circuit which selects one of the outputs of the two voltage comparators 2.4, and a resistor R is connected between the selected output two doors and the capacitor C. In the output selection circuit 6, the output node 3 of the voltage comparator 2 passes through two stages of inverters 8 and 9 to a first analog switch (a p-channel transistor P8 and an N-channel transistor N are connected in parallel). 10, and the output node 5 of the voltage comparator 4 is connected to the two-stage inverter 11.12ff.
and is connected to one end of a second analog switch 13 (consisting of a p-channel transistor P and an N-channel transistor N). The other ends of the two analog switches 10.13 are commonly connected and then connected to the selection output two-door via the two-stage inverter 14.15f. In addition, the output terminal of the inverter 14 is connected to the two analog switches 10 and 13 correspondingly.
The output terminal of the inverter 15 is connected to the dart of the N-channel transistor N5 in the two analog switches 10.13, and the dart of the N-channel transistor N6 in the two analog switches 10. Connected to the gate of channel transistor P6.

Next, the oscillation operation of the above circuit will be explained with reference to FIG. Now, in the initial state, the output terminal of the inverter 9, the output terminal of the inverter 12, and the selection output two door in the output selection circuit 6 are each at a high level, the analog switch 13 is in the off state, and the analog switch 10 is in the on state. If there is no charge stored in the capacitor C, the terminal voltage vc of the capacitor C increases exponentially due to the time constant of the CR time constant circuit consisting of the capacitor C1 and the resistor R. During this rising process, the terminal voltage vc of the capacitor C first exceeds the reference voltage V, and the second
The output node 5 of the first voltage comparator 4 is inverted from a high level to a low level, and then the terminal voltage VC of the capacitor Cl7) exceeds the reference voltage V1 and the output node 3 of the first voltage comparator 2 is inverted from a high level to a low level. Flip to level. During this time, even if the output terminal of the inverter 12 is reversed to a low level, the second analog switch 13 remains off and the 1 selection output two door maintains a high level. Then, as described above, when the output node 3 of the first voltage comparator 2 is inverted to a low level and the output terminal of the inverter 9 becomes a low level, the selected output two door becomes a low level. This allows the first
The analog switch f101rL is turned off, and the charge on the capacitor C begins to be released toward the selected output two doors through the resistor Rt-, and the terminal voltage V of the capacitor C gradually decreases. In this lowering process, the terminal voltage vc of the capacitor C first becomes lower than the reference voltage vl, and the output node 3 of the first voltage comparator 2 is inverted to a high level, and then the terminal voltage vc of the capacitor C becomes lower than the reference voltage vl. V, the second lower
The output node 5 of the voltage comparator 4 is inverted to high level.

During this time, even if the output terminal of the output terminal 9 is reversed to a high level, the first analog switch 10 remains off.
The dispatch card will maintain all low levels. Then, as described above, when the output node 5 of the second voltage comparator 4 is inverted to a high level, and the output terminal of the inverter 12 becomes a high level, the second analog switch 13 is turned on, so the selection is made. Output to door becomes high level. As a result, the second analog switch 13 is turned off9.
Charging of the capacitor C starts from the selected output Two Door through the resistor Rt-.

The oscillation operation is performed by repeating the above-mentioned operations. In this case, two reference voltages vs e
The difference in V2 determines the Schmitt voltage width, and the reference voltages vl, v! is generated by a resistor divider, and the Schmitt voltage III? is generated under a wide range of supply voltages. ! /
Since the value of t@voltage can be kept constant, the circuit operation is stable and the oscillation frequency is also stable.

In addition, since two voltage ratio 'F2 devices 2 and 4 each having the above two reference voltages "1 + V@" as circuit thresholds are used, oscillation is possible even at a low power supply voltage, and it can be used over a wide range of power supply voltages. In other words, since the first voltage comparator 2 uses N-channel transistors N!, N, for input, it can operate as long as there is a power supply voltage equal to or higher than its threshold voltage V□. Similarly, the second voltage comparator 4 has a P-channel transistor P1eP4 as an input.
is used, so the absolute value of the threshold voltage is 1v□,
Operation is possible if there is a power supply voltage of 1 or more. Therefore, compared to the conventional system which required a power supply voltage of V□N +l vTHP 1 or higher, operation with a lower power supply voltage is possible.

Note that the present invention is not limited to the above embodiments, and various modifications are possible. For example, the CR shown in Figure 3
The R oscillation circuit is the same as the CRR oscillation circuit of the embodiment described above, but has an excavation stop mode. That is, the CRR
The difference from the oscillating circuit is that the constant voltage generating circuit is used as the first. It is divided into the second constant voltage generating circuit 31 and 32, and the first constant voltage generating circuit 31 and 32 are
Pressure generation circuit 3inP channel transistor Pγ and resistor R
45R5 are connected in series, and the connection point between the resistors R4* and R5 is used as the output node of the reference voltage v1, and the second constant voltage generation circuit 32 is connected in series with the resistor R@*R7 and the N-channel transistor NY. The connection point between the resistors R6*Ry is used as the output node of the reference voltage V. Also, the first
N-channel transistor N! for comparison voltage input in the voltage ratio shaper 2'. An N-channel transistor for standby control is connected in parallel to Ns? The P-channel transistor Ps t for standby control is connected in parallel to the P-channel transistor P of the current mirror load -R (Qll).Similarly, the comparison input in the voltage comparator 4' of W, 2 The standby control P-channel transistor Pet' is connected in parallel to the standby control P-channel transistor P4, and the standby control N-channel transistor Nsk is connected in parallel to the N-channel transistor N on the primary side of the current mirror load. Then, the standby input terminal 30 is connected to the transistors P?mNB, NB.
The input terminal is connected to the input terminal 31, and the output terminal of the inverter 33 is connected to the transistor N7.
# Connected to each dart of PleP9.

In the above CRR oscillator circuit with oscillation stop mode, when the standby input terminal 30 is at a low level, the transistor P? , N is on, transistor P s m
NB # P g m N* is turned off and the same operation as in the previous embodiment is obtained. On the other hand, when the standby input terminal 30 is at a high level, the transistors Pγ and R7 are turned off, and the transistor P.

N@@Pg*N is turned on, the oscillation operation is stopped, and the current consumption is suppressed.

The output selection circuit 6 can also be modified in various ways, as long as it is configured to switch input selection 2 at the timing when the logic levels of two inputs match and invert the logic level of the output.

[Effects of the Invention] As described above, according to the CR oscillation circuit of the present invention, stable oscillation can be performed even at a low power supply voltage, and oscillation operation with little frequency fluctuation can be performed under a wide range of power supply voltages.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the CR generation circuit of the present invention. 2 is a waveform diagram showing the operation of the circuit of FIG. 1, FIG. 3 is a circuit diagram showing another embodiment, and FIGS. 4 and 5 are circuit diagrams showing conventional CRR oscillator circuits. 1 #31 a 32... Constant voltage generation circuit, 2.4
...Voltage comparator, 3,5.7-...Output node, 6.
...output selection circuit, C...capacitor, R...resistance, vl, ■. ...Reference voltage, N1 #Nz...N channel transistor sP@#P4...P channel transistor, 30...Standby input terminal.

Claims (3)

[Claims] (1) A constant voltage generation circuit that generates a first reference voltage and a second reference voltage with different potentials by resistance division, and the first reference voltage and the second reference voltage are respectively given as circuit thresholds. a first voltage comparator and a second voltage comparator that waveform shape a mutually common input voltage;
each output of these two voltage comparators is led as an input, and an output selection circuit switches the input selection at the timing when each logic level of these two inputs matches, and inverts the logic level of an output signal; It has a capacitor and a resistor whose charging operation and discharging operation can be switched by the output signal of the output selection circuit, and a CR time constant circuit which supplies the voltage at one end of the capacitor as a common input voltage to the two voltage comparators. A CR oscillation circuit characterized by: (2) The first voltage comparator has two N-channel transistors whose gates are respectively inputted with a reference voltage and a comparison voltage, and the second voltage comparator has two N-channel transistors whose gates are respectively inputted with a reference voltage and a comparison voltage. The CR oscillation circuit according to claim 1, characterized in that it has two P-channel transistors that input to the gates correspondingly. (3) Oscillation operation possible state according to standby control input;
3. The CR oscillation circuit according to claim 1 or 2, further comprising an additionally connected element for controlling the oscillation operation to a halt state.