JP2010147418A - Semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is reducible in electric resistance of a power supply line and a ground line and in inductance, and a method of manufacturing the same. <P>SOLUTION: The method of manufacturing the semiconductor device includes the steps of: forming openings which penetrate an insulating layer by pressing a pattern 56 having columnar bodies 56a and 56c against the insulating layer 38, so that the columnar bodies pierce the insulating layer; burying conductors in the openings; arranging the insulating layer having the conductors buried on a circuit board; and mounting a semiconductor element on the insulating layer having the conductors buried and connecting a plurality of electrodes of the semiconductor element by the conductors in common. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Recently, a BGA (Ball Grid Array) package in which a semiconductor element (semiconductor chip) such as an LSI is mounted on a circuit board and solder bumps (solder balls) are formed on the lower surface of the circuit board has attracted attention.

  A circuit board used in such a semiconductor device is required to be further miniaturized in order to realize high-density mounting and the like.

The via (opening) of the circuit board is formed by, for example, a drill, a laser, a photolithography technique, or the like. As the wiring becomes finer, the via diameter tends to be smaller.
JP 2006-351963 A JP 2000-223614 A JP 2003-142624 A

  Small diameter vias have relatively large electrical resistance and inductance. In the case of a signal line, even if a via having a small diameter is used, no particular problem occurs. However, in order to ensure stable operation, it is preferable to sufficiently reduce the electrical resistance and inductance of the power supply line and the ground line (ground line).

  An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that can reduce the electrical resistance and inductance of a power supply line and a ground line while miniaturization is achieved.

  According to one aspect of the embodiment, a step of pressing a mold having a columnar body against an insulating layer to penetrate the insulating layer by the columnar body and forming an opening penetrating the insulating layer; and conducting in the opening Embedding a body, disposing the insulating layer in which the conductor is embedded on a circuit board, mounting a semiconductor element on the insulating layer in which the conductor is embedded, and a plurality of the semiconductor elements A method of manufacturing a semiconductor device, comprising: a step of commonly connecting electrodes by the conductor.

  According to another aspect of the embodiment, a step of pressing a conductive layer including a columnar conductor against the insulating layer and penetrating the insulating layer with the conductor, and polishing the conductive layer until a surface of the insulating layer is exposed A step of embedding the conductor in the insulating layer, a step of arranging the insulating layer in which the conductor is embedded on a circuit board, and a semiconductor on the insulating layer in which the conductor is embedded. There is provided a method of manufacturing a semiconductor device, comprising: mounting an element; and connecting a plurality of electrodes of the semiconductor element in common by the conductor.

  According to still another aspect of the embodiment, an insulating layer formed on a circuit board, a conductor embedded in an opening penetrating the insulating layer, and mounted on the insulating layer in which the conductor is embedded. A semiconductor device is provided, wherein a plurality of electrodes of the semiconductor element are connected in common by the conductor.

  According to the disclosed semiconductor device and the manufacturing method thereof, a large-sized conductor that commonly connects a plurality of power supply electrodes of the semiconductor element is embedded in the insulating layer. Electrical resistance and the like can be sufficiently reduced.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIG. FIG. 1 is a cross-sectional view and a plan view showing the semiconductor device according to the present embodiment. FIG. 1A is a cross-sectional view (part 1) showing the semiconductor device according to the present embodiment. FIG. 1B is a plan view showing a part of the semiconductor device according to the present embodiment. FIG. 1A corresponds to the AA ′ cross section of FIG. FIG. 2 is a cross-sectional view (part 2) of the semiconductor device according to the present embodiment. FIG. 2 corresponds to the BB ′ cross section of FIG.

  As shown in FIGS. 1 and 2, through holes (openings, via holes) 12 a to 12 c are formed in a circuit board (package board, support board, core layer) 10. The through hole 12a (see FIG. 1A) is for embedding a conductor (through electrode, via) 14a for power supply. The through hole 12b (see FIG. 2) is for embedding a grounding (ground) conductor 14b. The through hole 12c is for embedding the signal conductor 14c. The diameter of the through holes 12a to 12c is, for example, about 150 to 300 μm. As the circuit board 10, for example, a glass epoxy board or the like is used. The circuit board 10 is not limited to a glass epoxy board. For example, a ceramic substrate or the like may be used as the circuit board 10.

  Conductors 14a to 14c are embedded in the through holes 12a to 12c, respectively. For example, Cu (copper) or the like is used as the material for the conductors 14a to 14c. It is preferable to set the electric resistance and inductance of the power line and the ground line to be sufficiently low. For this reason, a large number of conductors 14a for power supply (see FIG. 1A) and conductors 14b for grounding (see FIG. 2) are embedded in the circuit board 10.

  Wirings 16a to 16c are formed on the upper surface side of the circuit board 10 in which the conductors 14a to 14c are embedded. For example, Cu or the like is used as the material of the wirings 16a to 16c. A number of power supply conductors 14a embedded in the circuit board 10 are electrically connected to each other by wirings 16a. Thus, a large number of power supply conductors 14a embedded in the circuit board 10 are connected in parallel. A large number of grounding conductors 14b embedded in the circuit board 10 are electrically connected to each other by wirings 16b. As a result, a large number of grounding conductors 14b embedded in the circuit board 10 are connected in parallel. The signal wiring 16 c is connected to a signal conductor 14 c embedded in the circuit board 10.

  Wirings 18a to 18c are formed on the lower surface side of the circuit board 10 in which the conductors 14a to 14c are embedded. For example, Cu or the like is used as the material of the wirings 18a to 18c. A number of power supply conductors 14a embedded in the circuit board 10 are electrically connected to each other by wirings 18a. A large number of power supply conductors 14b embedded in the circuit board 10 are electrically connected to each other by wirings 18b. The signal wiring 18 c is connected to the signal conductor 14 c embedded in the circuit board 10.

  An insulating layer 20 is formed on the upper surface side of the circuit board 10 so as to cover the wirings 16a to 16c. The thickness of the insulating layer 20 is about 5 to 50 μm, for example. As the material of the insulating layer 20, for example, a resin is used. More specifically, epoxy resin, polyimide resin, or the like is used as the material of the insulating layer 20.

  Openings (via holes) 22a to 22c reaching the wirings 16a to 16c, respectively, are formed in the insulating layer 20. Conductors (vias) 24a to 24c are embedded in the openings 22a to 22c. For example, Cu or the like is used as the material of the conductors 24a to 24c. As described above, it is preferable to set the electric resistance and inductance of the power supply line and the ground line sufficiently low. For this reason, the insulating layer 20 is embedded with a large number of conductors 24a for power supply and conductors 24b for grounding. The power supply conductors 24a are electrically connected to each other by the wiring 16a. The grounding conductors 24b are electrically connected to each other by the wiring 16b. The signal conductor 24c is connected to the signal wiring 16c.

  An insulating layer 26 is formed on the lower surface side of the circuit board 10 so as to cover the wirings 18a to 18c. The thickness of the insulating layer 26 is, for example, about 5 to 50 μm. As a material of the insulating layer 26, for example, a resin is used. More specifically, epoxy resin, polyimide resin, or the like is used as the material of the insulating layer 26.

  Openings (via holes) 28 a to 28 c reaching the wirings 18 a to 18 c are formed in the insulating layer 26. Conductors (vias) 30a to 30c are embedded in the openings 28a to 28c. For example, Cu or the like is used as a material for the conductors 30a to 30c.

  An electrode pad 32 is formed on the lower surface side of the insulating layer 26. The electrode pads 32 are connected to the conductors 30a to 30c, respectively. The pitch of the electrode pads 32 is, for example, about 1 mm. Solder bumps 34 are formed on the lower surface side of the electrode pads 32.

  Wirings (conductive films) 36a to 36c are formed on the insulating layer 20 in which the conductors 24a to 24c are embedded. For example, Cu or the like is used as a material of the wirings 36a to 36c. A number of power supply conductors 24a embedded in the insulating layer 20 are electrically connected to each other by wiring (conductive film) 36a. A large number of grounding conductors 24b embedded in the insulating layer 20 are electrically connected to each other by wiring (conductive film) 36b. The signal wiring 36 c is connected to a signal conductor 24 c embedded in the insulating layer 20.

  An insulating layer 38 is formed on the insulating layer 20 on which the wirings 36a to 36c and the like are formed. The thickness of the insulating layer 38 is about 5 to 50 μm, for example. As a material of the insulating layer 38, for example, a resin is used. More specifically, for example, an epoxy resin or a polyimide resin is used as the material of the insulating layer 38.

  In the insulating layer 38, openings (via holes) 40a to 40c reaching the wirings (conductive films) 36a to 36c are formed. The openings 40 a to 40 c are formed so as to penetrate the insulating layer 38. As will be described later, in this embodiment, a mold 56 having columnar bodies (convex bodies, convex portions) 56a to 56c is pressed against the insulating layer 38, and the insulating layer 38 is penetrated by the columnar body, thereby opening the insulating layer 38. Portions 40a to 40c are formed. In this embodiment, since the openings 40a to 40c are formed using the mold 56 having the columnar bodies 56a to 56c, the openings 40a to 40c having different diameters (sizes) can be easily formed. The opening 40a for embedding the power supply conductor 42a is formed by a columnar body 56a having a relatively large diameter. The opening 40b for embedding the grounding conductor 42b is formed by a columnar body 56b having a relatively large diameter. The opening 40c for embedding the signal conductor 42c is formed by a columnar body 56c having a relatively small diameter. The diameter of the opening 40a for embedding the power supply conductor 42a is, for example, 2 mm × 0.2 mm. The diameter of the opening 40b for embedding the grounding conductor 42b is, for example, 2 mm × 0.2 mm. The diameter of the opening 40c for embedding the signal conductor 42c is, for example, 0.1 mmφ.

  Conductors (vias) 42a to 42c are embedded in the openings 40a to 40c. As shown in FIG. 1B, the power supply conductors 42a and the grounding conductors 42b are alternately provided. The cross-sectional area of the power supply conductor 42a and the grounding conductor 42b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as the cross-sectional area of the signal conductor 42c (the upper surface of the circuit board 10). For example, the cross-sectional area of the cross section is three times or more. In addition, the cross-sectional area of the power supply conductor 42a and the grounding conductor 42b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as the cross-sectional area of the signal conductor 42c (the upper surface of the circuit board 10). More preferably, it is 10 times or more of the cross-sectional area of the parallel cross section.

  A solder resist film 44 is formed on the insulating layer 38 in which the conductors 42a to 42c are embedded.

  In the solder resist film 44, openings 46 reaching the conductors 42a to 42c are formed. The opening 46 is formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2.

  An electrode pad 50 is formed in the opening 46 of the solder resist film 44. The electrode pad 50 is formed of, for example, a solder paste. The electrode pad 50 is formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2. A plurality of electrode pads 50 are formed on the power supply conductor 42a. A plurality of electrode pads 50 are formed on the grounding conductor 42b.

  A semiconductor element (semiconductor chip) 2 is mounted on the insulating layer 38 on which the electrode pads 50 are formed. The electrodes 48 a to 48 c of the semiconductor element 2 are electrically connected to the conductors 42 a to 42 c embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. More specifically, the plurality of power supply electrodes 48 a of the semiconductor element 2 are electrically connected to the power supply conductor 42 a embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. Yes. The plurality of power supply electrodes 48 a are commonly connected by a power supply conductor 42 a embedded in the insulating layer 38. The plurality of grounding electrodes 48 b of the semiconductor element 2 are electrically connected to the grounding conductors 42 b embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. The plurality of grounding electrodes 48 b of the semiconductor element 2 are commonly connected by a grounding conductor 42 b embedded in the insulating layer 38. The signal electrode 48 c of the semiconductor element 2 is electrically connected to the signal conductor 42 c through the solder bump 52 and the electrode pad 50.

  Thus, in this embodiment, as will be described later, by pressing the mold 56 having the columnar bodies 56a to 56c against the insulating layer 38, the openings 40a to 40c having different diameters are formed, and the openings 40a to 40c are formed in the openings 40a to 40c. The conductors 42a to 42c are embedded in the substrate. Therefore, according to the present embodiment, the conductors 42a to 42c having different diameters can be easily embedded in the insulating layer 38. The conductors 42a and 42b having relatively large diameters are used as power source and grounding conductors. On the other hand, the conductor 42c having a relatively small diameter is used as a signal conductor. Therefore, according to the present embodiment, it is possible to sufficiently reduce the electric resistance and inductance of the power supply line and the ground line while achieving miniaturization and high integration.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 3 to 6 are process cross-sectional views illustrating the semiconductor device manufacturing method according to the present embodiment.

  First, a conductive film is formed on a pedestal (support substrate) 54. As the base 54, for example, a silicon wafer or the like can be used. The film thickness of the conductive film is, for example, about 5 μm. As a material for the conductive film, for example, Cu or the like can be used.

  Next, the conductive film is patterned using a photolithography technique. Thereby, the wiring (conductive film) 36a connected to the plurality of conductors 24a for power supply (see FIG. 1A) and the wiring (conductive) connected to the plurality of conductors 24b for grounding (see FIG. 2). A film (film) 36b and a wiring (conductive film) 36c connected to the signal conductor 24c are formed (see FIG. 3A).

  Next, the insulating layer 38 is formed on the base 54 on which the wirings 36a to 36c are formed (see FIG. 3B). The thickness of the resin layer 38 is, for example, about 10 μm. As a material of the insulating layer 38, for example, a resin is used. More specifically, for example, an epoxy resin or a polyimide resin is used as the material of the insulating layer 38. As the insulating layer 38, for example, a semi-cured insulating layer is formed. The semi-cured insulating layer can be obtained, for example, by applying a liquid resin material for forming the insulating layer 38 on the pedestal and then semi-curing the resin material by heat treatment.

  Alternatively, the uncured insulating layer 38 may be formed on the entire surface, and the insulating layer 38 may be cured while pressing the mold 56 against the insulating layer 38 in a subsequent process.

  Next, a mold (imprint mold) 56 in which columnar bodies (convex bodies, convex portions) 56a to 56c are formed is prepared (see FIG. 3C). The die 56 is for forming the openings 40a to 40c in the insulating layer 38 in a later step. Accordingly, the shapes of the columnar bodies 56 a to 56 c are set according to the shapes of the openings 40 a to 40 c to be formed in the insulating layer 38. As a material of the mold 56, for example, silicon can be used. When processing the mold 56, for example, anisotropic etching or the like can be used.

  The tip end (lower end) of the columnar body 56c is preferably sharp. The tip of the columnar body 56c is sharpened because the insulating layer 38 is easily penetrated by the columnar body 56c when the mold 56 is pressed against the insulating layer 38 in the subsequent process to form the openings 40a, 40c in the insulating layer 38. It is for doing so. From the same viewpoint, the tip end (lower end) of the columnar body 56a may be sharpened. Specifically, it is preferable to form unevenness having a sawtooth cross section at the lower end of the columnar body 56a.

  The diameter of the columnar body 56a for forming the power supply conductor 42a is, for example, 2 mm × 0.2 mm. The diameter of the columnar body 56b for forming the grounding conductor 42b is, for example, 2 mm × 0.2 mm. The diameter of the columnar body 56c for forming the signal conductor 42c is, for example, 0.1 mmφ.

  Note that the material of the mold 56 is not limited to silicon. For example, a metal such as nickel or a nickel alloy may be used as the material of the mold 56.

  Next, the mold 56 in which the columnar bodies 56a to 56c are formed is pressed against the insulating layer 38 (mold pressing, imprint) (see FIGS. 3B and 3D). Thereby, the insulating layer 38 is penetrated by the columnar bodies 56 a to 56 c, and openings (via holes) 40 a to 40 c are formed in the insulating layer 38. Since the openings 40a and 40b are formed by penetrating the insulating layer 38 by the columnar bodies 56a and 56b, the cross-sectional area of the lower part of the openings 40a and 40b and the cross-sectional area of the upper part of the openings 40a and 40b are equal to each other. . In the present embodiment, the openings 56 a to 40 c are formed in the insulating layer 38 by pressing the mold 56 having the columnar bodies 56 a to 56 c against the insulating layer 38. For this reason, it is possible to form openings 40a to 40c of various sizes in the insulating layer 38 by appropriately setting the diameters of the columnar bodies 56a to 56c according to the diameters of the openings 40a to 40c to be formed. is there. For example, the opening 40a for embedding the power supply conductor 42a and the opening 40b for embedding the grounding conductor 42b can be formed with a sufficiently large diameter. On the other hand, the opening 40c for embedding the signal conductor 42c can be formed with a relatively small diameter.

  Next, the insulating layer 38 is cured by performing a heat treatment. The heat treatment temperature is about 300 ° C., for example. The heat treatment time is about 60 minutes, for example.

  Next, the mold 56 is removed from the base 54. Thus, an opening 40a for embedding the power supply conductor 42a, an opening 40b for embedding the grounding conductor 42b, and an opening 40c for embedding the signal conductor 42c are formed in the insulating layer 38. (See FIG. 4A). Since the opening 40c is formed using the columnar body 56c having a sharp lower end, the insulating layer 38 is surely penetrated by the columnar body 56c, and the upper surface of the wiring 36c is reliably exposed in the opening 40c.

  Next, a conductive film 42 is formed in the openings 40a to 40c and on the insulating layer 38 by electroplating (see FIG. 4B). The film thickness of the conductive film 42 is, for example, about 20 μm. For example, a Cu film or the like is formed as the conductive film 42.

  Next, the conductive film 42 is polished by, for example, CMP (Chemical Mechanical Polishing) until the upper surface of the insulating layer 38 is exposed (see FIG. 4C). Thereby, the conductors 42a to 42c are embedded in the openings 40a to 40c. The cross-sectional area of the power supply conductor 42a and the grounding conductor 42b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as the cross-sectional area of the signal conductor 42c (the upper surface of the circuit board 10). For example, the cross-sectional area of the cross section is preferably 3 times or more. Further, it is more preferable that the cross-sectional area of the power supply conductor 42a and the grounding conductor 42b is, for example, 10 times or more the cross-sectional area of the signal conductor 42c.

  In this embodiment, the diameters of the power supply conductor 42a and the grounding conductor 42b are relatively large. Such conductors 42a and 42b having a relatively large diameter can commonly connect a plurality of power supply electrodes 48a and a plurality of grounding electrodes 48b of the semiconductor element 2. According to the present embodiment, since the conductor having a relatively large diameter is formed as the power supply conductor 42a and the grounding conductor 42b, the electric resistance and inductance of the power supply line and the ground line are sufficiently reduced. be able to.

  Next, a solder resist film 44 is formed on the entire surface by, eg, spin coating. The film thickness of the solder resist film 44 is, for example, about 10 μm.

  Next, an opening 46 reaching the conductors 42a to 42c is formed in the solder resist film 44 by using a photolithography technique (see FIG. 4D). The openings 46 are formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2, respectively. A plurality of openings 46 are formed on the power supply conductor 42a. A plurality of openings 46 are also formed on the grounding conductor 42b. The pitch of the openings 46 is, for example, about 176 μm.

  Next, an electrode pad 50 is formed in the opening 46 formed in the solder resist film 44 (see FIG. 5A). As a material for the electrode pad 50, for example, a solder paste is used. When a solder paste is used as the material for the electrode pad 50, the electrode pad 50 can be formed by, for example, a printing method. The electrode pad 50 is formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2. A plurality of electrode pads 50 are formed on the power supply conductor 42a. A plurality of electrode pads 50 are also formed on the grounding conductor 42b.

  Next, the pedestal 54 supporting the insulating layer 38 in which the conductors 42a to 42c and the like are embedded is removed (see FIG. 5B). The removal of the pedestal 54 can be performed, for example, by wet etching or the like. As the etchant, for example, hydrofluoric acid is used when the material of the base 54 is a silicon wafer. The pedestal 54 can be removed by a CMP method or the like.

  Next, as shown in FIG. 5C, a circuit board (package board) 10 on which insulating layers 20 and 26, conductors 14a to 14c, 24a to 24c, 30a to 30c, solder bumps 34, and the like are formed is prepared. To do.

  As the circuit board 10, for example, a glass epoxy board or the like is used. The circuit board 10 is not limited to a glass epoxy board. For example, a ceramic substrate or the like may be used as the circuit board 10.

  Through holes 12 a to 12 c are formed in the circuit board 10. The diameter of the through holes 12a to 12c is, for example, about 150 to 300 μm. Conductors 14a to 14c are embedded in the through holes 12a to 12c. For example, Cu or the like is used as the material of the conductors 14a to 14c. It is preferable to set the electric resistance and inductance of the power line and the ground line to be sufficiently low. For this reason, the circuit board 10 is embedded with a large number of conductors 14a for power supply (see FIG. 1A) and conductors 14b for grounding (see FIG. 2). In addition, a signal conductor 12 c is also embedded in the circuit board 10.

  Wirings 16a to 16c are formed on the upper surface side of the circuit board 10 in which the conductors 12a to 12c are embedded. For example, Cu or the like is used as the material of the wirings 16a to 16c. A number of power supply conductors 12a embedded in the circuit board 10 are connected in parallel by wirings 16a. A number of grounding conductors 12b embedded in the circuit board 10 are connected in parallel by wirings 16b. Further, the signal wiring 16 c is connected to a signal conductor 12 c embedded in the circuit board 10.

  Wirings 18a to 18c are formed on the lower surface side of the circuit board 10 in which the conductors 12a to 12c are embedded. For example, Cu or the like is used as the material of the wirings 18a to 18c. A large number of power supply conductors 12a embedded in the circuit board 10 are connected in parallel by wires 18a. The grounding conductors 12b embedded in the circuit board 10 are connected in parallel by wirings 18b. The signal wiring 18 c is connected to the signal conductor 14 c embedded in the circuit board 10.

  An insulating layer 20 is formed on the upper surface side of the circuit board 10 so as to cover the wirings 16a to 16c. The thickness of the insulating layer 20 is about 5 to 50 μm, for example. As the material of the insulating layer 20, for example, a resin is used. More specifically, epoxy resin, polyimide resin, or the like is used as the material of the insulating layer 20.

  Openings 22 a to 22 c reaching the wirings 16 a to 16 c are formed in the insulating layer 20. Conductors 24a to 24c are embedded in the openings 22a to 22c. For example, Cu or the like is used as the material of the conductors 24a to 24c. As described above, it is preferable to set the electric resistance and inductance of the power supply line and the ground line sufficiently low. For this reason, the insulating layer 20 is embedded with a large number of conductors 24a for power supply and conductors 24b for grounding.

  An insulating layer 26 is formed on the lower surface side of the circuit board 10 so as to cover the wirings 18a to 18c. The thickness of the insulating layer 26 is, for example, about 5 to 50 μm. As a material of the insulating layer 26, for example, a resin is used. More specifically, epoxy resin, polyimide resin, or the like is used as the material of the insulating layer 26.

  Openings 28a to 28c reaching the wirings 18a to 18c are formed in the insulating layer 26, respectively. Conductors 30a to 30c are embedded in the openings 28a to 28c, respectively. For example, Cu or the like is used as a material for the conductors 30a to 30c.

  An electrode pad 32 is formed on the lower surface side of the insulating layer 26. The electrode pads 32 are connected to the conductors 30a to 30c, respectively. The pitch of the electrode pads 32 is, for example, about 1 mm. Solder bumps 34 are formed on the lower surface side of the electrode pads 32.

  Next, the insulating layer 38 in which the conductors 42a to 42c, the wirings 36a to 36c and the like are embedded is placed on the circuit board (package substrate) 10 (FIGS. 5C and 6A). reference).

  Next, the insulating layer 38 in which the conductors 42a to 42c, the wirings 36a to 36c and the like are embedded is attached to the circuit board 10 by heating while applying pressure. Thereby, the upper surface of the insulating layer 20 formed on the circuit board 10 and the lower surface of the insulating layer 38 are joined. Further, the upper surfaces of the conductors 24 a to 24 c embedded in the insulating layer 20 and the lower surfaces of the wirings 36 a to 36 c embedded in the insulating layer 38 are joined.

  Next, the semiconductor element 2 is mounted on the circuit board 10 provided with the insulating layer 38, the conductors 42a to 42c, and the like. The electrodes 48 a to 48 c of the semiconductor element 2 are electrically connected to the conductors 42 a to 42 c embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. More specifically, the plurality of power supply electrodes 48 a of the semiconductor element 2 are electrically connected to the power supply conductor 42 a embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. The plurality of power supply electrodes 48 a of the semiconductor element 2 are commonly connected by a power supply conductor 42 a embedded in the insulating layer 38. The plurality of grounding electrodes 48 c of the semiconductor element 2 are electrically connected to the conductor 42 b embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. The plurality of grounding electrodes 48 b of the semiconductor element 2 are commonly connected by a grounding conductor 42 b embedded in the insulating layer 38. The signal electrode 48 c of the semiconductor element 2 is electrically connected to the signal conductor 42 c embedded in the insulating layer 38 via the solder bump 52 and the electrode pad 50.

  Thus, the semiconductor device according to the present embodiment is manufactured.

  As described above, in this embodiment, the molds 56 having the columnar bodies 56a to 56c are pressed against the insulating layer 38 to form the openings 40a to 40c having different diameters, and the conductors 42a to 42c are formed in the openings 40a to 40c. Embed 42c. Therefore, according to the present embodiment, the conductors 42a to 42c having different diameters can be easily embedded in the insulating layer 38. The conductors 42a and 42b having relatively large diameters are used as power source and grounding conductors. On the other hand, the conductor 42c having a relatively small diameter is used as a signal conductor. Therefore, according to the present embodiment, it is possible to sufficiently reduce the electric resistance and inductance of the power supply line and the ground line while achieving miniaturization and high integration.

[Second Embodiment]
The semiconductor device and the manufacturing method thereof according to the second embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 6 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The semiconductor device and the manufacturing method thereof according to the present embodiment embed the columnar conductors 62a to 62c in the insulating layer 38 by pressing the conductive layer (type) 62 having the columnar conductors 62a to 62c against the insulating layer 38. Has the main features.

(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 7 is a sectional view and a plan view showing the semiconductor device according to the present embodiment. FIG. 7A is a first cross-sectional view of the semiconductor device according to the present embodiment. FIG. 7B is a plan view showing a part of the semiconductor device according to the present embodiment. FIG. 7A corresponds to the AA ′ cross section of FIG. FIG. 8 is a cross-sectional view (part 2) of the semiconductor device according to the present embodiment. FIG. 8 corresponds to the BB ′ cross section of FIG.

  As shown in FIGS. 7 and 8, conductors (vias) 62a to 62c are embedded in the insulating layer 38 in which the wirings 36a to 36c are embedded. The power supply conductor 62a is connected to the wiring 36a. The grounding conductor 62b is connected to the wiring 36b. The signal conductor 62c is connected to the wiring 36c.

  As will be described later, in this embodiment, a mold 62 having columnar conductors (convex bodies, convex portions) 62a to 62c is pressed against the insulating layer 38, and the insulating layer 38 is penetrated by the columnar conductors 62a to 62c. Thus, the conductors 62 a to 62 c are embedded in the insulating layer 38. In the present embodiment, the conductors 62a to 62c are embedded by pressing the conductive layer 62 having the columnar conductors 62a to 62c against the insulating layer 38. Therefore, the conductors 62a to 62c having different diameters (sizes) can be easily formed into the insulating layer. 38 can be embedded.

  The upper cross-sectional area and the lower cross-sectional area of the power supply conductor 62a are equal to each other. Further, the upper cross-sectional area and the lower cross-sectional area of the grounding conductor 62b are equal to each other.

  The diameter of the power supply conductor 62a is set to be relatively large. The diameter of the power supply conductor 62a is, for example, 2 mm × 0.2 mm. The diameter of the grounding conductor 62b is also set to be relatively large. The diameter of the grounding conductor 62b is, for example, 2 mm × 0.2 mm. The diameter of the signal conductor 62c is set to be relatively small. The diameter of the signal conductor 62c is, for example, 0.1 mm.

  As shown in FIG. 7B, the power supply conductors 62a and the grounding conductors 62b are alternately provided. The cross-sectional area of the power source conductor 62a and the grounding conductor 62b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as the cross-sectional area of the signal conductor 62c (the upper surface of the circuit board 10). For example, the cross-sectional area of the cross section is three times or more. Further, the cross-sectional area of the power source conductor 62a and the grounding conductor 62b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as the cross-sectional area of the signal conductor 62c (the upper surface of the circuit board 10). More preferably, it is 10 times or more of the cross-sectional area of the parallel cross section.

  On the lower end portion of the power supply conductor 62a, irregularities having a sawtooth cross section are formed. In addition, unevenness having a sawtooth cross section is formed at the lower end of the grounding conductor 62b. The lower end of the signal conductor 62c is pointed. The reason why the lower ends of the conductors 62a to 62c are set in such a shape is that the conductors 62a to 62c make it easy to penetrate the insulating layer 38 and the electrical connection between the conductors 62a to 62c and the wirings 36a to 36c. This is to ensure the connection.

  A semiconductor element (semiconductor chip) 2 is mounted on the insulating layer 38 on which the electrode pads 50 and the like are formed. The electrodes 48a to 48c of the semiconductor element 2 are electrically connected to the conductors 62a to 62c embedded in the insulating layer 38 via the solder bumps 52, the electrode pads 50, and the like. More specifically, the plurality of power supply electrodes 48 a of the semiconductor element 2 are electrically connected to the power supply conductor 62 a embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. Yes. The plurality of power supply electrodes 48 a are commonly connected by a power supply conductor 62 a embedded in the insulating layer 38. The plurality of grounding electrodes 48 b of the semiconductor element 2 are electrically connected to the grounding conductors 62 b embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. The plurality of grounding electrodes 48 b of the semiconductor element 2 are commonly connected by a grounding conductor 62 b embedded in the insulating layer 38. The signal electrode 48 c of the semiconductor element 2 is electrically connected to the signal conductor 62 c through the solder bump 52 and the electrode pad 50.

  Thus, in this embodiment, the columnar conductors 62 a to 62 c are embedded in the insulating layer 38 by pressing the conductive layer 62 having the columnar conductors 62 a to 62 c against the insulating layer 38. Also in this embodiment, the conductors 62a and 62b having a relatively large diameter and the conductor 62c having a relatively small diameter can be easily embedded in the insulating layer 38. The conductors 62a and 62b having relatively large diameters are used as power source and grounding conductors. On the other hand, the conductor 62c having a relatively small diameter is used as a signal conductor. For this reason, according to this embodiment, it is possible to sufficiently reduce the electric resistance and inductance of the power supply line and the ground line while achieving miniaturization and high integration.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 9 to 14 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, a mold 60 in which openings (recesses) 58a to 58c are formed is prepared (see FIG. 9A). As the material of the mold 60, for example, silicon or the like is used. When processing the mold 60, for example, anisotropic etching or the like can be used. The openings 58a to 58c are formed so as to correspond to the shapes of the conductors 62a to 62c embedded in the insulating layer 38.

  On the bottoms of the openings 58a and 58b for forming the power supply conductor 62a and the grounding conductor 62b, unevenness having a sawtooth cross section is formed. The reason why such cross-sections have serrated irregularities at the bottoms of the openings 58a and 58b is to form serrated irregularities with cross-sectional sections at the bottoms of the columnar conductors 62a and 62b. Concavities and convexities having a sawtooth cross section are formed on the bottoms of the columnar conductors 62a and 62b because the insulating layer 38 is pressed when the conductive layer 62 having the columnar conductors 62a to 62c is pressed against the insulating layer 38 in a later step. This is to facilitate penetration by the columnar conductors 62a and 62b. Further, unevenness having a sawtooth cross section is formed at the bottom of the columnar conductors 62a and 62b because the columnar conductor layer 62a is formed when the insulating layer 38 is penetrated by the columnar conductors 62a and 62b in a later step. 62b to be surely connected to the wirings 36a and 36b.

  The bottom of the opening 58c for forming the signal conductor 62c is formed so that the diameter gradually decreases downward. The reason why the bottom of the opening 58c is formed in such a shape is to sharpen the tip of the bottom of the columnar conductor (convex portion) 62c. The tip of the bottom of the columnar conductor 62c is sharpened because the insulating layer 38 is likely to be penetrated by the columnar conductor 62c when the conductive layer 62 having the conductors 62a to 62c is pressed against the insulating layer 38 in a later step. It is for doing so. In addition, the tip of the bottom of the columnar conductor 62c is sharpened because the columnar conductor 62c is reliably connected to the wiring 36c when the insulating layer 38 is penetrated by the columnar conductor 62c in a later step. It is for doing so.

  The diameter of the opening 58a for forming the power supply conductor 62a is, for example, 2 mm × 0.2 mm. The diameter of the opening 58b for forming the grounding conductor 62b is, for example, 2 mm × 0.2 mm. The diameter of the opening 58c for forming the signal conductor 62c is, for example, 0.1 mm.

  The cross-sectional area of the power source conductor 62a and the grounding conductor 62b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as the cross-sectional area of the signal conductor 62c (the upper surface of the circuit board 10). For example, the cross-sectional area of the cross section is preferably 3 times or more. Further, it is more preferable that the cross-sectional area of the power supply conductor 62a and the grounding conductor 62b is, for example, 10 times or more the cross-sectional area of the signal conductor 62c.

  The material of the mold 60 is not limited to silicon. For example, a metal such as nickel or a nickel alloy may be used as the material of the mold 60.

  Next, a mold release agent is applied in the openings 58 a to 58 c of the mold 60 and on the upper surface. The reason why the mold release agent is applied to the mold 60 is to allow the conductive layer 62 to be easily separated from the mold 60 in a subsequent process.

  Next, the conductive layer 62 is formed on the mold 60 by, for example, electroplating (see FIG. 9B). For example, Cu is used as the material of the conductive layer 62. Thus, the conductive layer 62 is formed in the openings 58 a to 58 c of the mold 60 and on the mold 60.

  Next, a support substrate (support) 64 is attached on the conductive layer 62 (see FIG. 9C). As a result, the conductive layer 62 is supported by the support substrate 64. As the support substrate 64, for example, a resin substrate can be used.

  Next, the conductive layer 62 is separated from the mold 60 in which the openings 58a to 58c are formed (see FIG. 10A). Since the mold release agent is applied to the mold 60 in which the openings 58 a to 58 c are formed, the conductive layer 62 is easily separated from the mold 60. The conductive layer 62 is separated from the mold 60 while being supported by the support substrate 64. In this way, the conductive layer 62 having columnar conductors (convex portions, convex bodies) 62a to 62c is formed. The conductive layer 62 is for embedding the columnar conductors 62a to 62c in the insulating layer 38 in a later step.

  Next, a conductive film is formed on the pedestal (support substrate) 54. As the base 54, for example, a silicon wafer or the like can be used. As a material for the conductive film, for example, Cu or the like can be used.

  Next, the conductive film is patterned using a photolithography technique. Thereby, the wiring (conductive film) 36a connected to the plurality of conductors 24a for power supply (see FIG. 7A) and the wiring (conductive) connected to the plurality of conductors 24b for grounding (see FIG. 8). A film (film) 36b and a wiring (conductive film) 36c connected to the signal conductor 24c are formed (see FIG. 10B).

  Next, the insulating layer 38 is formed on the base 54 on which the wirings 36a to 36c are formed (see FIG. 10C). As a material of the insulating layer 38, for example, a resin is used. More specifically, for example, an epoxy resin or a polyimide resin is used as the material of the insulating layer 38. As the insulating layer 38, for example, a semi-cured insulating layer is formed. The semi-cured insulating layer can be obtained, for example, by applying a liquid resin material for forming the insulating layer 38 on the pedestal and then semi-curing the resin material by heat treatment.

  Note that the uncured insulating layer 38 may be formed on the entire surface, and the insulating layer 38 may be cured while pressing the conductive layer 62 having the columnar conductors 62a to 62c against the insulating layer 38 in a subsequent process. .

  Next, the conductive layer 62 in which the columnar conductors 62a to 62c are formed is pressed against the insulating layer 38 (see FIGS. 11A and 11B). Thereby, the insulating layer 38 is penetrated by the columnar conductors 62 a to 62 c, and the columnar conductors 62 a to 62 c are embedded in the insulating layer 38. The columnar conductors 62a to 62c are connected to the wirings 38a to 38c, respectively.

  In the present embodiment, the columnar conductors 62 a to 62 c are embedded in the insulating layer 38 by pressing the conductive layer 62 having the columnar conductors 62 a to 62 c against the insulating layer 38. For this reason, by appropriately setting the diameters of the conductors 62a to 62c formed using the mold 60, it is possible to embed the conductors 62a to 62c of various sizes in the insulating layer 38. For example, the power supply conductor 62a and the grounding conductor 62b can be formed with a sufficiently large diameter. On the other hand, the signal conductor 62c can be formed with a relatively small diameter.

  Next, the insulating layer 38 is cured by performing a heat treatment. The heat treatment temperature is about 300 ° C., for example. The heat treatment time is about 60 minutes, for example.

  Next, the support substrate 64 is removed from the conductive layer 62 (see FIG. 12A). Thus, the conductive layer 62 having the conductors 62 a, 62 b and 62 c that penetrate the insulating layer 38 is formed on the insulating layer 38.

  Next, the conductive layer 62 is polished by, for example, CMP until the upper surface of the insulating layer 38 is exposed (see FIG. 12B). Thereby, the conductors 62 a to 62 c are embedded in the insulating layer 38.

  Next, a solder resist film 44 is formed on the entire surface by, eg, spin coating.

  Next, an opening 46 reaching the conductors 62a to 62c is formed in the solder resist film 44 by using a photolithography technique (see FIG. 12C). The openings 46 are formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2, respectively. A plurality of openings 46 are formed on the power supply conductor 62a. A plurality of openings 46 are also formed on the grounding conductor 62b. The pitch of the openings 46 is, for example, about 176 μm.

  Next, an electrode pad 50 is formed in the opening 46 formed in the solder resist film 44 (see FIG. 13A). As a material for the electrode pad 50, for example, a solder paste is used. The electrode pad 50 is formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2. A plurality of electrode pads 50 are formed on the power supply conductor 62a. A plurality of electrode pads 50 are also formed on the grounding conductor 62b.

  Next, the base 54 supporting the insulating layer 38 in which the conductors 62a to 62c and the like are embedded is removed (see FIG. 13B).

  Next, as shown in FIG. 13C, a circuit board (package board) 10 on which insulating layers 20 and 26, conductors 14a to 14c, 24a to 24c, 30a to 30c, solder bumps 34, and the like are formed is prepared. To do.

  Next, the insulating layer 38 in which the conductors 62a to 62c and the wirings 36a to 36c are embedded is placed on the circuit board 10 (see FIGS. 13C and 14A).

  Next, the insulating layer 38 in which the conductors 62 a to 62 c and the like are embedded is attached on the circuit board 10 by heating while applying pressure. Thereby, the upper surface of the insulating layer 20 formed on the circuit board 10 and the lower surface of the insulating layer 38 are joined. Further, the upper surfaces of the conductors 24 a to 24 c embedded in the insulating layer 20 and the lower surfaces of the wirings 36 a to 36 c embedded in the insulating layer 38 are joined.

  Next, the semiconductor element 2 is mounted on the circuit board 10 provided with the insulating layer 38, the conductors 62a to 62c, and the like. The electrodes 48 a to 48 c of the semiconductor element 2 are electrically connected to the conductors 62 a to 62 c embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. More specifically, the plurality of power supply electrodes 48 a of the semiconductor element 2 are electrically connected to the power supply conductor 62 a embedded in the insulating layer 38 through the solder bumps 52 and the electrode pads 50. The plurality of power supply electrodes 48 a of the semiconductor element 2 are commonly connected by a power supply conductor 62 a embedded in the insulating layer 38. The plurality of grounding electrodes 58 c of the semiconductor element 2 are electrically connected to the conductor 62 b embedded in the insulating layer 38 through the solder bumps 52 and the electrode pads 50. The plurality of grounding electrodes 48 b of the semiconductor element 2 are commonly connected by a grounding conductor 62 b embedded in the insulating layer 38. The signal electrode 48 c of the semiconductor element 2 is electrically connected to the signal conductor 62 c embedded in the insulating layer 38 via the solder bump 52 and the electrode pad 50.

  Thus, the semiconductor device according to the present embodiment is manufactured.

  Thus, the columnar conductors 62 a to 62 c may be embedded in the insulating layer 38 by pressing the conductive layer 62 having the columnar conductors 62 a to 62 c against the insulating layer 38. Also in this embodiment, the conductors 62a and 62b having a relatively large diameter and the conductor 62c having a relatively small diameter can be easily embedded in the insulating layer 38. The conductors 62a and 62b having relatively large diameters are used as power source and grounding conductors. On the other hand, the conductor 62c having a relatively small diameter is used as a signal conductor. For this reason, according to this embodiment, it is possible to sufficiently reduce the electric resistance and inductance of the power supply line and the ground line while achieving miniaturization and high integration.

[Third Embodiment]
A semiconductor device and a manufacturing method thereof according to the third embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first or second embodiment shown in FIGS. 1 to 14 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  The semiconductor device and the manufacturing method thereof according to the present embodiment are mainly characterized in that the electronic component 4 is embedded in the insulating layer 38 and the conductors 72a to 72c are further formed on the conductors 42a to 42c. .

(Semiconductor device)
First, the semiconductor device according to the present embodiment will be explained with reference to FIGS. FIG. 15 is a cross-sectional view and a plan view showing the semiconductor device according to the present embodiment. FIG. 15A is a cross-sectional view (part 1) illustrating the semiconductor device according to the present embodiment. FIG. 15B is a plan view showing a part of the semiconductor device according to the present embodiment. FIG. 15A corresponds to the AA ′ cross section of FIG. FIG. 16 is a cross-sectional view (part 2) of the semiconductor device according to the present embodiment. FIG. 16 corresponds to the BB ′ cross section of FIG.

  As shown in FIGS. 15 and 16, wirings 36a to 36c are formed on the insulating layer 20 in which the conductors 22a to 22c and the like are embedded. Further, the electronic component 4 is mounted on the insulating layer 20. As the electronic component 4, for example, a semiconductor element (semiconductor chip) such as an LSI, a capacitor, or the like is mounted. An electrode 68 is formed on the upper surface of the electronic component 4.

  An insulating layer 38 is formed on the insulating layer 20 on which the wirings 36a to 36c and the electronic component 4 are formed. Conductors 42 a to 42 c are embedded in the insulating layer 38.

  An insulating layer 68 is formed on the insulating layer 38 in which the conductors 42a to 42c and the like are embedded. The thickness of the insulating layer 68 is, for example, about 5 to 50 μm. As a material of the insulating layer 68, for example, a resin or the like is used. More specifically, an epoxy resin, a polyimide resin, or the like is used as a material for the insulating layer 68.

  In the insulating layer 68, openings 70a to 70c reaching the conductors 42a to 42c are formed. The openings 70 a to 70 c are formed so as to penetrate the insulating layer 68. As will be described later, in the present embodiment, the insulating layer 68 is formed by pressing a mold 74 having columnar bodies (convex bodies, convex portions) 74a to 74c against the insulating layer 68 and penetrating the insulating layer 68 with the columnar bodies 74a to 74c. Openings 70 a to 70 c are formed in 68. In this embodiment, since the openings 70a to 70c are formed using the mold 74 having the columnar bodies 74a to 74c, the openings 70a to 70c having different diameters (sizes) can be easily formed.

  The opening 70a for embedding the power supply conductor 72a is formed by a columnar body 74a having a relatively large diameter. The opening 70b for embedding the grounding conductor 72b is also formed by a columnar body 74b having a relatively large diameter. The opening 70c for embedding the signal conductor 72c is formed by a columnar body 74c having a relatively small diameter.

  The diameter of the opening 70a for embedding the power supply conductor 72a is set equal to the diameter of the opening 40a for embedding the power supply conductor 42a. The diameter of the opening 70b for embedding the grounding conductor 72b is set equal to the diameter of the opening 40b for embedding the grounding conductor 42b. The diameter of the opening 70c for embedding the signal conductor 72c is set equal to the diameter of the opening 40c for embedding the signal conductor 42c, for example.

  Conductors 72a to 72c are embedded in the openings 70a to 70c. As shown in FIG. 15B, the power supply conductors 72a and the grounding conductors 72b are alternately provided. The cross-sectional area of the power source conductor 72a and the grounding conductor 72b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as that of the signal conductor 72c (the upper surface of the circuit board 10). For example, the cross-sectional area of the cross section is three times or more. In addition, the cross-sectional area of the power source conductor 72a and the grounding conductor 72b (the cross-sectional area of the cross section parallel to the upper surface of the circuit board 10) is the same as the cross-sectional area of the signal conductor 72c (the upper surface of the circuit board 10). More preferably, it is 10 times or more of the cross-sectional area of the parallel cross section.

  The upper cross-sectional area and the lower cross-sectional area of the power supply conductor 72a are equal to each other. In addition, the upper cross-sectional area and the lower cross-sectional area of the grounding conductor 72b are equal to each other.

  The lower end of the signal conductor 72c is pointed. The reason why the lower end portion of the conductor 72c is set in such a shape is that the conductor 72c facilitates the penetration of the insulating layer 68 and the electrical connection between the conductor 72c and the conductor 42c embedded in the insulating layer 38. This is to ensure the connection.

  A solder resist film 44 is formed on the insulating layer 68 in which the conductors 72a to 72c are embedded.

  In the solder resist film 44, openings 46 reaching the conductors 72a to 72c are formed. The opening 46 is formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2.

  An electrode pad 50 is formed in the opening 46 of the solder resist film 44. A plurality of electrode pads 50 are formed on the power supply conductor 72a. A plurality of electrode pads 50 are formed on the grounding conductor 72b.

  A semiconductor element (semiconductor chip) 2 is mounted on the insulating layer 68 on which the electrode pads 50 are formed. The electrodes 48 a to 48 c of the semiconductor element 2 are electrically connected to the conductors 72 a to 72 c embedded in the insulating layer 68 via the solder bumps 52 and the electrode pads 50. More specifically, the plurality of power supply electrodes 58 a of the semiconductor element 2 are electrically connected to the power supply conductor 72 a embedded in the insulating layer 68 through the solder bumps 52 and the electrode pads 50. Yes. The plurality of power supply electrodes 48 a are commonly connected by a power supply conductor 72 a embedded in the insulating layer 38. The plurality of grounding electrodes 48 b of the semiconductor element 2 are electrically connected to the grounding conductor 72 b embedded in the insulating layer 38 via the solder bumps 52 and the electrode pads 50. The plurality of grounding electrodes 48 b of the semiconductor element 2 are commonly connected by grounding conductors 72 b embedded in the insulating layer 38.

  The signal electrode 48c of the semiconductor element 2 is electrically connected to the electrode 66 of the electronic component 4 via the solder bump 52 and the electrode pad 50, the signal conductor 72c, and the signal conductor 42c.

  As in this embodiment, the electronic component 4 may be further embedded in the resin layer 38. Further, as in the present embodiment, a power supply conductor 72a is further formed on the power supply conductor 42a, and a grounding conductor 72b is further formed on the grounding conductor 42b. A signal conductor 72b may be further formed on the conductor 42c. Even when formed in this manner, the plurality of power supply electrodes 48a of the semiconductor element 2 are commonly connected by the power supply conductor 72a. The plurality of grounding electrodes 48b of the semiconductor element 2 are commonly connected by a grounding conductor 72b. The signal electrode 48c of the semiconductor element 2 is electrically connected to the electrode 66 of the electronic component 4 via the signal conductor 72c and the signal conductor 42c. Also according to the present embodiment, the electrical resistance and inductance of the power supply line and the ground line can be sufficiently reduced while achieving miniaturization and high integration.

(Method for manufacturing semiconductor device)
Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS. 17 to 23 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  First, a conductive film is formed on a pedestal (support substrate) 54 (see FIG. 17A). As the base 54, for example, a silicon wafer or the like can be used. The film thickness of the conductive film is, for example, about 5 μm. As a material for the conductive film, for example, Cu or the like can be used.

  Next, the conductive film is patterned using a photolithography technique. As a result, the wiring (conductive film) 36a connected to the plurality of conductors 24a for power supply (see FIG. 15A) and the wiring (conductive) connected to the plurality of conductors 24b for grounding (see FIG. 16). A film (film) 36b and a wiring (conductive film) 36c connected to the signal conductor 24c are formed (see FIG. 17A).

  Further, the electronic component 4 is arranged on the pedestal 54. Examples of the electronic component 4 include a semiconductor element (semiconductor chip) such as an LSI, a capacitor, and the like. An electrode 68 is formed on the upper surface of the electronic component 4.

  Next, the insulating layer 38 is formed on the base 54 on which the wirings 36a to 36c and the electronic component 4 are formed (see FIG. 17B). The thickness of the resin layer 38 is, for example, about 10 μm. As a material of the insulating layer 38, for example, a resin is used. More specifically, for example, an epoxy resin or a polyimide resin is used as the material of the insulating layer 38.

  As the insulating layer 38, for example, a semi-cured insulating layer is formed. The semi-cured insulating layer can be obtained, for example, by applying a liquid resin material for forming the insulating layer 38 on the pedestal and then semi-curing the resin material by heat treatment.

  Alternatively, the uncured insulating layer 38 may be formed on the entire surface, and the insulating layer 38 may be cured while pressing the mold 56 against the insulating layer 38 in a subsequent process.

  Next, a mold 56 on which columnar bodies 56a to 56c are formed is prepared (see FIG. 17C). The mold 56 is for forming the openings 40a to 40c in the insulating layer 38 in a later step. Accordingly, the shapes of the columnar bodies 56 a to 56 c are set according to the shapes of the openings 40 a to 40 c to be formed in the insulating layer 38.

  Next, the die 56 on which the columnar bodies 56a to 56c are formed is pressed against the insulating layer 38 (see FIGS. 17C and 17D). Thereby, the insulating layer 38 is penetrated by the columnar bodies 56 a to 56 c, and openings (via holes) 40 a to 40 c are formed in the insulating layer 38.

  Next, the insulating layer 38 is cured by performing a heat treatment. The heat treatment temperature is about 300 ° C., for example. The heat treatment time is about 60 minutes, for example.

  Next, the mold 56 is removed from the base 54. Thus, an opening 40a for embedding the power supply conductor 42a, an opening 40b for embedding the grounding conductor 42b, and an opening 40c for embedding the signal conductor 42c are formed in the insulating layer 38. (See FIG. 18A). Since the opening 40c is formed using the columnar 56c having a sharp lower end, the insulating layer 38 is surely penetrated by the columnar body 56c, and the upper surface of the wiring 36c and the upper surface of the electrode 66 are reliably exposed in the opening 40c. Is done.

  Next, a conductive film 42 is formed in the openings 40a to 40c and on the insulating layer 38 by electroplating (see FIG. 18B). The film thickness of the conductive film 42 is, for example, about 20 μm. For example, a Cu film or the like is formed as the conductive film 42.

  Next, the conductive film 42 is polished by, for example, CMP until the upper surface of the insulating layer 38 is exposed (see FIG. 18C). Thereby, the conductors 42a to 42c are embedded in the openings 40a to 40c.

  Next, an insulating layer 68 is formed on the insulating layer 38 in which the conductors 42a to 42c and the electronic component 4 are embedded (see FIG. 18D). The thickness of the resin layer 68 is, for example, about 10 μm. As a material of the insulating layer 68, for example, a resin is used. More specifically, for example, an epoxy resin or a polyimide resin is used as the material of the insulating layer 68.

  As the insulating layer 68, for example, a semi-cured insulating layer is formed. The semi-cured insulating layer can be obtained, for example, by applying a liquid resin material for forming the insulating layer 68 on the entire surface and then semi-curing the resin material by heat treatment.

  Alternatively, an uncured insulating layer 68 may be formed on the entire surface, and the insulating layer 68 may be cured while pressing the mold 74 against the insulating layer 68 in a subsequent process.

  Next, a mold 74 on which columnar bodies 74a to 74c are formed is prepared (see FIG. 19A). The mold 74 is for forming openings 70a to 70c in the insulating layer 68 in a later step. Accordingly, the shapes of the columnar bodies 74 a to 74 c are set according to the shapes of the openings 70 a to 70 c to be formed in the insulating layer 68.

  Next, the mold 74 on which the columnar bodies 74a to 74c are formed is pressed against the insulating layer 68 (see FIGS. 19A and 19B). Thereby, the insulating layer 68 is penetrated by the columnar bodies 74 a to 74 c, and the openings 70 a to 70 c are formed in the insulating layer 68.

  Next, the insulating layer 68 is cured by performing a heat treatment. The heat treatment temperature is set to 300 ° C., for example. The heat treatment time is about 60 minutes, for example.

  Next, the mold 74 is removed from the pedestal 54. Thus, an opening 70a for embedding the power supply conductor 72a, an opening 70b for embedding the grounding conductor 72b, and an opening 70c for embedding the signal conductor 72c are formed in the insulating layer 68. (See FIG. 20A). Since the opening 70c is formed using the columnar body 74c having a sharp lower end, the insulating layer 68 is surely penetrated by the columnar body 74c, and the upper surface of the conductor 42c is reliably exposed in the opening 70c.

  Next, a conductive film 72 is formed in the openings 70a to 70c and on the insulating layer 68 by electroplating (see FIG. 20B). The film thickness of the conductive film 72 is, for example, about 20 μm. For example, a Cu film or the like is formed as the conductive film 72.

  Next, the conductive film 72 is polished by, for example, CMP until the upper surface of the insulating layer 68 is exposed (see FIG. 20C). Thereby, the conductors 72a to 72c are embedded in the openings 70a to 70c.

  Next, a solder resist film 44 is formed on the entire surface by, eg, spin coating (see FIG. 21A).

  Next, an opening 46 reaching the conductors 72a to 72c is formed in the solder resist film 44 by using a photolithography technique (see FIG. 21A). The openings 46 are formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2, respectively. A plurality of openings 46 are formed on the power supply conductor 72a. A plurality of openings 46 are also formed on the grounding conductor 72b. The pitch of the openings 46 is, for example, about 176 μm.

  Next, an electrode pad 50 is formed in the opening 46 formed in the solder resist film 44 (see FIG. 21B). The electrode pad 50 is formed so as to correspond to the electrodes 48 a to 48 c of the semiconductor element 2. A plurality of electrode pads 50 are formed on the power supply conductor 72a. A plurality of electrode pads 50 are also formed on the grounding conductor 72b.

  Next, the base 54 supporting the insulating layers 38 and 68 in which the conductors 42a to 42c, 72a to 72c, the wirings 36a to 36c and the like are embedded is removed (see FIG. 21C).

  Next, as shown in FIG. 22A, a circuit board (package board) 10 on which insulating layers 20 and 26, conductors 14a to 14c, 24a to 24c, 30a to 30c, solder bumps 34, and the like are formed is prepared. To do.

  Next, the insulating layers 38 and 68 in which the conductors 42a to 42c, 72a to 72c, the wirings 36a to 36c and the like are embedded are placed on such a circuit board (package substrate) 10 (FIG. 22A). And FIG. 22 (b)).

  Next, the insulating layers 38 and 68 in which the conductors 42a to 42c, 72a to 72c, the wirings 36a to 36c and the like are embedded are attached on the circuit board 10 by heating while applying pressure. Thereby, the upper surface of the insulating layer 20 formed on the circuit board 10 and the lower surface of the insulating layer 38 are joined. Further, the upper surfaces of the conductors 24 a to 24 c embedded in the insulating layer 20 and the lower surfaces of the wirings 36 a to 36 c embedded in the insulating layer 38 are joined.

  Next, the semiconductor element 2 is mounted on the circuit board 10 provided with the insulating layer 68, the conductors 72a to 72c, and the like. The electrodes 48 a to 48 c of the semiconductor element 2 are electrically connected to the conductors 72 a to 72 c embedded in the insulating layer 68 through the solder bumps 52 and the electrode pads 50. More specifically, the plurality of power supply electrodes 48 a of the semiconductor element 2 are electrically connected to the power supply conductor 72 a embedded in the insulating layer 68 through the solder bumps 52 and the electrode pads 50. The plurality of power supply electrodes 48 a of the semiconductor element 2 are commonly connected by a power supply conductor 72 a embedded in the insulating layer 68. The plurality of grounding electrodes 48 c of the semiconductor element 2 are electrically connected to the conductor 72 b embedded in the insulating layer 68 through the solder bumps 52 and the electrode pads 50. The plurality of grounding electrodes 48 b of the semiconductor element 2 are commonly connected by a grounding conductor 72 b embedded in the insulating layer 68. The signal electrode 48 c of the semiconductor element 2 is electrically connected to the signal conductor 72 c embedded in the insulating layer 68 through the solder bump 52 and the electrode pad 50.

  Thus, the semiconductor device according to the present embodiment is manufactured.

  As in this embodiment, the electronic component 4 may be further embedded in the resin layer 38. Then, a power supply conductor 72a is further formed on the power supply conductor 42a, a grounding conductor 72b is further formed on the grounding conductor 42b, and a signal conductor is formed on the signal conductor 42c. The conductor 72b may be further formed. Even when formed in this manner, the plurality of power supply electrodes 48a of the semiconductor element 2 are commonly connected by the power supply conductor 72a. The plurality of grounding electrodes 48b of the semiconductor element 2 are commonly connected by a grounding conductor 72b. The signal electrode 48c of the semiconductor element 2 is electrically connected to the electrode 66 of the electronic component 4 via the signal conductor 72c and the signal conductor 42c. Also according to the present embodiment, the electrical resistance and inductance of the power supply line and the ground line can be sufficiently reduced while achieving miniaturization and high integration.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the third embodiment, a case where openings 40a to 40c are formed in the insulating layer 38 using a mold 56 having columnar bodies 56a to 56c, and conductors 42a to 42c are embedded in the openings 40a to 40c. Although described as an example, the present invention is not limited to this. For example, as described above in the second embodiment, a columnar conductor may be embedded in the insulating layer 38 by pressing a conductive layer having a columnar conductor against the insulating layer 38.

  In the third embodiment, the openings 74a to 70c are formed in the insulating layer 68 using the mold 74 having the columnar bodies 74a to 74c, and the conductors 72a to 72c are embedded in the openings 70a to 70c. Although described as an example, the present invention is not limited to this. For example, as described above in the second embodiment, the columnar conductor may be embedded in the insulating layer 68 by pressing a conductive layer having a columnar conductor against the insulating layer 68.

It is sectional drawing and the top view which show the semiconductor device by 1st Embodiment. It is sectional drawing which shows the semiconductor device by 1st Embodiment. FIG. 6 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 6 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment; FIG. 9 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment; It is sectional drawing and the top view which show the semiconductor device by 2nd Embodiment. It is sectional drawing which shows the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 5) which shows the manufacturing method of the semiconductor device by 2nd Embodiment. It is process sectional drawing (the 6) which shows the manufacturing method of the semiconductor device by 2nd Embodiment. It is sectional drawing and the top view which show the semiconductor device by 3rd Embodiment. It is sectional drawing which shows the semiconductor device by 3rd Embodiment. It is process sectional drawing (the 1) which shows the manufacturing method of the semiconductor device by 3rd Embodiment. It is process sectional drawing (the 2) which shows the manufacturing method of the semiconductor device by 3rd Embodiment. It is process sectional drawing (the 3) which shows the manufacturing method of the semiconductor device by 3rd Embodiment. It is process sectional drawing (the 4) which shows the manufacturing method of the semiconductor device by 3rd Embodiment. It is process sectional drawing (the 5) which shows the manufacturing method of the semiconductor device by 3rd Embodiment. It is process sectional drawing (the 6) which shows the manufacturing method of the semiconductor device by 3rd Embodiment. It is process sectional drawing (the 7) which shows the manufacturing method of the semiconductor device by 3rd Embodiment.

Explanation of symbols

2 ... Semiconductor element 4 ... Electronic component 10 ... Circuit boards 12a-12c ... Through holes 14a-14c ... Conductors 16a-16c ... Wiring 18a-18c ... Wiring 20 ... Insulating layers 22a-22c ... Openings 24a-24c ... Conductors 26 ... Insulating layers 28a-28c ... Openings 30a-30c ... Conductor 32 ... Electrode pads 34 ... Solder bumps 36a-36c ... Wiring 38 ... Insulating layers 40a-40c ... Openings 42a-42c ... Conductor 44 ... Solder resist film 46 ... Openings 48a-48c ... Electrodes 50 ... Electrode pads 52 ... Solder bumps 54 ... Pedestal 56 ... Dies 56a-56c ... Columns 58a-58c ... Openings 60 ... Dies 62 ... Conductive layers 62a-62c ... Electric conductors 64 ... Support substrate 66 ... Electrode 68 ... Insulating layers 70a-70c ... Openings 72a-72c ... Conductor 74 ... Molds 74a-74c ... Columnar body

Claims (7)

A step of pressing a mold having a columnar body against the insulating layer to penetrate the insulating layer by the columnar body and forming an opening that penetrates the insulating layer;
Embedding a conductor in the opening;
Disposing the insulating layer embedded with the conductor on a circuit board;
A method of manufacturing a semiconductor device, comprising: mounting a semiconductor element on the insulating layer in which the conductor is embedded, and connecting a plurality of electrodes of the semiconductor element in common by the conductor. Pressing a conductive layer including a columnar conductor against the insulating layer and penetrating the insulating layer with the conductor;
Burying the conductor in the insulating layer by polishing the conductive layer until the surface of the insulating layer is exposed;
Disposing the insulating layer embedded with the conductor on a circuit board;
A method of manufacturing a semiconductor device, comprising: mounting a semiconductor element on the insulating layer in which the conductor is embedded, and connecting a plurality of electrodes of the semiconductor element in common by the conductor. The method of manufacturing a semiconductor device according to claim 2.
A method of manufacturing a semiconductor device, further comprising a step of curing the insulating layer by performing a heat treatment after the step of penetrating the insulating layer with the conductor and before the step of polishing the conductive layer. In the manufacturing method of the semiconductor device according to any one of claims 1 to 3,
The method for manufacturing a semiconductor device, wherein the plurality of electrodes of the semiconductor elements connected in common by the conductor are electrodes for power supply or electrodes for grounding. In the manufacturing method of the semiconductor device of any one of Claims 1 thru / or 4,
The method for manufacturing a semiconductor device, wherein a cross-sectional area of an upper layer portion of the conductor is equal to a cross-sectional area of a lower layer portion of the conductor. An insulating layer formed on the circuit board;
A conductor embedded in an opening through the insulating layer;
A semiconductor element mounted on the insulating layer in which the conductor is embedded;
A plurality of electrodes of the semiconductor element are connected in common by the conductor. The semiconductor device according to claim 6.
The plurality of electrodes of the semiconductor elements connected in common by the conductor are power supply electrodes or ground electrodes. A semiconductor device, wherein:

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