JP2014086525A - Wiring structure and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring structure capable of suppressing a contact failure between a land and a via, and a method of manufacturing the same.SOLUTION: The wiring structure comprises: a first via embedded in a first insulating film; a second insulating film formed on the first insulating film; a land embedded in the second insulating film and electrically connected to the first via; a wiring pattern embedded in the second insulating film and formed apart from the land; a third insulating film formed on the second insulating film; and a second via embedded in the third insulating film and electrically connected to the land. The land has a plurality of columnar conductors, and at least some of the plurality of columnar conductors are electrically connected to the first via and the second via.

Description

  The present invention relates to a wiring structure and a manufacturing method thereof.

  In recent years, along with demands for downsizing and high performance of electronic devices, the miniaturization of semiconductor chips and the increase in the number of terminals, miniaturization and high integration of circuit boards on which semiconductor chips are mounted, and electronic components on circuit boards High-density mounting is underway. Since the increase in the number of terminals of a semiconductor chip and the reduction in the pitch between terminals lead to a demand for miniaturization of rewiring used for circuit boards and packages, the miniaturization technique of this rewiring is regarded as important.

  A wiring formation process called a semi-additive method is often used for the rewiring of a buildup substrate used for a package substrate and the rewiring of a wafer level package. In the semi-additive method, a wiring is formed by selectively growing a plating film in an opening using a resist having an opening of the wiring pattern as a mask. However, in the semi-additive method, it is necessary to remove the seed layer that serves as a seed during plating and the underlying adhesion layer after the growth of the plating film, but the side etching at this time makes it difficult to control the wiring width and adhesion strength. .

  For this reason, it is preferable to use a wiring formation process called a damascene method for forming fine wiring, particularly wiring having L / S = 5/5 μm or less. In the damascene method, after wiring material is deposited on the entire surface of a substrate on which an insulating film having a wiring groove is formed, the wiring material on the insulating film is removed to selectively leave the wiring material in the wiring groove. Is formed.

JP 2006-135154 A

  However, when a structure in which multilayer vias are stacked by using a damascene process, that is, a so-called stacked via structure is formed, via contact failure may occur.

  An object of the present invention is to provide a wiring structure capable of suppressing contact failure between a land and a via and a manufacturing method thereof.

  According to one aspect of the embodiment, the first insulating film formed on the substrate, the first via embedded in the first insulating film, and the first via embedded in the first via. A second insulating film formed on the insulating film, a land embedded in the second insulating film, electrically connected to the first via, and embedded in the second insulating film, A wiring pattern formed away from the land, a third insulating film formed on the second insulating film in which the land and the wiring pattern are embedded, and embedded in the third insulating film. A second via electrically connected to the land, wherein the land has a plurality of columnar conductors, and at least a part of the plurality of columnar conductors includes the first via and the second vias. A wiring structure is provided that is electrically connected to the second via.

  According to another aspect of the embodiment, a step of forming a first insulating film in which a first via is embedded on a substrate, and the first insulating film in which the first via is embedded Forming a second insulating film on the first insulating film; forming a plurality of openings formed on the first via in the second insulating film; and wiring grooves; Forming a conductive film on the second insulating film in which the opening and the wiring trench are formed; and removing the conductive film on the second insulating film and embedding in the plurality of openings A land having a plurality of columnar conductors made of the conductive film, wherein at least a part of the plurality of columnar conductors is electrically connected to the first via; and the conductor embedded in the wiring trench. Forming a wiring pattern made of a film, and embedding the land and the wiring pattern. Forming a third insulating film in which the second via electrically connected to the first via through the land is embedded on the second insulating film; Is provided.

  According to the disclosed wiring structure and the manufacturing method thereof, since one land is formed by an assembly of columnar conductors, dishing of the land during the damascene process can be suppressed. As a result, even when the land is formed by the conductive layer of the same level as the fine wiring pattern, it is possible to prevent the contact failure between the vias and improve the reliability and manufacturing yield of the semiconductor device. .

FIG. 1 is a schematic cross-sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 2 is an enlarged partial sectional view showing the structure of the semiconductor device according to the first embodiment. FIG. 3 is a perspective view showing a wiring structure of the semiconductor device according to the first embodiment. FIG. 4 is a plan view showing a wiring structure of the semiconductor device according to the first embodiment. FIG. 5 is a perspective view showing a typical stacked via structure. FIG. 6 is a diagram for explaining the mechanism of contact failure caused by dishing. FIG. 7 is a schematic diagram showing the structure of a land to which dishing measures are taken. FIG. 8 is a graph showing the relationship between the dishing amount and the land size. FIG. 9 is a plan view showing the shape of a land used for evaluating a contact failure between vias. FIG. 10 is a diagram for explaining the effect of the columnar conductors that are not arranged between the vias. FIG. 11 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 12 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 13 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 14 is a process cross-sectional view (No. 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 15 is a process cross-sectional view (No. 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 16 is a process cross-sectional view (No. 6) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 17 is a process cross-sectional view (No. 7) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 18 is a process cross-sectional view (No. 8) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 19 is a process cross-sectional view (No. 9) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 20 is a process cross-sectional view (No. 10) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 21 is a process cross-sectional view (No. 11) illustrating the method for manufacturing the semiconductor device according to the first embodiment. FIG. 22 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the second embodiment. FIG. 23 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the second embodiment.

[First Embodiment]
The semiconductor device and the manufacturing method thereof according to the first embodiment will be described with reference to FIGS.

  1 and 2 are sectional views showing the structure of the semiconductor device according to the present embodiment. FIG. 3 is a perspective view showing the wiring structure of the semiconductor device according to the present embodiment. FIG. 4 is a plan view showing the wiring structure of the semiconductor device according to the present embodiment. FIG. 5 is a perspective view showing a typical stacked via structure. FIG. 6 is a diagram for explaining the mechanism of contact failure caused by dishing. FIG. 7 is a schematic diagram showing the structure of a land to which dishing measures are taken. FIG. 8 is a graph showing the relationship between the dishing amount and the land size. FIG. 9 is a plan view showing the shape of a land used for evaluating a contact failure between vias. FIG. 10 is a diagram for explaining the effect of the columnar conductors that are not arranged between the vias. 11 to 21 are process cross-sectional views illustrating the method for manufacturing the semiconductor device according to the present embodiment.

  First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  As shown in FIG. 1, the semiconductor device according to the present embodiment includes a substrate 106 such as a printed circuit board, a silicon interposer 100 formed on the circuit substrate 106, and a semiconductor chip 104 formed on the silicon interposer 100. doing. The substrate 106 and the silicon interposer 100 are electrically connected via solder bumps 108. The silicon interposer 100 and the semiconductor chip 104 are electrically connected via solder bumps 102.

  The silicon interposer 100 includes a silicon substrate 10 in which through-hole vias 20 are embedded, and a multilayer wiring layer 110 formed on the silicon substrate 10. The multilayer wiring layer 110 includes a wiring structure in which vias are stacked via lands, a so-called stacked via structure. The stacked via structure is a structure in which vias and vias are relayed by a land, and a typical example is a through via that penetrates the silicon interposer 10 such as a power supply line.

  The land is sometimes called a pad. In this specification, in addition to the uppermost layer electrode (land 92) to which the solder bump is connected, a relay line (land 38, 56, 72, 82) for connecting the via to the via is also expressed as a land. To do. The land is a wiring structure formed by a wiring layer at the same level as the wiring pattern. A via is a wiring structure for electrically connecting different levels of wiring layers.

  In the example of the semiconductor device of FIG. 1, for example, a wiring structure in which lands 38, vias 40, lands 56, vias 66, lands 72, vias 76, lands 82, and lands 98 are sequentially stacked on the through-hole vias 20. Corresponds to the stacked via structure (see FIG. 2).

  Here, in the semiconductor device according to the present embodiment, of the lands forming the stacked via structure, the lands 56, 72, and 82 formed of the wiring layer at the same level as the wiring patterns 54, 70, and 80 are formed of the columnar conductor. It is formed by a set.

  FIG. 3 is a perspective view in which the vias 66 and 76 and the land 72 between the vias 66 and 76 are extracted from the stacked via structure of FIG. As shown in FIG. 3, the land 72 is formed by an assembly of a plurality of columnar conductors 112. The land 72 is formed over a region wider than the diameter of the vias 66 and 76 in consideration of misalignment between the via 66 and the via 76.

  FIG. 4 is a diagram illustrating an example of a plan view of the land 72. In the example of FIG. 4, the columnar conductors 120 are arranged in a matrix to form the lands 72. A land 72 is formed in a region having a diameter approximately twice the diameter of the vias 66 and 76.

  Although the land 72 has been described with reference to FIGS. 3 and 4, the same applies to the lands 56 and 82.

  Next, the reason why the lands 56, 72, and 82 are formed of a set of columnar conductors will be described with reference to FIGS.

  In a typical stacked via structure, for example, as shown in FIG. 5, vias 124 are stacked via lands 122 formed by one lump wiring structure.

  On the other hand, the wiring pattern for rewiring the build-up substrate is required to be miniaturized. In particular, a wiring forming process by a damascene method is desirable for forming a fine wiring having an L / S of less than 5/5 μm. Here, since the land is a wiring structure formed of a wiring layer at the same level as the wiring pattern, it is formed by the same wiring forming process as the wiring pattern.

  However, when a wiring structure having a larger area than a wiring pattern such as a land is formed by the damascene method, a phenomenon in which the center of the land is recessed from the peripheral edge when the wiring material is removed by polishing, a so-called phenomenon. Dishing occurs. For example, as shown in FIG. 6A, when the land 136 connected to the via 132 embedded in the insulating film 130 is formed, the surface of the land 136 is recessed from the surface of the insulating film 134. This is due to the pattern density dependency of the plating in which the plating film thickness is thicker in the region where the fine pattern is formed at higher density, and the polishing characteristic that the wider region is more easily scraped.

  If large dishing occurs in the land, for example, as shown in FIG. 6B, the bottom of the via 140 does not contact the land 136 when the via 140 embedded in the insulating film 138 is formed on the land 136. Occurs. As a result, a contact failure occurs in via connection, and the yield decreases.

  As a countermeasure against land dishing, there is a method of providing a dummy insulating pattern in the land. In this method, for example, as shown in FIG. 7A, a plurality of dummy columnar bodies 142 of the insulating film 134 are arranged in the area of the land 136 so as to alleviate dishing of the land 136.

 However, in the structure in which the dummy columnar body 142 is provided in the land 136, a phenomenon called erosion occurs in which the dummy columnar body 142 is also polished at the same time as the polishing of the land 136. For example, as shown in FIG. The surface of the land 136 is recessed together with the dummy columnar body 142. In particular, when an organic resin material that is more easily polished than an inorganic material is used for the insulating film 134, the erosion becomes larger. As a result, a contact failure similar to the case where the dummy columnar body 142 is not provided occurs.

  The stack via structure is a structure adopted on various package substrates including a resin substrate, and the thermal expansion / contraction of the resin often occurs due to the thermal history during the process. And, since the substrate is warped by such stress, the connection position between the land and the via may be displaced, so-called misalignment phenomenon may occur. Therefore, the land has a shape sufficiently larger than the via. It is necessary to keep. This background is also a factor that increases dishing and erosion.

  From such a viewpoint, in the wiring structure of the present embodiment, the lands 56, 72, and 82 are formed by a set of columnar conductors. Dishing can be suppressed by dividing the lands 56, 72, and 82 into a plurality of columnar conductors having a small area. Also, in the structure in which a plurality of columnar conductors are arranged in the insulating film, erosion does not occur unlike the case of FIG. As a result, depressions on the surfaces of the lands 56, 72, and 82 can be suppressed, and contact defects in via connection can be reduced.

  FIG. 8 is a graph showing the relationship between the dishing amount and the land diameter (land size). As shown in FIG. 8, the dishing amount of the land decreases as the land size decreases. In particular, when the land size is smaller than 100 μm, the dishing amount decreases rapidly, and when the land size is about 20 μm or less, dishing is almost eliminated.

  Table 1 summarizes the results of evaluating the relationship between the land structure, dishing amount (erosion amount), and connection contact rate.

  Land structures (a) to (f) correspond to FIGS. 9 (a) to (f). The structure (a) is a typical land structure in which the conductive layer 146 is disposed on the entire land formation region 144 (FIG. 9A). The structure (b) is a land structure in which a dummy columnar body 142 of an insulating film is provided in a conductive layer 146 disposed in the land formation region 144 (FIG. 9B). The structure (c) is a land structure in which conductive layers 146 having a diameter of 80 μmφ are arranged at an interval of 40 μm in the land formation region 144 (FIG. 9C). The structure (d) is a land structure in which conductive layers 146 having a diameter of 50 μmφ are arranged in the land formation region 144 at intervals of 25 μm (FIG. 9D). The structure (e) is a land structure in which conductive layers 146 having a diameter of 20 μmφ are arranged at an interval of 10 μm in the land formation region 144 (FIG. 9E). The structure (f) is a land structure in which conductive layers 146 having a diameter of 10 μmφ are arranged in the land formation region 144 at intervals of 5 μm (FIG. 9 (f)). The land formation region 144 was 200 μmφ.

  The connection contact ratio represents the ratio of the good evaluation of the connection between the land and the via among the 50 evaluation samples in which the via is formed on each land structure.

  As shown in Table 1, in the structures (c), (d), (e), and (f) in which the lands are formed by a collection of columnar conductors, the structure (a) in which the conductive layer 146 is arranged on one surface and the dummy columnar shape Compared with the structure (b) provided with the body 142, the dishing amount (erosion amount) could be reduced. As a result, in the structures (c), (d), (e), and (f), the connection contact ratio between the land and the via can be improved as compared with the structures (a) and (b). It was. In particular, in the structures (e) and (f) provided with a conductive layer having a diameter of 20 μmφ or less, the dishing amount can be significantly reduced to 0.12 μm or less, and the connection contact rate is also 100%.

  From the above evaluation results, it has been verified that the contact failure between the land and the via can be reduced by the wiring structure according to the present embodiment in which the land is formed by a collection of columnar conductors.

  From the results shown in Table 1, the diameter of the columnar conductor constituting the land is preferably 20 μmφ or less. By setting the diameter of the columnar conductor to 20 μmφ or less, dishing can be reduced and the occurrence of contact failure between the land and the via can be effectively suppressed.

  In addition, if the distance between the columnar conductors is too close, it substantially approximates the structure (a) in which the conductive layer 146 is disposed on one surface, and the effect of suppressing dishing is reduced. Is preferably about the radius of the columnar conductor. For example, when columnar conductors having a diameter of 20 μmφ are arranged, it is desirable that the interval between the columnar conductors be 10 μm or more.

  On the other hand, if the interval between the columnar conductors is too large, the number of columnar conductors connected to the vias decreases, and as a result, the contact resistance between the land and the via increases. It is desirable that the interval between the columnar conductors is appropriately set in consideration of the contact resistance value required between the land and the via.

  Note that the relationship between the dishing amount and the land size may be changed by changing the polishing conditions. It is desirable that the diameter and interval of the columnar conductor that can suppress the dishing amount be appropriately selected according to the polishing conditions.

  When the land is formed by a collection of columnar conductors, not all columnar conductors constituting the land are electrically connected to the vias. The columnar conductor connected to only one of the lower via and the upper via, and the columnar conductor not connected to both the lower via and the upper via are also included. If at least a part of all the columnar conductors constituting the land is connected to both the lower via and the upper via, electrical connection between the lower via and the upper via can be ensured.

  When a stress such as a thermal cycle is applied to the wiring structure, only the columnar conductor 154 connected to both exists between the lower via 150 and the upper via 152 as shown in FIG. 10A, for example. In this case, stress load concentrates on the columnar conductor 154. This increases the probability that a disconnection will occur between the lower via 150 and the upper via 152.

  On the other hand, when the columnar conductor 156 connected to only one of the lower via 150 and the upper via 152 exists around the columnar conductor 154, for example, as shown in FIG. 10B, the lower via 150 and the upper via 152 are provided. The stress load applied between the two is relaxed. Further, for example, as shown in FIG. 10C, when there is a columnar conductor 158 that is not connected to the lower via 150 and the upper via 152, the stress load applied between the lower via 150 and the upper via 152 is further alleviated. Is done.

  Next, the method for fabricating the semiconductor device according to the present embodiment will be explained with reference to FIGS.

  First, the silicon substrate 10 which becomes the base of the silicon interposer 22 is prepared (FIG. 11A).

  Next, an opening 12 is formed in the through-holvia 20 formation region of the silicon substrate 10 by photolithography and dry etching (FIG. 11B). The diameter of the opening 12 corresponds to the diameter of the through-hole via 20 to be formed, and is set to 200 μm, for example. The depth of the opening 12 is made deeper than the length of the through-hole via 20 to be formed. For example, when forming the through-hole via 20 having a length of 500 μm, the depth of the opening 12 is set to 500 μm or more.

  Next, a Ti film of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, sputtering, to form a Ti film adhesion layer 14.

  Next, a Cu film of, eg, a 100 nm-thickness is deposited on the adhesion layer 14 by, eg, sputtering to form a Cu film seed layer 16 (FIG. 11C).

  Next, a Cu film is grown by electrolytic plating using the seed layer 16 as a seed, and a Cu film 18 is formed on the adhesion layer 14 (FIG. 11D).

  Next, the Cu film 18 and the adhesion layer 14 on the silicon substrate 10 are removed by a CMP (Chemical Mechanical Polishing) method, and the adhesion layer 14 and the Cu film 18 are selectively left in the opening 12. (FIG. 11 (e)).

  Next, the silicon substrate 10 is polished by CMP until the Cu film 18 is exposed from the back surface side, and a through-hole via 20 composed of the adhesion layer 14 and the Cu film 18 embedded in the opening 12 is formed.

  In this manner, for example, the silicon substrate 10 in which the through-hole vias 20 having a diameter of 200 μm and a length of 500 μm are embedded is formed (FIG. 11F).

  The above-described method for forming the through-hole via 20 is an example, and the present invention is not limited to this.

  Next, a Ti film of, eg, a 20 nm-thickness is deposited on the silicon substrate 10 in which the through-hole vias 20 are buried by, eg, sputtering to form an adhesion layer 22 of the Ti film.

  Next, a Cu film of, eg, a 100 nm-thickness is deposited on the adhesion layer 22 by, eg, sputtering to form a Cu film seed layer 24 (FIG. 12A).

  Next, a photoresist film 26 of, eg, a 10 μm-thickness is formed on the seed layer 24 (FIG. 12B).

  Next, the photoresist film 26 is patterned by photolithography, and an opening 28 is formed in the photoresist film 26 to expose a region where a land 38 to be connected to the through-hole via 20 is to be formed (FIG. 12C). Although the diameter of the opening part 28 is not specifically limited, For example, you may be 300 micrometers.

  Next, a Cu film is grown by electrolytic plating using the seed layer 24 as a seed, and a Cu film 30 having a total film thickness of, for example, 5 μm is formed on the adhesion layer 24 in the opening 28 (FIG. 12D). . As an electrolytic plating solution for growing the Cu film 30, for example, an acidic copper sulfate plating solution can be applied.

  Next, for example, a cleaning process using a chemical solution such as NMP (N-methyl-2-pyrrolidone) or acetone is performed to remove the photoresist film 26 (FIG. 13A).

  Next, a photoresist film 32 of, eg, a 10 μm-thickness is formed on the entire surface (FIG. 13B).

  Next, the photoresist film 32 is patterned by photolithography, and an opening 34 is formed in the photoresist film 32 to expose a region where a via 40 to be connected to the Cu film 30 to be the land 38 is to be formed (FIG. 13C). )). Although the diameter of the opening part 28 is not specifically limited, For example, you may be 300 micrometers.

  Next, a Cu film is grown by electrolytic plating using the seed layer 24 and the Cu film 30 as seeds, and a Cu film 36 of, eg, a 6 μm-thickness is formed on the Cu film 30 in the opening 34 (FIG. 13D). )).

  Next, a cleaning process using a chemical such as NMP or acetone is performed to remove the photoresist film 32 (FIG. 14A).

Next, the seed layer 24 and the adhesion layer 22 in the region where the Cu films 36 and 30 are not formed are etched. Thereby, a land 38 made of the adhesion layer 22 and the Cu layer 30 and a via 40 made of the Cu layer 36 are formed (FIG. 14B). For etching Cu of the seed layer 24, for example, an etching solution such as calcium sulfate or ammonium peroxide can be used. For etching Ti of the adhesion layer 22, for example, an etching solution such as ammonium fluoride can be used. For etching Ti of the adhesion layer 22, for example, dry etching using a CF ₄ / O ₂ mixed gas or the like can be used.

  Next, a resin material such as polyimide or phenol resin is applied to the entire surface by, eg, spin coating to form an insulating film 42 having a film thickness of 11 μm, for example, so as to cover the via 40 (FIG. 14C).

  Next, the surface of the insulating film 42 is polished by about 1 μm by CMP to expose the upper surface of the via 40 from the insulating film 42 (FIG. 14D). When polishing the insulating film 42, for example, a slurry using alumina abrasive grains can be used.

  From this step onward, the multilayer wiring layer is formed. In this example, it is assumed that a wiring pattern having a wiring with a line width of 1 μm is formed, and typical values for the conditions such as film thickness are described here. To do.

  Next, a photosensitive permanent resist is applied on the insulating film 42 by, eg, spin coating to form an insulating film 44 having a thickness of 1 μm, for example (FIG. 15A).

  Next, the insulating film 44 is patterned by photolithography, and a predetermined opening for embedding a wiring material is formed in the insulating film 44. A wiring groove 46 having a predetermined pattern is formed in the formation region of the wiring pattern 54, and an assembly 48 of openings having a diameter of about 20 μmφ or less is formed in the formation region of the land 56 (FIG. 15B). . For example, openings having a diameter of 20 μmφ are arranged in a matrix at intervals of 10 μm in the formation region of the land 56 having a size of 200 μmφ.

  Next, a Ti film of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, sputtering, to form a Ti film adhesion layer 50 (FIG. 15C).

  Next, a Cu film of, eg, a 100 nm-thickness is deposited on the adhesion layer 50 by, eg, sputtering to form a seed layer (not shown) of the Cu film.

  Next, a Cu film is grown by electrolytic plating using the seed layer as a seed to form a Cu film 52 having a thickness of 3 μm, for example (FIG. 15D).

Next, the Cu film 52 and the adhesion layer 50 are polished by about 2 μm by CMP, and the Cu film 52 and the adhesion layer 52 on the surface of the insulating film 44 are removed. Thereby, a wiring layer embedded in the insulating film 44 is formed. The wiring layer includes a wiring pattern 54 formed of the adhesion layer 50 and the Cu film 52 embedded in the wiring groove 46, and a land 56 formed of the adhesion layer 50 and the Cu film 52 embedded in the opening assembly 48. (FIG. 16A). For polishing the Cu film 52, for example, a slurry using H ₂ O ₂ or ammonium persulfate as an oxidizing agent can be applied. For polishing the adhesion layer 50 made of Ti, for example, a slurry containing H ₂ O ₂ and silica abrasive grains can be applied.

  Next, a photosensitive permanent resist is applied on the insulating film 44 in which the wiring pattern 54 and the land 56 are embedded, for example, by a spin coating method to form an insulating film 58 having a thickness of 5 μm, for example (FIG. 16B). .

  Next, the insulating film 58 is patterned by photolithography to form a via hole 60 in a region where the via 66 of the insulating film 58 is to be formed (FIG. 16C). For example, a via hole 60 having a diameter of 100 μmφ is formed on the land 56.

  Next, a Ti film of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, sputtering, to form a Ti film adhesion layer 62 (FIG. 16D).

  Next, a Cu film of, eg, a 100 nm-thickness is deposited on the adhesion layer 62 by, eg, sputtering to form a Cu film seed layer (not shown).

  Next, a Cu film is grown by electrolytic plating using the seed layer as a seed to form a Cu film 64 having a thickness of 10 μm, for example (FIG. 17A).

  Next, the Cu film 64 and the adhesion layer 62 are polished by about 10 μm by CMP, and the Cu film 64 and the adhesion layer 62 on the surface of the insulating film 58 are removed. Thereby, a via 66 embedded in the via hole 60 is formed (FIG. 17B).

  15A to 17B, the insulating film 68, the wiring pattern 70 embedded in the insulating film 68, and the land 72 are formed on the insulating film 58 in which the via 66 is embedded. Then, the insulating film 74 and the via 76 embedded in the insulating film 74 are formed.

  Similarly to the steps shown in FIGS. 15A to 16A, the insulating film 78, the wiring pattern 80 embedded in the insulating film 78, and the land 82 are formed on the insulating film 74 in which the via 76 is embedded. Is formed (FIG. 17C).

  Next, a resin material is applied on the insulating film 78 in which the wiring patterns 80 and the lands 82 are embedded, for example, by spin coating to form an insulating film 84 having a thickness of, for example, 5 μm (FIG. 18A).

  Next, the insulating film 84 is patterned by photolithography and dry etching, and a via hole 86 reaching the wiring pattern 80 and the land 82 is formed in the insulating film 84 (FIG. 18B).

  Next, a Ti film of, eg, a 20 nm-thickness is deposited on the entire surface by, eg, sputtering, to form a Ti film adhesion layer 88 (FIG. 18C).

  Next, a Cu film of, eg, a 100 nm-thickness is deposited on the adhesion layer 88 by, eg, sputtering to form a Cu film seed layer (not shown).

  Next, a photoresist film 90 of, eg, a 10 μm-thickness is formed on the seed layer (FIG. 19A).

  Next, the photoresist film 90 is patterned by photolithography, and an opening 92 is formed in the photoresist film 90 so as to expose a region where a land 94 to be connected to the wiring pattern 80 and the land 82 through the via hole 86 is exposed. FIG. 19 (b)).

  Next, a Cu film is grown by electrolytic plating using the seed layer as a seed, and a Cu film 94 having a total film thickness of, for example, 5 μm is formed on the adhesion layer 24 in the via hole 86 and the opening 92 (FIG. 19C). )).

  Next, for example, a cleaning process using a chemical such as NMP or acetone is performed to remove the photoresist film 90 (FIG. 20A).

  Next, the seed layer and the adhesion layer 88 in the region where the Cu film 94 is not formed are etched (FIG. 20B).

  Next, for example, a 500 nm-thickness Au film and a 200 nm-thickness NiP alloy film are formed on the surface of the Cu film 94 by electroplating, and the NiP / Au layer 96 is formed. Thereby, a land 98 made of the adhesion layer 88, the Cu layer 94 and the NiP / Au layer 96 and connected to the wiring pattern 80 or the land 82 via the via hole 86 is formed.

  In this way, the silicon interposer 100 in which the multilayer wiring layer is formed on the silicon substrate 10 in which the through-hole via 20 is embedded is formed (FIG. 20C).

  Next, the semiconductor chip 104 is mounted on the land 98 of the silicon interposer 100 formed in this way via the solder bumps 102 (FIG. 21A).

  Next, the silicon interposer 100 on which the semiconductor chip 104 is mounted is mounted on the substrate 106 such as a printed circuit board via the solder bumps 108 (FIG. 21B).

  Thus, according to the present embodiment, since one land of the stacked via structure is formed by an aggregate of columnar conductors, dishing of the land during the damascene process can be suppressed. As a result, even when the land is formed by the conductive layer of the same level as the fine wiring pattern, it is possible to prevent the contact failure between the vias and improve the reliability and manufacturing yield of the semiconductor device. .

[Second Embodiment]
A method for fabricating a semiconductor device according to the second embodiment will be described with reference to FIGS. The same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment shown in FIGS. 1 to 21 are denoted by the same reference numerals, and description thereof is omitted or simplified.

  22 and 23 are process cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  In the semiconductor device manufacturing method according to the first embodiment, the damascene process is used to form the vias 66 and 76. However, the above-described dishing and erosion are common problems in the damascene process, and dishing and erosion may occur if the diameters of the vias 66 and 76 are increased. The vias 66 and 76 may not require fine patterning as required for the wiring patterns 54, 70, and 80. In such a case, the vias 66 and 76 may be formed by a semi-additive method.

  The via can be formed by the semi-additive method, for example, as follows. Here, the via 66 will be described as an example, but the same applies to the via 76.

  First, in the same way as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 11A to 16A, for example, the wiring pattern 54 and the via 56 embedded in the insulating film 44 are formed (FIG. 11). 22 (a)).

  Next, a Ti film of, eg, a 20 nm-thickness is deposited on the insulating film 44 in which the wiring pattern 54 and the via 56 are embedded, for example, by sputtering, to form a Ti film adhesion layer 62.

  Next, a Cu film of, eg, a 100 nm-thickness is deposited on the adhesion layer 62 by, eg, sputtering to form a seed layer 63 of the Cu film (FIG. 22B).

  Next, a photoresist film 65 is formed on the seed layer 63 by, eg, spin coating.

  Next, the photoresist film 65 is patterned by photolithography to form an opening 67 in a region where the via 66 of the photoresist film 65 is to be formed (FIG. 22C). For example, an opening 67 having a diameter of 100 μmφ is formed on the land 56.

  Next, a Cu film is grown by electroplating using the seed layer 63 as a seed, and a Cu film 64 having a total film thickness of 10 μm, for example, is formed on the adhesion layer 62 in the opening 67 (FIG. 22D). .

  Next, a cleaning process using a chemical solution such as NMP or acetone is performed to remove the photoresist film 65 (FIG. 23A).

  Next, the seed layer 63 and the adhesion layer 62 in the region where the Cu film 94 is not formed are etched. Thus, the via 66 connected to the wiring pattern 54 or the land 56 is formed on the insulating film 44 (FIG. 23B).

  Next, a resin material is applied on the insulating film 44 with the vias 66 formed by, for example, spin coating to form an insulating film 58 having a thickness of 5 μm, for example (FIG. 23C).

  Next, the surface of the insulating film 58 is polished by CMP to expose the upper surface portion of the via 66. Thus, the via 66 embedded in the insulating film 58 is formed.

  Thereafter, the semiconductor device is completed in the same manner as the semiconductor device manufacturing method according to the first embodiment shown in FIGS. 17C to 21B, for example.

  As described above, according to the present embodiment, by using the semi-additive method for forming the via, it is possible to use photolithography with a loose rule, so that the manufacturing cost of the semiconductor device can be reduced.

[Modified Embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, in the first embodiment, the lands 56, 72, and 82 are formed of aggregates of columnar conductors, but the lands 56, 72, and 82 are not necessarily formed when a fine wiring pattern is not formed by the same level of conductive layer. Is not required to be formed of an aggregate of columnar conductors. When a fine wiring pattern is not formed by a conductive layer at the same level as the land, it is not necessary to use a damascene method desirable for fine processing, and a large-area land 56, 72, using a semi-additive method that is not affected by dishing. 82 can also be formed. The land forming method by the semi-additive method is the same as the manufacturing method of the via 66 in the second embodiment. Note that the land 38 and the land 98 can be exemplified as the land in which the fine wiring pattern is not formed by the same level of the conductive layer.

  From the results shown in FIG. 8, it is considered that a via having a diameter of at least 50 μm or more, preferably more than 20 μm, is preferably formed by an aggregate of columnar conductors having a diameter of 20 μmφ or less. A via having a diameter of less than 50 μm, preferably 20 μm or less, is not necessarily formed by an aggregate of columnar conductors having a diameter of 20 μmφ or less.

  In the above embodiment, the case where the columnar conductors are arranged in an orthogonal lattice pattern in the land formation region is shown, but it is not always necessary to form the orthogonal lattice arrangement. For example, the columnar conductors may be arranged in a triangular lattice shape.

  In the above embodiment, the planar shape of the columnar conductor forming the land is circular. However, the planar shape is not necessarily circular, and may be a polygonal shape such as a triangle or a square.

  In the first and second embodiments, the example of application to the rewiring of the silicon interposer has been described. However, the present invention can be applied not only to the rewiring of the silicon interposer but also to various wiring structures. For example, the present invention can be applied to a multilayer wiring structure formed on a circuit board such as a package board or a wafer level package (WLP).

  In addition, the structure, constituent materials, manufacturing conditions, and the like of the semiconductor device described in the above embodiment are merely examples, and can be appropriately modified or changed according to technical common sense of those skilled in the art.

  Regarding the above embodiment, the following additional notes are disclosed.

(Supplementary note 1) a first insulating film formed on a substrate;
A first via embedded in the first insulating film;
A second insulating film formed on the first insulating film in which the first via is embedded;
A land embedded in the second insulating film and electrically connected to the first via;
A wiring pattern embedded in the second insulating film and spaced apart from the land;
A third insulating film formed on the second insulating film in which the land and the wiring pattern are embedded;
A second via embedded in the third insulating film and electrically connected to the land;
The land has a plurality of columnar conductors, and at least a part of the plurality of columnar conductors is electrically connected to the first via and the second via. Construction.

(Appendix 2) In the wiring structure described in Appendix 1,
The columnar conductor has a diameter of 20 μmφ or less.

(Appendix 3) In the wiring structure described in Appendix 1 or 2,
An interval between the plurality of columnar conductors is equal to or greater than a radius of the columnar conductors.

(Appendix 4) In the wiring structure according to any one of appendices 1 to 3,
The land has a diameter of 50 μmφ or more.

(Appendix 5) In the wiring structure according to any one of appendices 1 to 4,
The wiring structure, wherein the wiring pattern has a wiring width of 5 μm or less.

(Appendix 6) A step of forming a first insulating film in which a first via is embedded on a substrate;
Forming a second insulating film on the first insulating film in which the first via is embedded;
Forming a plurality of openings formed on the first via and a wiring groove in the second insulating film;
Forming a conductive film on the second insulating film in which the plurality of openings and wiring grooves are formed;
The conductive film on the second insulating film is removed, and a plurality of columnar conductors made of the conductive film embedded in the plurality of openings are provided, and at least a part of the plurality of columnar conductors is the Forming a land electrically connected to the first via and a wiring pattern made of the conductive film embedded in the wiring groove;
A third insulating film in which a second via electrically connected to the first via via the land is embedded on the second insulating film in which the land and the wiring pattern are embedded. A method for manufacturing a wiring structure, comprising: forming a wiring structure.

(Supplementary note 7) In the method for manufacturing a wiring structure according to supplementary note 6,
The columnar conductor has a diameter of 20 μmφ or less. A method of manufacturing a wiring structure, wherein:

(Additional remark 8) In the manufacturing method of the wiring structure of Additional remark 6 or 7,
The space between the plurality of columnar conductors is equal to or greater than the radius of the columnar conductors.

(Supplementary note 9) In the wiring structure according to any one of supplementary notes 6 to 8,
The method for manufacturing a wiring structure, wherein the land has a diameter of 50 μmφ or more.

(Appendix 10) In the wiring structure according to any one of appendices 6 to 9,
The method of manufacturing a wiring structure, wherein the wiring pattern has a wiring width of 5 μm or less.

(Appendix 11) In the method for manufacturing a wiring structure according to any one of appendices 6 to 10,
The step of forming the third insulating film includes
Forming a seed layer on the second insulating film in which the land and the wiring pattern are embedded;
Forming a resist film on the seed layer having an opening that exposes a region where the second via is to be formed;
Forming a conductive film on the seed layer in the opening by electroplating using the seed layer as a seed and the resist film as a mask;
Removing the resist film after forming the conductive film;
Removing the seed layer in the region covered with the resist film and forming the second via made of the conductive film and the seed layer;
And a step of forming the third insulating film on the second insulating film in which the second via is formed. A method for manufacturing a wiring structure, comprising:

DESCRIPTION OF SYMBOLS 10 ... Silicon substrate 12, 28, 34, 67, 92 ... Opening part 14, 22, 50, 62, 88 ... Adhesion layer 16, 24, 63 ... Seed layer 18, 30, 36, 52, 64, 94 ... Cu film | membrane 20 ... through-hole vias 26, 32, 65, 90 ... photoresist films 38, 56, 72, 82, 94, 98 ... lands 40, 66, 76 ... vias 42, 44, 58, 68, 74, 78, 84 ... Insulating film 46 ... Wiring groove 48 ... Aggregation 54, 70, 80 ... Wiring pattern 60, 86 ... Via hole 96 ... NiP / Au layer 100 ... Silicon interposer 102, 108 ... Solder bump 104 ... Semiconductor chip 106 ... Substrate 110 ... multilayer wiring layers 112, 120, 154, 156, 158 ... columnar conductors 122, 136 ... lands 124, 132, 140 ... vias 130, 134, 138 Insulating film 142 ... dummy pillars 144 ... land forming region 146 ... conductive layer 150 ... lower via 152 ... upper via

Claims (6)

A first insulating film formed on the substrate;
A first via embedded in the first insulating film;
A second insulating film formed on the first insulating film in which the first via is embedded;
A land embedded in the second insulating film and electrically connected to the first via;
A wiring pattern embedded in the second insulating film and spaced apart from the land;
A third insulating film formed on the second insulating film in which the land and the wiring pattern are embedded;
A second via embedded in the third insulating film and electrically connected to the land;
The land has a plurality of columnar conductors, and at least a part of the plurality of columnar conductors is electrically connected to the first via and the second via. Construction. The wiring structure according to claim 1,
The columnar conductor has a diameter of 20 μmφ or less. In the wiring structure according to claim 1 or 2,
An interval between the plurality of columnar conductors is equal to or greater than a radius of the columnar conductors. The wiring structure according to any one of claims 1 to 3,
The land has a diameter of 50 μmφ or more. Forming a first insulating film embedded with a first via on a substrate;
Forming a second insulating film on the first insulating film in which the first via is embedded;
Forming a plurality of openings formed on the first via and a wiring groove in the second insulating film;
Forming a conductive film on the second insulating film in which the plurality of openings and wiring grooves are formed;
The conductive film on the second insulating film is removed, and a plurality of columnar conductors made of the conductive film embedded in the plurality of openings are provided, and at least a part of the plurality of columnar conductors is the Forming a land electrically connected to the first via and a wiring pattern made of the conductive film embedded in the wiring groove;
A third insulating film in which a second via electrically connected to the first via via the land is embedded on the second insulating film in which the land and the wiring pattern are embedded. And a step of forming the wiring structure. In the manufacturing method of the wiring structure according to claim 5,
The step of forming the third insulating film includes
Forming a seed layer on the second insulating film in which the land and the wiring pattern are embedded;
Forming a resist film on the seed layer having an opening that exposes a region where the second via is to be formed;
Forming a conductive film on the seed layer in the opening by electroplating using the seed layer as a seed and the resist film as a mask;
Removing the resist film after forming the conductive film;
Removing the seed layer in the region covered with the resist film and forming the second via made of the conductive film and the seed layer;
And a step of forming the third insulating film on the second insulating film in which the second via is formed. A method for manufacturing a wiring structure, comprising:

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