JP2010147203A - Exposure method and method of manufacturing device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid a reduction in accuracy of superposition due to thermal expansion of a wafer. <P>SOLUTION: At step 206, the wafer is irradiated with illumination light of a quantity which is 1/N a reference quantity to expose a plurality of divided regions arrayed on the wafer. The above operations are repeated N times. The number N of times by which the operations are repeated is determined based on a position alignment accuracy (accuracy of superposition) of patterns or a time taken for pattern transfer. Thus, the reduction in accuracy of superposition of patterns or a reduction in throughput can be avoided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an exposure method and a device manufacturing method, and more particularly to an exposure method for forming a pattern on an object by irradiating a sensitive layer on the surface of the object with an energy beam, and a device manufacturing method using the exposure method. .

  Conventionally, in a photolithography process for manufacturing a semiconductor element, a liquid crystal display element, or the like, a photomask or a reticle (hereinafter, collectively referred to as “reticle”) pattern is exposed to a photosensitive agent such as a photoresist via a projection optical system. A projection exposure apparatus, such as a step-and-repeat type projection exposure apparatus (so-called stepper), or a step-and- A scanning projection exposure apparatus (a so-called scanning stepper (also called a scanner)) or the like is used.

  In this type of projection exposure apparatus, when the amount of illumination light applied to the wafer is large, pattern alignment accuracy (including overlay accuracy of patterns in a plurality of layers formed on the wafer) may be reduced. It is known (see, for example, Patent Document 1). One of the reasons may be that the wafer is thermally expanded by irradiation of illumination light, that is, the wafer is locally thermally expanded, and the pattern is transferred to the deformed partitioned area. In view of this, it is conceivable to maintain a certain alignment accuracy by cooling the wafer with a waiting time each time a pattern is transferred to one partition area. However, if this is done, there is a risk that throughput will be reduced more than necessary.

Japanese Patent Laid-Open No. 10-50588

  The present invention has been made under the circumstances described above. From the first viewpoint, the present invention is an exposure method in which an object is exposed by irradiating an energy beam, and a reference amount is applied to a sensitive layer formed on the object. Irradiating a lesser amount of the energy beam and sequentially exposing a plurality of locations on the object until the irradiation amount of the energy beam on the sensitive layer reaches the reference amount. The exposure method includes a step of forming the plurality of pattern regions in which a pattern is formed on the object by repeating the number of times determined based on at least one of alignment accuracy and throughput.

  According to this, it is possible to irradiate the sensitive layer formed on the object with an energy beam smaller than the reference amount and sequentially expose a plurality of locations on the object. A plurality of pattern regions in which a pattern is formed on the object are formed by repeating the number of times until the amount is reached. Therefore, repeated exposure is always performed in a state where there is no influence of the local thermal expansion of the wafer or it is sufficiently small. As a result, it is possible to avoid a decrease in pattern alignment accuracy (including overlay accuracy) as described above. Here, the number of repetitions is determined based on at least one of the required pattern alignment accuracy and throughput. Therefore, it is possible to avoid a decrease in pattern alignment accuracy and / or suppress a decrease in throughput.

  According to a second aspect of the present invention, there is provided a step of forming the plurality of pattern regions in which a pattern is formed on an object using the exposure method of the present invention; and the object in which the plurality of pattern regions are formed. And a step of developing the device.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 6B.

  FIG. 1 shows a schematic configuration of an exposure apparatus 100 according to an embodiment. The exposure apparatus 100 is a step-and-repeat projection exposure apparatus (so-called stepper). As will be described later, in the present embodiment, a projection optical system PL is provided. In the following, a direction parallel to the optical axis AX of the projection optical system PL is a Z-axis direction, and in a two-dimensional plane orthogonal to the Z-axis direction. In FIG. 1, the left and right direction on the paper surface is defined as the X axis direction, and the direction orthogonal to the paper surface is defined as the Y axis direction.

  The exposure apparatus 100 holds an illumination system IOP, a reticle stage (reticle holder) RST that holds a reticle R, a projection optical system PL that projects an image of a pattern formed on the reticle R on the wafer W, and a wafer 2. An XY stage 20 that moves on a dimensional plane (within the XY plane), a drive system 22 that drives the XY stage 20, a control system that controls these, and the like are provided.

  The illumination system IOP includes, for example, a light source composed of an ultra-high pressure mercury lamp that outputs an ultraviolet bright line (g-line, i-line, etc.), an elliptical mirror, a reflection mirror, a wavelength filter, a fly-eye integrator, a relay lens system, and a variable field of view. An illumination optical system including a diaphragm (reticle blind), a bending mirror, a condenser lens, and the like is included. A shutter for closing and opening the optical path is disposed in the vicinity of the second focal point of the elliptical mirror. Details of such an illumination system are disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-146732. In the illumination system, the light emitted from the light source passes through the wavelength filter to become the illumination light IL for exposure, and the illumination light IL is adjusted to a luminous flux having a uniform illuminance distribution by a fly eye integrator, and then the variable field of view. By passing through the stop, the rectangular illumination area on the reticle R is illuminated with substantially uniform illuminance.

  Reticle stage RST is arranged below illumination system IOP in FIG. 1 (on the −Z side). On reticle stage RST, reticle R is held by suction via a vacuum chuck (not shown) or the like. Reticle stage RST can be finely driven in a rotation direction (θz direction) around the X axis direction, the Y axis direction, and the Z axis by a drive system (not shown). Thus, reticle stage RST can position reticle R (reticle alignment) in a state where the center of the pattern of reticle R (reticle center) substantially coincides with optical axis AXp of projection optical system PL. FIG. 1 shows a state in which this reticle alignment is performed.

  Projection optical system PL is arranged below reticle stage RST in FIG. 1 (on the −Z side) so that its optical axis AXp is parallel to the Z axis. Here, the projection optical system PL is a double-sided telecentric reduction system, and a refractive optical system (not shown) comprising a plurality of lens elements arranged at a predetermined interval along a direction parallel to the optical axis AXp is used. Yes. Among the plurality of lens elements, a plurality of specific lens elements are controlled by an imaging characteristic correction controller (not shown) based on a command from the main controller 28, and the projection optical system PL thereby has its optical characteristics. For example, magnification, distortion, coma aberration, and field curvature are adjusted (including imaging characteristics).

  The projection magnification of the projection optical system PL is, for example, 1/5 (or 1/4). For this reason, when the reticle R is uniformly illuminated by the pulse illumination light IL, the pattern image of the reticle R is reduced and projected onto the exposed area on the wafer W coated with the photoresist. Thereby, a reduced image of the pattern of the reticle R is transferred onto the wafer W.

  The XY stage 20 is disposed below (-Z side) in FIG. 1 of the projection optical system PL, and freely moves in the XY plane along the upper surface of a base (not shown). A wafer table 18 is mounted on the XY stage 20, and a wafer W is held on the wafer table 18 by vacuum suction or the like via a wafer holder (not shown).

  The wafer table 18 is also called a Z / tilt stage, and minutely drives the wafer holder holding the wafer W in the Z-axis direction and the tilt direction with respect to the XY plane. A movable mirror 24 is provided on the upper surface of the wafer table 18. A laser interferometer 26 is provided facing the reflecting surface of the movable mirror 24. The laser interferometer 26 irradiates the movable mirror 24 with a laser beam and receives the reflected light, thereby measuring the position of the wafer table 18 in the XY plane. Actually, an X moving mirror having a reflecting surface orthogonal to the X axis and a Y moving mirror having a reflecting surface orthogonal to the Y axis are provided, and the position in the X axis direction is measured correspondingly. And an X laser interferometer for measuring a position in the Y-axis direction. However, in FIG. 1, these are shown as the moving mirror 24 and the laser interferometer 26. Note that the X laser interferometer and the Y laser interferometer are multi-axis interferometers having a plurality of measurement axes, and yawing (rotation around the Z axis (θz rotation)) and pitching (rotation around the X axis (rotation around the X axis ( θx rotation)) and rolling (rotation around the Y axis (θy rotation)) can also be measured. Therefore, the laser interferometer 26 can measure position information of the wafer table 18 in the five-degree-of-freedom directions (X, Y, θz, θy, and θx directions).

  The position information measured by the laser interferometer 26 is supplied to the main controller 28. The main controller 28 positions the wafer table 18 by controlling the XY stage 20 via the drive system 22 based on the position information.

  In addition, the exposure apparatus 100 of the present embodiment is provided with a focus sensor AFS that measures the position and inclination of the surface of the wafer W in the Z-axis direction. The focus sensor AFS includes, for example, an oblique incidence type multipoint focal position detection system having a light transmission system 50a and a light reception system 50b disclosed in US Pat. No. 5,502,311 and the like. The measurement result of the focus sensor AFS is also supplied to the main controller 28. The main controller 28 drives the wafer table 18 in the Z-axis direction, θx direction, and θy direction via the drive system 22 according to the measurement result, and the position and inclination of the wafer W with respect to the optical axis direction of the projection optical system PL. To control.

  As described above, by driving the wafer table 18, the position of the wafer W can be controlled in the directions of five degrees of freedom (X, Y, Z, θx, θy). The position of the wafer W in the remaining θz direction (yawing) is controlled by rotating at least one of reticle stage RST and wafer table 18 in accordance with the yawing of wafer table 18 measured by laser interferometer 26. The

  Further, a reference plate FP is fixed on the wafer table 18 so that the surface thereof is the same height as the surface of the wafer W. On the surface of the reference plate FP, various reference marks including reference marks used for baseline measurement of an alignment detection system, which will be described later, are formed.

  Furthermore, in the present embodiment, an off-axis alignment detection system AS is provided on the side surface of the projection optical system PL. As the alignment detection system AS, for example, an image processing type FIA (Field Image Alignment) system is used. The alignment detection system AS can measure the position of the reference mark formed on the reference plate FP and the alignment mark formed on the wafer W in the two-dimensional direction (X-axis and Y-axis directions).

  In the present embodiment, the main controller 28 performs fine alignment or the like that accurately measures the position of each exposed region on the wafer using the alignment detection system AS. In addition, as the alignment detection system AS, for example, an alignment sensor that irradiates a target mark with coherent detection light and detects two diffracted lights (for example, the same order) generated from the target mark alone, Alternatively, it can be used in combination with an FIA system or the like.

  The alignment control device 16 performs A / D conversion on the output signal DS from each alignment sensor constituting the alignment detection system AS, calculates the converted signal, and detects the mark position. This detection result is supplied from the alignment controller 16 to the main controller 28.

  In addition, the exposure apparatus 100 of the present embodiment is provided with a pair of reticle alignment detection systems (not shown) above the reticle R. The pair of reticle alignment detection systems are, for example, a reticle mark on the reticle R or a reference mark on the reticle stage RST via the projection optical system PL as disclosed in US Pat. No. 5,646,413. (Neither shown) and a TTR (Through The Reticle) alignment system for simultaneously observing the mark on the reference plate FP. The detection signal of the reticle alignment detection system is supplied to the main controller 28 via the alignment controller 16.

  The control system is mainly composed of a main control device 28 composed of a microcomputer or the like for comprehensively controlling the entire device.

  Here, when the irradiation amount of the illumination light IL on the wafer is large, pattern alignment accuracy (accuracy of alignment between patterns formed in a plurality of shot regions formed in the same layer, compared to the case where the illumination light IL is small, In addition, the overlay accuracy of patterns in a plurality of layers formed on the wafer (including the overlay accuracy hereinafter) decreases. Here, the irradiation amount of the illumination light IL on the wafer can be variously defined. Here, the product of the dose amount of the illumination light IL (amount per unit area) and the transmittance of the reticle is defined as the irradiation amount of the illumination light IL. Defined as quantity.

  FIG. 2A shows the surface of the wafer W when the irradiation amount of the illumination light IL is small. Points in FIG. 2A, for example, points Pa and Pb, indicate the center of the partition area (shot area). FIG. 2A shows a state in which the illumination light IL is irradiated to the partitioned area Sa, that is, a state in which the partitioned area Sa is being exposed. In FIG. 2A, a partitioned area Sb adjacent to the partitioned area Sa is a partitioned area to be exposed next to the partitioned area Sa. In the state shown in FIG. 2A, the partition regions Sa and Sb are not deformed due to thermal expansion, and the designed rectangular shape is maintained.

  On the other hand, FIG. 2B shows the surface of the wafer W when the irradiation amount of the illumination light IL is larger than that shown in FIG. FIG. 2B shows a state where the illumination light IL is applied to the partitioned area Sa ′, that is, a state where the partitioned area Sa ′ is being exposed. In FIG. 2B, a partitioned area Sb ′ adjacent to the partitioned area Sa ′ is a partitioned area that is to be exposed next to the partitioned area Sa ′. As shown in FIG. 2B, the irradiation of the illumination light IL causes the wafer W to expand locally and isotropically around the center Pa ′ of the partitioned area Sa ′, and thereby the partitioned area Sa. ', Sb' is deformed (locally deformed). In FIG. 2B, the design shapes (rectangular shapes) of the partitioned areas Sa ′ and Sb ′ are indicated by broken lines. Therefore, in the next exposure of the partitioned area Sa ′, the reticle pattern is transferred to the deformed partitioned area Sb ′ in a shape corresponding to the designed shape (rectangular shape).

  FIG. 2C shows the surface of the wafer W after the exposure for all the partitioned areas in the case shown in FIG. 2B (when the irradiation amount of the illumination light IL is relatively large). ing. The pattern transferred to the partition area deformed as described above is cooled by the wafer W and the local deformation is recovered, so that the stepping direction (for example, + X with respect to the partition area aligned in the X-axis direction including the partition area S ′) The center of the pattern is shifted in the reverse direction (−X direction) from the center P ′ of the partition area. In this manner, pattern overlay deviation (pattern deviation of the pattern itself and deviation from the design exposure position) occurs. Furthermore, since the thermal expansion of the wafer W depends on the irradiation amount (intensity and irradiation time) of the illumination light IL, the thermal expansion coefficient of the wafer W, the heat dissipation, and the like, the pattern overlay deviation has a certain systematic property (for example, However, it occurs almost randomly.

  In the exposure apparatus 100 of the present embodiment, illumination sufficient to form a resist image of a pattern when a wafer is developed after exposure in order to avoid a decrease in reticle pattern overlay accuracy due to thermal expansion as described above. A pattern is formed on the wafer by repeatedly exposing (multiple exposure) the wafer with illumination light IL having an irradiation amount smaller than the irradiation amount of light IL (that is, resist sensitivity of resist applied to the wafer surface; also referred to as a reference amount). An exposure method for transferring (forming) is employed.

  Specifically, in the present embodiment, the amount of the illumination light IL smaller than the reference amount is 1 / N of the reference amount, and the exposure process with the exposure amount 1 / N of the reference amount is repeated N times. As a result, the pattern is transferred onto the wafer.

  Next, the procedure of the exposure method in the present embodiment will be described with reference to the flowchart shown in FIG. This flowchart shows an outline of a processing algorithm performed by the CPU in the main controller 28. Here, it is assumed that exposure is performed on a predetermined number of wafers.

  First, at step 200, main controller 28 loads reticle R onto reticle stage RST using a reticle loader (not shown). Then, main controller 28 performs preparatory work such as reticle alignment and measurement of the baseline of alignment detection system AS, and adjustment of the irradiation amount of illumination light IL.

In the next step 202, the main controller 28 exchanges the wafer on the wafer table 18 using a wafer exchange mechanism (not shown). However, if there is no wafer on the wafer table 18, the wafer W is simply loaded onto the wafer table 18. Here, the wafer W is exposed to at least one layer to form a plurality of, for example, 45 partition regions S _{1 to} S ₄₅ (see FIG. 4), and a photoresist is applied to the surface thereof. Thus, it is assumed that a resist layer (sensitive layer) is formed. In addition, it is assumed that at least one alignment mark (base mark) is attached to each partition region S _j (j = 1 to 45). Further, main controller 28 sets 1 as a counter i representing the number of times of exposure for transferring (forming) a pattern onto wafer W as an initial setting (i ← 1).

In the next step 204, the main controller 28 uses the alignment detection system AS to position coordinates of a specific plurality of alignment marks (sample marks) among the plurality of alignment marks (base marks) formed on the wafer W. Enhanced to calculate array coordinates in the XY plane of the partition regions S _{1 to} S ₄₅ by statistical calculation using, for example, the least square method disclosed in US Pat. No. 4,780,617 and the like -Perform global alignment (EGA). Here, at the time of EGA, the main controller 28 moves the XY stage 20 via the drive system 22 based on the position information measured by the laser interferometer 26, so that a plurality of sample marks on the wafer W are obtained. Are sequentially positioned and detected within the detection field of the alignment detection system AS. Then, main controller 28 detects the X and Y position coordinates of each sample mark based on the detection center detected by alignment detection system AS, and measurement information of laser interferometer 26 at the time of detection (of wafer table 18). XY position coordinates in the stage coordinate system of each sample mark are calculated based on (X, Y position coordinates).

In the next step 206, the main controller 28 performs the i-th (here, the first) exposure for all 45 partitioned areas on the wafer in the order shown in FIG. Specifically, the main controller 28 determines the driving system based on the positional information of the wafer table WTB measured by the laser interferometer 26, the array coordinates of each partition area obtained by the EGA, and the measurement result of the baseline. 22, the exposure center (optical axis AXp) is sequentially set to the center of the partitioned area numbered 1, 2, 3,..., 44, 45 shown in FIG. Position to. Then, each time the positioning is performed, the main control device 28 sends an amount smaller than the reference amount, here 1 / N of the reference amount (N is 2 or more) to each partition region S _j via the reticle R and the projection optical system PL. (Integer) illumination light IL is irradiated. In this way, the illumination light IL having an amount 1 / N of the reference amount is irradiated onto all the partitioned regions, and the pattern of the reticle R is projected in a reduced scale. However, in this case, since the intensity of the illumination light is 1 / N of the reference amount, a latent image of the pattern is not formed, and a resist image is not formed even if the wafer W is developed after the first exposure. The same applies after the second to (N-1) th exposure.

  In step 208, main controller 28 checks whether or not N exposures have been completed. Here, since i (= 1) ≠ N, the process proceeds to step 210.

  In step 210, main controller 28 increments counter i by 1 (i ← i + 1), and returns to step 204.

  Then, main controller 28 determines until the determination in step 208 is affirmed, that is, until the exposure of N times is completed and the amount of illumination light IL applied to the resist layer (sensitive layer) reaches the reference amount. Steps 204, 206, 208 and 210 are repeated. Thereby, the second to Nth exposures to the wafer W are performed in the same manner as the first exposure described above. In each exposure, as described above, the reference areas 1, 2, 3,..., 44, 45 shown in FIG. 4 are sequentially supplied to the reference areas via the reticle R and the projection optical system PL. The illumination light IL of 1 / N of the amount is irradiated, and the pattern of the reticle R is reduced and projected.

  In this way, when N exposures are completed and the determination in step 208 is affirmed, the process proceeds to step 212.

  In step 212, main controller 28 determines whether or not exposure of a predetermined number of wafers has been completed. If this determination is denied, the process returns to step 202, and the processes of steps 202, 204, 206, 208, and 210 are repeated until the determination in step 212 is affirmed. On the other hand, if the determination in step 212 is affirmed, main controller 28 ends the series of processes.

The exposed wafer W unloaded from the wafer table 18 by the wafer exchange described above is transferred to a coater / developer (not shown) via a wafer transfer system (not shown) and developed. After the development, a resist image having a pattern of the reticle R is formed in 45 divided areas _Sj on the wafer W.

  In the present embodiment, the irradiation amount of the illumination light IL per one exposure, that is, the number of exposures N is determined from pattern alignment accuracy (including overlay accuracy), throughput, and the like.

  Here, in the exposure apparatus 100 of the present embodiment, as the mode for performing the exposure process (multiple exposure) based on the flowchart shown in FIG. 3, the number of times of exposure N is determined with priority given to the pattern alignment accuracy. A priority mode and a throughput priority mode in which the number of exposures N is determined by giving priority to the throughput are selectable. Prior to the start of the process according to the flowchart of FIG. 3, the optimum number of exposures N is set by the main controller 28 according to the selected mode.

  Hereinafter, an optimization method of the number of times of exposure (the number of times of multiplexing) N in each of the accuracy priority mode and the throughput priority mode will be described.

First, the principle of determining the number of exposures N in the accuracy priority mode will be described.
a. In this case, as shown in FIG. 5 (A), the overlay accuracy when the predetermined reference amount is divided into N times (for example, 1, 2, 5, 10 times, etc.) for multiple exposure (here, 5 is plotted on a two-dimensional graph with the horizontal axis as the number of exposures N, and a least square operation using an approximation function is performed, as shown in FIG. Find an approximate curve. Of course, the plot points may be complemented by an appropriate complement calculation. As shown in FIG. 5A, as the number of exposures N increases, that is, as the exposure amount IL per time decreases, the thermal expansion of the wafer is suppressed, so that the overlay accuracy improves (overlay error). Becomes smaller).
b. Next, based on FIG. 5A, a minimum exposure number that satisfies the required overlay accuracy, that is, an optimum exposure number N is obtained.
c. a. And b. This process is repeated for a plurality of different reference amounts, and the optimum number of exposures N for each reference amount is obtained. Then, as shown in FIG. 5B, the optimum number of exposures N for each reference amount is plotted on a two-dimensional graph with the horizontal axis as the reference amount, and a least square operation using an approximate function is performed. An approximate curve as shown in FIG.

  In the present embodiment, a curve indicating the relationship between the reference amount and the optimum exposure count N as shown in FIG. 5B is obtained in advance and stored in the memory. Then, when the accuracy priority mode is selected by the operator via an input / output device (not shown), the main control device 28 is based on the resist sensitivity (reference amount) at that time and the graph shown in FIG. The optimal number of exposures N is set. As shown in FIG. 5B, main controller 28 sets exposure number N to a larger value as the reference amount is larger.

Next, the principle of determining the number of exposures N in the throughput priority mode will be described.
d. In this case, as shown in FIG. 6A, the throughput (here, the index) when multiple exposure is performed by dividing a predetermined reference amount into N times (for example, 1, 2, 5, 10 times, etc.). 6 is plotted on a two-dimensional graph with the horizontal axis as the number of exposures N, and a least square operation using an approximation function is performed to obtain an approximation as shown in FIG. Find a curve. Of course, the plot points may be complemented by an appropriate complement calculation. As shown in FIG. 6A, the throughput decreases (the total exposure time becomes longer) as the number of exposures N increases, that is, as the irradiation amount of illumination light IL per time decreases.
e. Next, based on FIG. 6A, the minimum number of exposures N that satisfies the required throughput (exposure time allowed as the actual exposure time including the cooling time of the projection optical system PL) is obtained. In the exposure apparatus 100, the projection optical system PL is heated and the desired imaging performance cannot be maintained. Therefore, even when normal exposure is performed, each time exposure of a predetermined number of wafers is completed, a certain waiting time is required. The projection optical system PL is cooled by providing time. Therefore, the required throughput of the actual exposure apparatus is determined including the cooling time.
f. d. And e. This process is repeated for a plurality of different reference amounts, and the optimum number of exposures N for each reference amount is obtained. Then, as shown in FIG. 6B, the optimum number of exposures N for each reference amount is plotted on a two-dimensional graph with the horizontal axis as the reference amount, and a least square operation using an approximation function is performed. An approximate curve as shown in FIG. 6B is obtained.

  In the present embodiment, a curve indicating the relationship between the reference amount and the optimum exposure number N as shown in FIG. 6B is obtained in advance and stored in the memory. Then, when the throughput priority mode is selected by the operator via an input / output device (not shown), the main control device 28 is based on the resist sensitivity (reference amount) at that time and the graph shown in FIG. The optimal number of exposures N is set. As shown in FIG. 6B, main controller 28 sets exposure number N to a larger value as the reference amount is larger.

  In setting the number of exposures N in the accuracy priority mode, the main controller 28 may consider the heat dissipation efficiency of the wafer W (heat dissipation efficiency of the wafer itself, the capability of the cooling device of the exposure apparatus 100, etc.). That is, as the heat dissipation efficiency of the wafer is higher, the thermal expansion is smaller and the alignment accuracy is improved. Therefore, the main controller 28 may reduce the number of exposures accordingly. This improves the throughput. In setting the number of exposures N in the accuracy priority mode, the main controller 28 may also consider the area of the partition area on the wafer. That is, the smaller the area of the partitioned area, the smaller the amount of light, so the thermal expansion for each partitioned area is reduced. Accordingly, since the overlay accuracy is improved, the main controller 28 reduces the number of exposures accordingly. This improves the throughput.

  The main controller 28 may also consider the above-described cooling time of the projection optical system PL when setting the number of exposures N in the accuracy priority mode.

  Further, in the accuracy priority mode, main controller 28 may provide a waiting time for cooling wafer W in step 210 in consideration of the cooling time of projection optical system PL. The time required for cooling depends on the degree of heating of the wafer W, that is, the irradiation amount of the illumination light IL, the heat dissipation of the wafer W, the performance of the cooling device (not shown), or the pattern alignment accuracy (overlay accuracy), etc. It is desirable to take this into account. Here, the alignment accuracy of the pattern can be evaluated from the result of wafer alignment, for example. Therefore, prior to step 210, the same EGA as in step 204 is executed, the waiting time can be determined according to the alignment accuracy of the evaluated pattern, and the wafer W can be cooled. Of course, the main controller 28 may set the number of exposures N in consideration of the cooling time of the projection optical system PL in addition to the setting of the waiting time.

  As described above in detail, in the exposure method of the present embodiment, first, the photosensitive layer on the wafer is irradiated with illumination light of an amount 1 / N of the reference amount (resist sensitivity in the present embodiment), and the wafer is irradiated on the wafer. The plurality of partitioned areas arranged are exposed. Then, exposure with illumination light having an amount 1 / N of the reference amount is repeated N times. As described above, according to the exposure method of the present embodiment, by performing multiple exposure, the amount of illumination light per one time can be reduced, so that the thermal expansion of the wafer can be suppressed and the pattern alignment accuracy can be reduced. (Including overlay accuracy) can be improved. Here, the number of repeated exposures when performing multiple exposure is determined based on pattern alignment accuracy (including overlay accuracy) or time (throughput) required for pattern transfer. Therefore, it is possible to avoid a decrease in pattern alignment accuracy or to suppress a decrease in throughput.

  In the above-described embodiment, the exposure (multiple exposure) is repeatedly performed with the illumination light IL having a constant irradiation amount obtained by dividing the reference amount by N. However, the irradiation amount of the illumination light IL when performing a plurality of exposures is: It may be different each time. For example, the irradiation amount of the illumination light IL may be changed for each exposure according to the pattern overlay accuracy. In this case, exposure is repeated until the amount of illumination light IL irradiated to the photosensitive layer reaches a reference amount. In the above embodiment, as a method for determining the number of exposures at the time of multiple exposure, a method in which priority is given to pattern alignment accuracy and a method in which throughput is given priority have been prepared. The number of exposures may be determined by balancing both the throughputs. For example, in the accuracy priority mode, if the throughput decreases significantly due to an increase in the number of exposures, a threshold is set for the throughput (exposure time), and the number of exposures is reduced so that the throughput is below this threshold. May be. Further, in the throughput priority mode, when the alignment accuracy is remarkably lowered by reducing the number of exposures, a threshold is provided for the alignment accuracy (overlay error) so that the overlay error is less than this threshold. In addition, the number of exposures may be increased.

  In the above-described embodiment, the case where at least one layer of exposure is performed on the wafer W, that is, the case where the exposure of the second and subsequent layers is performed is illustrated. When performing the exposure, multiple exposure processing according to the same flowchart as that of FIG. 3 may be performed. However, in this case, since there is no ground mark on the wafer, the wafer alignment (EGA) in step 204 is omitted.

  In the exposure apparatus 100 of the above embodiment, the position of the wafer table 18 is measured using the laser interferometer 26. Here, instead of the laser interferometer 26, an encoder (an encoder system including a plurality of encoders) may be used. Alternatively, the laser interferometer 26 and the encoder may be used in combination.

  In the above embodiment, the exposure method of the present invention is applied to a reduced projection exposure apparatus of the step-and-repeat method as an example. The present invention is not limited to this, and the present invention can also be applied to a scanning exposure apparatus such as a step-and-scan method. The present invention can also be applied to a step-and-stitch reduction projection exposure apparatus, a proximity exposure apparatus, or a mirror projection aligner that synthesizes a shot area and a shot area. Further, as disclosed in, for example, US Pat. No. 6,590,634, US Pat. No. 5,969,441, US Pat. No. 6,208,407, etc. The present invention can also be applied to a multi-stage type exposure apparatus provided with a stage. Further, as disclosed in, for example, WO 2005/074014 pamphlet, an exposure apparatus including a measurement stage including a measurement member (for example, a reference mark and / or a sensor) is provided separately from the wafer stage. The present invention is applicable.

  Further, the projection optical system PL may be any of a refractive system, a catadioptric system, and a reflective system. Further, any of a reduction system, an equal magnification system, and an enlargement system may be used. The projected image may be either an inverted image or an erect image.

Furthermore, an ArF excimer laser (wavelength 193 nm), KrF excimer laser (wavelength 248 nm), F ₂ laser (wavelength 157 nm), or other pulse laser light source in the vacuum ultraviolet region may be used as the light source of the exposure apparatus of this embodiment. it can. In addition, as the illumination light for exposure, for example, a fiber doped with, for example, erbium (or both erbium and ytterbium) with a single wavelength laser beam in the infrared region or visible region oscillated from a DFB semiconductor laser or fiber laser. It is also possible to use a harmonic that is amplified by an amplifier and wavelength-converted into ultraviolet light using a nonlinear optical crystal.

  In the above embodiment, a light transmissive mask (reticle) in which a predetermined light shielding pattern (or phase pattern / dimming pattern) is formed on a light transmissive substrate is used. Instead of this reticle, for example, the US As disclosed in Japanese Patent No. 6,778,257, an electronic mask (variable molding mask, active mask) that forms a transmission pattern, a reflection pattern, or a light emission pattern based on electronic data of a pattern to be exposed. Alternatively, for example, a DMD (Digital Micro-mirror Device) that is a kind of non-light emitting image display element (spatial light modulator) may be used.

  Further, as disclosed in, for example, US Pat. No. 6,611,316, two reticle patterns are synthesized on a wafer via a projection optical system, and one shot on the wafer is obtained by one exposure. The present invention can also be applied to an exposure apparatus that double exposes a region almost simultaneously.

  Note that the object on which the pattern is to be formed in the above embodiment (the object to be exposed to the energy beam) is not limited to the wafer, but other objects such as a glass plate, a ceramic substrate, a film member, or a mask blank. But it ’s okay.

  The use of the exposure apparatus is not limited to the exposure apparatus for semiconductor manufacturing. For example, an exposure apparatus for liquid crystal that transfers a liquid crystal display element pattern onto a square glass plate, an organic EL, a thin film magnetic head, an image sensor ( CCDs, etc.), micromachines, DNA chips and the like can also be widely applied to exposure apparatuses. Further, in order to manufacture reticles or masks used in not only microdevices such as semiconductor elements but also light exposure apparatuses, EUV exposure apparatuses, X-ray exposure apparatuses, electron beam exposure apparatuses, etc., glass substrates or silicon wafers, etc. The present invention can also be applied to an exposure apparatus that transfers a circuit pattern.

  Furthermore, the present invention relates to an exposure apparatus for transferring a device pattern onto a glass plate, a thin film magnetic head, which is used for manufacturing not only an exposure apparatus used for manufacturing a semiconductor element but also a display including a liquid crystal display element and a plasma display. It is also applied to exposure equipment used to manufacture device patterns, exposure equipment used to transfer device patterns onto ceramic wafers, imaging devices (CCD, etc.), micromachines, DNA chips, and masks or reticles. can do.

  An electronic device such as a semiconductor element includes a step of designing a function / performance of the device, a step of manufacturing a reticle based on the design step, a step of manufacturing a wafer from a silicon material, and the exposure apparatus (pattern forming apparatus) of the above-described embodiment. ) A lithography step for transferring a mask (reticle) pattern onto a wafer, a development step for developing the exposed wafer, an etching step for removing exposed members other than the portion where the resist remains by etching, and etching is completed. It is manufactured through a resist removal step for removing unnecessary resist, a device assembly step (including a dicing process, a bonding process, and a package process), an inspection step, and the like. In this case, in the lithography step, the exposure method described above is executed using the exposure apparatus of the above embodiment, and a device pattern is formed on the wafer. Therefore, a highly integrated device can be manufactured with high productivity.

  The exposure method of the present invention is suitable for forming a pattern on an object by irradiation with an energy beam. The device manufacturing method of the present invention is suitable for manufacturing an electronic device such as a semiconductor element or a liquid crystal display element.

It is a figure which shows schematic structure of the exposure apparatus of one Embodiment of this invention. 2A to 2C are views for explaining the principle of deformation of the partition region due to thermal expansion of the wafer. It is a flowchart which shows the procedure of the exposure method of this embodiment. It is a figure for demonstrating the exposure order of the division area in the exposure method of this embodiment. FIG. 5A and FIG. 5B are diagrams for explaining a method for determining the number of exposures in the accuracy priority mode. FIGS. 6A and 6B are diagrams for explaining a method for determining the number of exposures in the throughput priority mode.

Explanation of symbols

  IL ... illumination light, IOP ... illumination system, 20 ... XY stage, 26 ... laser interferometer, 28 ... main controller, 100 ... exposure apparatus, AS ... alignment detection system, PL ... projection optical system, W ... wafer.

Claims (7)

An exposure method for exposing an object by irradiating an energy beam,
The sensitive layer formed on the object is irradiated with a smaller amount of the energy beam than the reference amount, and a plurality of locations on the object are sequentially exposed. The irradiation amount of the energy beam on the sensitive layer is the reference amount. An exposure method including the step of forming the plurality of pattern regions in which the pattern is formed on the object by repeating a number of times determined based on at least one of required alignment accuracy and throughput until the amount is reached.   2. The exposure method according to claim 1, wherein the reference amount is an irradiation amount of the energy beam sufficient to form a latent image of the pattern on the sensitive layer by a single exposure. The amount less than the reference amount is 1 / N of the reference amount,
The exposure method according to claim 1, wherein in the step, exposure at a plurality of locations on the object is repeated N times.   4. The exposure method according to claim 1, wherein the amount smaller than the reference amount is determined based on at least one of the alignment accuracy of the pattern and the throughput. The energy beam is applied to the sensitive layer via an optical system,
The exposure method according to claim 1, wherein the number of repetitions is determined in consideration of a time required for cooling the optical system. The object is held by a moving body that moves while holding the object,
The exposure method according to claim 1, wherein the step is performed without releasing the holding of the object by the moving body. Using the exposure method according to any one of claims 1 to 6 to form the plurality of pattern regions in which a pattern is formed on an object;
Developing the object on which the plurality of pattern areas are formed;
A device manufacturing method including: