JP2005129805A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transfer a line pattern to a positive photoresist by an exposure method using a phase shifting mask. <P>SOLUTION: The line pattern is transferred to a positive photoresist film formed on a wafer by lap-exposing transferring areas 2A and 2B to light. In the transferring areas 2A and 2B, light shielding patterns 3b (3b1, 3b2, and 3b3) and 3c (3c1, 3c2, and 3c3) are disposed with a light transmitting area for a background. Although the dimensions, shapes, and disposition of the light shielding patterns 3b (3b1, 3b2, and 3b3) and 3c (3c1, 3c2, and 3c3) upon which the transferring areas 2A and 2B are superimposed are identical, shifters 7a and 7b are disposed so that they may be inverted against each other. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to an exposure technique using a phase shift mask.

  In next-generation 65 nm node lithography, there is a strong demand to continue using the ArF scanner introduced at the 90 nm node. The size of the logic LSI wiring at the 90 nm node is, for example, about 100 to 120 nm, and the K1 factor of R = K1 × λ / NA indicating the resolution R is about 0.5, which is realized by applying weak super-resolution technology. Is possible. However, the size of the wiring of the 65 nm node is required to be, for example, about 70 to 90 nm, and the K1 factor is about 0.35, and it is indispensable to introduce a strong super-resolution technique. In order to realize the super-resolution technique, a high-precision mask technique is required. In particular, in the Levenson mask or the like that is one of the phase shift masks, it is necessary to realize a complicated mask structure with high precision.

  Regarding the phase shift technique which is a super-resolution technique, for example, in Japanese Patent Laid-Open No. 6-83032, as a problem when an electron beam drawing resist or silicon dioxide is used as a shifter material of a phase shift mask, the transmittance of the shifter portion is changed. The resulting attenuation of exposure light is cited. As a means for solving this problem, a method is disclosed in which two masks having inverted shifter arrangements are prepared, and they are overlapped to compensate for attenuation of exposure light in the shifter (see Patent Document 1). .

  Also, for example, in Japanese Patent Application Laid-Open No. 2001-230186, light attenuation of a digging portion is obtained by double exposure of a phase inversion pattern with a digging shifter structure that forms a shifter by digging into a transparent mask substrate. A method for erasing the influence of a pattern and a method for securing resolution using an auxiliary pattern for an isolated pattern in a phase shift mask having a region for transferring a dense pattern and a region for transferring an isolated pattern are disclosed (see Patent Document 2). ).

Further, for example, Japanese Patent Application Laid-Open No. 7-130615 and US Pat. No. 6,258,493 B1 disclose a superposition exposure method of a phase shift mask and a normal mask without a phase shifter, but the patterns of the respective masks are different. Therefore, it is difficult to control the phase of transmitted light through the phase shift mask (see Patent Document 3).
JP-A-6-83032 JP 2001-230186 A JP-A-7-130615, US6258493 B1

  By the way, in the case of a single exposure, in order to form a line pattern such as a wiring pattern by a normal Levenson type phase shift method, a dark field type (DF) is used so that the edge of the phase shifter is not exposed in the light transmitting portion. ) Mask is used. This mask is a mask in which a transparent light transmission pattern is arranged on a black background (light-shielding region), and it is necessary to leave a photoresist pattern in a line pattern, that is, an exposure region. Therefore, it is necessary to use a negative photoresist. is there.

  However, in a lithography using a light source with a short wavelength such as an ArF excimer laser, a positive photoresist is mainstream, and it is desirable to use a positive photoresist in terms of performance. Therefore, in order to employ a positive photoresist, it is necessary to employ a bright field type (BF) mask. This mask is a mask in which a light shielding pattern is arranged on a white background (light transmission region), and a line pattern can be formed with a positive photoresist. However, when a pattern is transferred to a positive type photoresist by a normal single exposure using a bright field type mask in which a transparent phase shifter is arranged beside the light shielding pattern for transferring the line pattern, other than the light shielding pattern As a result of the dark part pattern being formed at the edge part of the phase shifter, there is a problem that an unnecessary pattern is transferred.

  An object of the present invention is to provide a technique capable of transferring a line pattern to a positive photoresist by an exposure method using a phase shift mask.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

That is, the present invention includes a step of transferring a desired pattern to the positive photoresist film by performing a reduction projection exposure process using a mask on the wafer on which the positive photoresist film is deposited. The reduced projection exposure process includes a step of exposing the first transfer region and the second transfer region of the mask so as to overlap one region of the positive photoresist film,
The first transfer region and the second transfer region include a light transmission region as a background,
A plurality of light shielding patterns are disposed in each of the first transfer region and the second transfer region,
A phase shifter that reverses the phase of the transmitted light with respect to the light transmitted through the light transmission region is disposed adjacent to the plurality of light shielding patterns in the first transfer region and the second transfer region,
The shape, size and arrangement of the light-shielding patterns of the first transfer area and the second transfer area are the same,
The phase shifters of the first transfer region and the second transfer region are arranged so as to be inverted from each other.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, the line pattern can be transferred to the positive photoresist by an exposure method using a phase shift mask, so that the degree of integration of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
First, a mask used in the method for manufacturing a semiconductor device according to the first embodiment will be described with reference to FIGS. 1 is an overall plan view of the mask 1A of the first embodiment, FIG. 2 is a sectional view taken along line XA-XA in FIG. 1, FIG. 3 is a sectional view taken along line XB-XB in FIG. The graph of an example of light intensity distribution on the wafer of the transmitted light which permeate | transmitted the coordinate x4-x14 and its vicinity is each shown. Although FIG. 1 is a plan view, it is hatched to make the drawing easy to see. 2 and 3 show coordinates x1 to x18 for explanation.

  The mask 1A of the first embodiment exemplifies a mask for transferring a line pattern (gate electrode, wiring, etc.) as an integrated circuit pattern. On the main surface of the mask 1A, for example, two transfer regions (first transfer region, second transfer region) 2A, 2B are defined in the light shielding pattern 3a in the vertical direction in FIG. 1 (scanning direction SC of the exposure apparatus). ) Are arranged side by side. Each of the transfer areas 2A and 2B corresponds to an area where, for example, a semiconductor chip (hereinafter simply referred to as a chip) is transferred. In the first embodiment, the two transfer regions 2A and 2B are overlapped and exposed to form a photoresist film (positive photoresist film) in one chip region of a semiconductor wafer (hereinafter simply referred to as a wafer). A desired line pattern is transferred.

  The mask 1A of the first embodiment is a bright field type mask, and each of the transfer regions 2A and 2B has a plurality of line patterns for line pattern transfer with the light transmission region of the main surface of the mask substrate 6 as a background. The light shielding patterns 3b (3b1, 3b2, 3b3), 3c (3c1, 3c2, 3c3) are arranged. The outer peripheries of the transfer areas 2A and 2B are shielded by the light shielding pattern 3a. The light shielding patterns 3a, 3b, 3c are made of, for example, chromium, chromium oxide, or a laminated film thereof. The mask substrate 6 is made of, for example, transparent synthetic quartz glass.

  The light-shielding patterns 3b1, 3b2, 3c1, and 3c2 transfer patterns having dimensions (width: dimensions in the short direction) that cannot be sufficiently transferred unless phase shifters (hereinafter simply referred to as shifters) 7a and 7b indicated by bold lines are arranged. It is a mask pattern for this. Among the light shielding patterns 3b1, 3b2, 3c1, and 3c2, the light shielding patterns 3b1 and 3c1 are examples of a light shielding pattern in a dense region in which a plurality of light shielding patterns 3b1 and 3c1 are repeatedly densely arranged. The light shielding pattern of the sparse region arranged in a sparsely isolated state is illustrated. On the other hand, the light-shielding patterns (second light-shielding patterns) 3b3 and 3c3 are for transferring a pattern having a dimension (width: short-direction dimension) that can sufficiently transfer the pattern without arranging the shifters 7a and 7b. This is a mask pattern. The widths (short dimension) of the light shielding patterns 3b1, 3b2, 3c1, 3c2 are smaller than the widths (short dimension) of the light shielding patterns 3b3, 3c3.

  The shifters 7a and 7b are arranged adjacent to one side of the light shielding patterns 3b1, 3b2, 3c1 and 3c2. In the dense area of the transfer area 2A, the shifter 7a is arranged so as to be shared between the adjacent light shielding patterns 3b1 and 3b1, and in the dense area of the transfer area 2B, shared between the adjacent light shielding patterns 3c1 and 3c1. As shown, the shifter 7b is arranged. In the dense area, the light transmissive areas where the shifters 7a and 7b are arranged and the light transmissive areas where the shifters 7a and 7b are not arranged are alternately arranged along the horizontal direction of FIG. By arranging the shifters 7a and 7b, the phase of the transmitted light is inverted by 180 degrees between the light transmitted through the shifters 7a and 7b and the light transmitted through the light transmission region without the shifters 7a and 7b. . Thereby, the contrast of the projected image of the light shielding patterns 3b1, 3b, 3c1, and 3c2 becomes clear, and the resolution of the pattern can be improved. Here, the shifters 7a and 7b are, for example, groove shifters. That is, the shifters 7a and 7b are formed by digging a groove having a concave section in the mask substrate 6 itself. The depth Z of the shifters 7a and 7b is formed so as to satisfy Z = λ / (2 (n−1)) in order to invert the phase of transmitted light by 180 degrees. In the above equation, n represents the refractive index of the mask substrate 6 with respect to exposure light having a predetermined exposure wavelength, and λ represents the exposure wavelength.

  When the light shielding patterns 3b and 3c in the transfer areas 2A and 2B of the mask 1A are compared with each other, the design shape, size and arrangement of the light shielding patterns 3b and 3c to be overlaid in the transfer area 2A and the transfer area 2B are the same. It is. However, when the transfer areas 2A and 2B are overlaid and exposed, the light shielding patterns 3b and 3c of the transfer areas 2A and 2B overlap, whereas the shifters 7a and 7b do not overlap. That is, the shifters 7a and 7b in the transfer regions 2A and 2B are so arranged that the phase of transmitted light is inverted by 180 degrees in the multiple exposure portions (or in the first embodiment, it is not always necessary to invert 180 degrees. It is arranged so that a phase difference necessary for exposure occurs. As shown in FIG. 4, in the case of only one exposure (referred to as single exposure), a peak having a low light intensity at a portion corresponding to the edge EG of the shifter 7a arranged in the background light transmission region of the transfer region 2A. PEG can be made. For this reason, an unnecessary pattern is transferred to the positive photoresist film in one exposure. On the other hand, in the first embodiment, the transfer regions 2A and 2B in which the shifters 7a and 7b are arranged in an inverted manner are overlapped and exposed, so that it is unnecessary to form the edge portions of the shifters 7a and 7b in the first exposure. Since a dark portion can be erased by overlapping exposure of the light transmission region in the second exposure, it is possible to prevent unnecessary patterns from being transferred to the positive photoresist film. That is, in the first embodiment, the shifters 7a and 7b can be arranged even in the bright field mask 1A by adopting the phase inversion multiple exposure method. Further, by performing multiple exposure, it is possible to obtain a phase shift effect at both side portions sandwiching the transfer pattern of the light shielding patterns 3b and 3c in both the sparse region and the dense region, so that high resolution can be obtained. As a result, the light shielding patterns 3b and 3c in the dense and sparse areas of the mask 1A can be satisfactorily transferred to the positive photoresist film.

  The erasing effect of the peak PEG with low light intensity will be described with reference to FIGS. 5 and 6 show the simulation results of the light intensity distribution (INTENSITY PROFILE) of the light transmitted through each of the separate transfer regions where the superposition is performed. 5 and 6, the shifter arrangement is reversed. FIG. 7 shows a simulation result of the light intensity distribution (INTENSITY PROFILE) obtained when the exposures shown in FIGS. 5 and 6 are overlaid. Since the peaks PEG1 and PEG1 with unnecessary low light intensity in FIGS. 5 and 6 overlap with the light intensity peaks PA2 and PA1, respectively, the peaks PEG2 and PEG2 with low light intensity are small as shown in FIG. Is not transferred to the photoresist film.

  Further, in the case of one-time exposure, the range of error of the shifters 7a and 7b must be very narrow so that, for example, the phase angle error is within ± 5 degrees. Difficult, causing a reduction in mask yield. For example, when an ArF excimer laser with a wavelength of 193 nm is used as the exposure light, the depth of the groove for forming the shifter is about 190 nm. If the required allowable amount of phase error is 2 degrees, the digging amount of the shifter groove must be adjusted with an accuracy of about 2 nm. In addition, in order to form the phase error in a narrow range as described above, a process such as measuring and adjusting the phase is required during the mask manufacturing process. As a result, the mask manufacturing is laborious and time-consuming. It has become. On the other hand, in the first embodiment, even if the absolute value accuracy (error accuracy) of the phase is somewhat poor due to the multiple exposure, the same resolution characteristic as in the case of the 180-degree phase difference can be obtained. For this reason, the dimensional accuracy of the pattern (transfer pattern) transferred to the wafer can be improved. Further, the allowable amount of phase error can be relaxed to about 20 degrees. That is, the phase angle error may be larger than ± 5 degrees (may be larger than 185 degrees or smaller than 175 degrees), so that the error range of the depth of the shifters 7a and 7b is set. Can be greatly relaxed. For this reason, the ease of manufacturing the mask 1A can be greatly improved, and the manufacturing yield of the mask 1A can be greatly improved. Therefore, the cost of the mask can be reduced. Further, according to the first embodiment in which the transfer areas 2A and 2B to be overlapped are formed at different plane positions in the same plane of the same mask 1A, compared to the case where the transfer areas 2A and 2B are arranged on separate masks. Since the depth of the shifters 7a and 7b and the error amount thereof can be made substantially uniform within the main surface of the mask substrate 6, the mask 1A can be easily manufactured while ensuring the absolute value accuracy of a relatively high phase. can do. Further, since the exposure is performed with one mask 1A, the throughput can be improved as compared with the case where the transfer regions 2A and 2B are arranged on separate masks. However, the transfer regions 2A and 2B may be arranged in separate masks, and after exposure with a mask having the transfer region 2A for each wafer, the mask may be replaced with a mask having the transfer region 2B for double exposure. This method is effective when the chip size is large and the two transfer regions 2A and 2B cannot be arranged in the same mask.

  In the case of a single exposure, the intensity of light transmitted through the light transmission region where the groove-type shifters 7a and 7b are disposed is attenuated. As a result, a dimensional difference may occur in the transfer pattern depending on the presence or absence of the shifters 7a and 7b. . This problem will be described with reference to FIGS. 42 to 44, and general countermeasures will be described with reference to FIGS. FIG. 42 shows a cross-sectional shape of a phase shift mask 50 having a mask substrate 50a, a light shielding pattern 50b formed on the main surface, and a light transmission pattern 50c. The light shielding pattern 50b is made of, for example, chromium. A groove-type shifter 50d is formed in one of the light transmission patterns 50c and 50c adjacent to each other in order to invert the phase of each transmitted light by 180 degrees. Here, a case where the substrate groove shifter is not a saddle type groove shifter is illustrated. Further, the planar shapes and dimensions of the light transmission patterns 50c, 50c adjacent to each other are the same. When projection exposure is performed using this phase shift mask 50, the light intensity obtained on the projection substrate is, as shown in FIG. 43, the intensity 51a of the light transmitted through the light transmission pattern 50c in which the groove-type shifter 50d is arranged. Since the intensity of the transmitted light is attenuated due to the influence of the side wall of the groove-type shifter 50d, the intensity is lower than the intensity 51b of the light transmitted through the light transmission pattern 50c in which the groove-type shifter 50d is not disposed. Therefore, when the pattern is transferred to the photoresist film by a normal method (single exposure), as shown in the exposure plane of FIG. 44, the width of the photoresist pattern 52a to which the light transmission pattern 50c on which the shifter 50d is arranged is transferred. The dimension W50 in the direction is smaller than the dimension W51 in the width direction of the photoresist pattern 52b to which the light transmission pattern 50c in which the groove-type shifter 50d is not disposed is transferred. In other words, the planar dimensions of the photoresist patterns 52a and 52b that should be transferred with the same planar dimension differ depending on the presence or absence of the groove-type shifter 50d. In order to prevent this, as shown in FIG. 45, the groove-type shifter 50d has a saddle-shaped groove shifter structure. That is, the side wall of the groove-type shifter 50d of the mask substrate 50a is adjusted so as to be hidden under the light shielding pattern 50b, and the end portion of the light shielding pattern 50b is projected in a bowl shape by the collar length P. With this structure, as shown in FIG. 46, the intensity 53a of the light transmitted through the light transmission pattern 50c in which the groove-type shifter 50d is arranged has a light transmission pattern 50c in which the groove-type shifter 50d is not arranged. It is almost the same as the intensity 53b of the light transmitted through. However, the current situation is not completely equal. Therefore, as shown in the exposure plane of FIG. 47, the width W 52 of the photoresist pattern 55a to which the light transmission pattern 50c having the groove-type shifter 50d is transferred and the groove-type shifter 50d are arranged. It is impossible to completely eliminate the dimensional difference from the dimension W53 in the width direction of the photoresist pattern 55b to which the light transmission pattern 50c is transferred. Further, according to the present inventor, the dimensional difference of the transfer pattern varies depending on the value of the dimension of the pattern to be formed on the wafer. It was found difficult to eliminate the dimensional difference.

  On the other hand, in the first embodiment, the light transmitted through the light transmission region where the shifters 7a and 7b are disposed and the light transmitted through the light transmission region where the shifters 7a and 7b are not disposed are made into the same region. Since the exposure is repeated, the light intensities of both can be averaged. That is, since the light intensity imbalance can be canceled, the light intensity distribution can be made uniform. For this reason, the dimensional variation of the transfer pattern can be suppressed or prevented, and the dimensional accuracy of the transfer pattern can be improved. In addition, the effect of averaging the aberration of the optical lens and the effect of averaging the dimensional distribution in the mask 1A are added, and the dimensional accuracy of the transfer pattern can be further improved.

  The effect of improving the non-uniform light intensity caused by the shifter will be described with reference to FIGS. In the simulation results of FIGS. 8 to 10, for example, the phase of the light transmitted through the shifter has a phase difference of 160 degrees with respect to the phase of the light transmitted through the region without the shifter, and is 20 degrees from the ideal 180 degrees. It is off. Also, the light transmittance of the shifter is 90%, which is 10% off from the ideal 100%. The focal position is also shifted by 0.2 μm. There are five light shielding patterns.

  8 and 9 show the simulation results of the light intensity distribution (INTENSITY PROFILE) of the light transmitted through each of the separate transfer regions where the superposition is performed. 8 and 9, the shifter arrangement is reversed. In each of FIGS. 8 and 9, since unnecessary dark portions due to the shifter edge portions are transferred, dark portion peaks should be seen at 6 locations, which should originally be 5 locations. In each of FIGS. 8 and 9, the light intensity peak PS of the light transmitted through the shifter is changed to the light intensity peak PB of the light transmitted through the light transmission region without the shifter due to the effect of the phase shift of the shifter and the light transmittance. It is smaller than that. FIG. 10 shows a simulation result of the light intensity distribution (INTENSITY PROFILE) obtained when the exposures shown in FIGS. Since the transfer areas in which the shifters are mutually inverted are subjected to double exposure, the light intensities of both can be averaged, so that a uniform light intensity can be obtained at the adjacent light intensity peak PC. I understand. As a result of actually transferring the pattern, for example, a 140 nm pattern was successfully formed with an accuracy of ± 5 nm on the entire surface of the chip. In addition, no special tendency was observed in the resolution dimension of adjacent patterns. Also, no unnecessary light intensity peak transfer was observed.

  As described above, according to the first embodiment, the dimensional accuracy of the transfer pattern can be improved by suppressing the dimensional variation of the transfer pattern due to the presence or absence of the shifter or the pattern dimension value without providing a fine wrinkle. That is, since it is not necessary to form a ridge, the ease of manufacturing the mask 1A can be greatly improved. For this reason, since the number of manufacturing steps of the mask 1A can be reduced, the manufacturing time of the mask 1A can be shortened. Moreover, since the yield of the mask 1A can be improved, the cost of the mask can be reduced. In particular, the ridge structure is more effective as the ridge length is longer. However, since the pattern of the mask 1A is also miniaturized in accordance with the demand for pattern miniaturization on the wafer, there is a limit to increasing the ridge length. Therefore, the technique of the first embodiment, which can improve the pattern dimension accuracy without adopting the eaves structure, is a technique suitable for pattern miniaturization.

  Further, according to the first embodiment, it is possible to average or remove defects randomly present in the transfer regions 2A and 2B of the mask 1A by multiple exposure, thereby reducing or preventing transfer of the defects of the mask 1A. it can. Moreover, the transfer limit of the defect of the mask 1A can be expanded. In other words, dimensional defects that could not be ignored until now can be ignored. For example, a defect of 0.2 μm or more is currently transferred, but according to the first embodiment, a defect of 0.4 μm or more is transferred. That is, since a defect of less than 0.4 μm on the mask 1A can be ignored, the critical dimension for defect inspection of the mask 1A can be relaxed. Therefore, since the defect inspection and defect correction of the mask 1A can be facilitated, the ease of manufacturing the mask 1A can be improved.

  In semiconductor devices, the number of mask patterns tends to increase in the future, so how to reduce the number of pattern data in mask design is an important issue. In the dark field type mask, when an isolated pattern exists, it is necessary to arrange an auxiliary pattern around the isolated pattern to have a phase shift effect, and the number of pattern data increases, and the auxiliary pattern arrangement DA (Design Automation) processing is required, and there are practical problems. On the other hand, in the first embodiment, it is not necessary to add an auxiliary pattern to the isolated pattern (light-shielding patterns 3b2 and 3c2), so that the problem of an increase in the number of pattern data due to the auxiliary pattern does not occur, and the auxiliary pattern arrangement DA There is no need for processing.

  The number of transfer areas arranged on one mask 1A is not limited to the above, and can be variously changed. In addition, another light transmission pattern such as a mask alignment mark or a measurement mark is formed in the light shielding area formed by the light shielding pattern 3a on the outer periphery of the transfer areas 2A and 2B. Further, in the transfer regions 2A and 2B, in addition to a pattern that substantially constitutes an integrated circuit, for example, an alignment mark pattern used for overlay, a mark pattern used for overlay inspection, or a mark used when inspecting electrical characteristics A pattern that does not substantially constitute an integrated circuit, such as a pattern, may be formed. Further, even in the case of the first embodiment, the optical proximity effect correction (OPC: Optical Proximity Correction) similar to that generally performed is necessary. For example, it is necessary to apply dimension correction to variables such as the distance to the adjacent pattern, the width of the adjacent pattern, and the presence / absence of the phase shifter with respect to the target pattern. In addition, the term “mask” in this embodiment indicates a broad concept including a reticle. In this embodiment, when the term “light-shielding region”, “light-shielding pattern”, “light-shielding film”, or “light-shielding” is used, the optical characteristics that transmit less than 40% of the exposure light irradiated to the region. It has shown that. Generally, 0% to less than 30% is used. On the other hand, when referring to “light transmission region”, “light transmission pattern”, “transparent region”, “transparent film” or “transparent”, optical that transmits 60% or more of the exposure light irradiated to that region. It shows that it has characteristics. Generally 90% or more is used.

  11 and 12 show examples of arrangement of the light shielding patterns 3b and 3c and the shifters 7a and 7b in the transfer region where the mask 1A is subjected to the overlay exposure for forming an actual device pattern. 11 and 12 show coordinates x20 to x26 and coordinates y20 to y25 so that the positional relationship of the overlay exposure can be understood. In addition, the light shielding patterns 3b and 3c are hatched to make the drawing easy to see. When the adjacent light shielding patterns 3b and 3b and the light shielding patterns 3c and 3c have different lengths in each region of FIGS. 11 and 12, it is necessary to arrange the shifters 7a and 7b according to the longer one. In addition, when the size of the light shielding pattern is large as described above (corresponding to the light shielding patterns 3b3 and 3c3), the arrangement of the shifter is unnecessary.

  Next, an example of a method for manufacturing the mask 1A of the first embodiment will be described with reference to FIGS. 13 to 15 are cross-sectional views corresponding to the XA-XA line in FIG. 1 during the manufacturing process of the mask 1A.

  First, as shown in FIG. 13, a light shielding film 3 made of, for example, chromium is deposited on the main surface of a mask substrate (mask blank) 6 made of, for example, transparent synthetic glass or the like by, for example, sputtering. Subsequently, as shown in FIG. 14, the light shielding film 3 is subjected to a series of lithography processes (hereinafter simply referred to as an electron beam lithography process) such as application of a resist film, exposure and development with an electron beam, and the like. After forming the resist pattern ER1 for pattern formation, wet etching is performed using the resist pattern ER1 as an etching mask, and the light shielding film 3 exposed from the resist pattern ER1 is etched to form the light shielding patterns 3a and 3b (3c). Thereafter, the resist pattern ER1 is removed.

  Next, as illustrated in FIG. 15, a resist pattern ER <b> 2 for forming a groove shifter is formed on the main surface of the mask substrate 6 through an electron beam lithography process. At this time, the outer periphery of the opening portion of the resist pattern ER2 does not need to coincide with the outer periphery of the groove shifter forming region, and a part of the light shielding film 3 may be exposed from the opening portion. Can do. Subsequently, anisotropic dry etching is performed using the resist pattern ER2 and the light shielding film 3 exposed from the opening as an etching mask, and a part of the mask substrate 6 exposed from the resist pattern ER2 and the light shielding film 3 is etched. Then, a groove-type shifter 7a (7b) is formed. When overlay exposure is not performed, the optical phase is strictly controlled, and the phase of the transmitted light is actually measured during the formation of the groove shifter. After the resist pattern is formed again through the electron beam lithography process, the etching process is performed. However, the mask manufacturing is troublesome and time-consuming, such as correcting the groove depth based on the measurement result. On the other hand, in the case of the first embodiment, since the absolute value control (error tolerance) of the phase of the transmitted light can be relaxed as described above, the groove for forming the shifter 7a (7b) The depth tolerance can be relatively large. Therefore, it is not necessary to actually measure the phase of transmitted light during the formation of the groove shifter, or to form a resist pattern again through the electron beam lithography process, and to correct the groove depth based on the measurement result. The manufacturing process of the mask 1A can be simplified. Therefore, the manufacturing time of the mask 1A can be greatly shortened. Further, the yield and reliability of the mask 1A can be improved. Therefore, the cost of the mask 1A can be reduced. Thereafter, the resist pattern ER2 is removed, and the mask 1A shown in FIGS. 1 and 2 is manufactured.

  However, if the difference in light intensity due to the presence or absence of the shifter has an extremely adverse effect on the resolution characteristics, isotropic wet etching is applied to the mask substrate 6 to block the side surfaces of the grooves for forming the shifters 7a and 7b. It is desirable to have a saddle structure as shown in FIG. 45 so as to slightly enter under the patterns 3b and 3c. Thereby, the difference in light intensity due to the presence or absence of the groove-type shifters 7a and 7b can be reduced, and the degradation of the resolution characteristics can be prevented.

Next, an example of the multiple exposure method using the mask 1A of the first embodiment will be described with reference to FIGS. 16 to 18 schematically show overall plan views of the wafer 9 during the multiple exposure process. The wafer 9 is a circular thin plate having, for example, silicon as a substrate, and a silicon oxide film having a thickness of, for example, about 200 nm is deposited on the main surface (device forming surface). A positive photoresist film having a thickness of about 300 nm is applied. Actual exposure conditions are, for example, as follows. The reduction projection exposure apparatus used a scanner. As the light source of the scanner, for example, an ArF excimer laser having a wavelength of 193 nm is used, and the numerical aperture NA of the optical lens is, for example, 0.70. The shape of the light source of the scanner is, for example, a circular shape, and the coherent factor (σ value) is, for example, 0.3. Single exposure amount to the photoresist film, for example a 150 J / m ^2, was adjusted to 300 J / m ² by double exposure. That is, the exposure amount of one time is a value obtained by dividing the required exposure amount by the number of multiple exposures. The minimum pattern in the mask 1A is a line-and-space pattern of, for example, about 140 nm in terms of the pattern size transferred to the wafer 9.

  First, after setting the mask 1A so that the transfer areas 2A and 2B of the mask 1A are arranged along the scanning direction, as shown in FIG. 16, the pattern of the transfer areas 2A and 2B of the mask 1A is scanned by a scanner. Exposure. The exposure amount at this time is about ½ of the required amount. Subsequently, as shown in FIG. 17, the wafer 9 is moved upward with respect to the mask 1A in FIG. At this time, the movement amount of the wafer 9 is set to ½ of the exposure area. Thus, the transfer area 2A of the mask 1A is overlapped with the transfer area 2B of the mask 1A transferred to the photoresist film of the wafer 9 in FIG. In addition, the exposure amount at this time is also about ½ of the required amount. Thus, an exposure amount necessary for exposure is obtained when the transfer regions 2A and 2B overlap. Subsequently, as shown in FIG. 18, the wafer 9 is moved upward in FIG. 18 with respect to the mask 1A, and the patterns of the transfer regions 2A and 2B of the mask 1A are similarly subjected to scanning exposure. At this time, the movement amount of the wafer 9 is also set to ½ of the exposure area so that the transfer area 2A of the mask 1A overlaps the transfer area 2B of the mask 1A transferred to the photoresist film of the wafer 9 in FIG. To do. Also, the exposure amount at this time is set to about ½ of the required amount so that the exposure amount necessary for the exposure can be obtained when the transfer regions 2A and 2B overlap. By repeating such multiple exposure processing operation on the entire main surface of the wafer 9, line patterns of a plurality of chip regions are transferred to the main surface of the wafer 9. In the above description, a region where double exposure has not been performed (for example, a chip region located on the outermost periphery of the main surface of the wafer 9) is generated. In the state, the double exposure process was performed.

  Next, the scanner will be described. FIG. 19 shows an example of the scanner 10. The scanner 10 is, for example, a scanning reduction projection exposure apparatus with a reduction ratio of 4: 1. The exposure conditions of the scanner 10 are as described above with reference to FIGS.

  The exposure light EXL emitted from the exposure light source 10a illuminates the mask (reticle) 1A through the fly-eye lens 10b, the aperture 10c, the condenser lenses 10d1, 10d2, and the mirror 10e. Of the optical conditions, the coherent factor was adjusted by changing the size of the opening of the aperture 10f. A pellicle PE is provided on the mask 1A to prevent pattern transfer failure due to adhesion of foreign matter. The mask pattern drawn on the mask 1A is projected onto the photoresist film on the main surface of the wafer 9 which is the sample substrate via the projection lens 10g. The mask 1A is placed on the mask stage 10i2 controlled by the mask position control means 10h and the mirror 10i1, and its center and the optical axis of the projection lens 10g are accurately aligned.

  The wafer 9 is vacuum-sucked on the sample stage 10j. The sample stage 10j is placed on the Z stage 10k that can move in the optical axis direction of the projection lens 10g, that is, the direction perpendicular to the wafer placement surface of the sample stage 10j (Z direction), and further the wafer of the sample stage 10j. It is mounted on an XY stage 10m that can move in a direction parallel to the mounting surface. Since the Z stage 10k and the XY stage 10m are driven by the respective driving means 10p and 10q in accordance with a control command from the main control system 10n, they can be moved to desired exposure positions. The position is accurately monitored by the laser length measuring instrument 10s as the position of the mirror 10r fixed to the Z stage 10k. Further, the surface position of the wafer 9 is measured by a focus position detecting means included in a normal exposure apparatus. By driving the Z stage 10k according to the measurement result, the main surface of the wafer 9 can always coincide with the imaging surface of the projection lens 10g.

  The mask 1A and the wafer 9 are driven in synchronization according to the reduction ratio, and the mask pattern is reduced and transferred onto the photoresist film on the main surface of the wafer 9 while the exposure region scans the main surface of the mask 1A. At this time, the position of the main surface of the wafer 9 is also dynamically driven and controlled for the scanning of the wafer 9 by the above-described means. When the circuit pattern on the mask 1A is superimposed and exposed on the circuit pattern formed on the wafer 9, the position of the mark pattern formed on the wafer 9 is detected using the alignment detection optical system 10t, and the detection result Then, the wafer 9 is positioned and superimposed and transferred. The main control system 10n is electrically connected to the network device 10u, and can remotely monitor the status of the scanner 10.

  FIG. 20 is an explanatory diagram schematically showing the scanning exposure operation of the scanner 10, and FIG. 21 is an explanatory diagram schematically showing the exposure area of the scanner 10 extracted. 20 and 21 are hatched to make the drawings easy to see.

  In the scanning exposure process using the scanner 10, the mask 1A and the wafer 9 are moved in the opposite directions while keeping their main surfaces parallel to each other. That is, since the mask 1A and the wafer 9 are in a mirror-symmetrical relationship, the scanning direction of the mask 1A and the scanning direction of the wafer 9 during the exposure process are indicated by the arrows in FIG. As shown in scan directions G and H, the directions are reversed. The mask 1A is set so that the transfer areas 2A and 2B are arranged along the scanning direction of the scanner 10. When the driving distance is a reduction ratio of 4: 1, the movement amount of the wafer 9 is 1 with respect to the movement amount 4 of the mask 1A. At this time, the exposure light EXL is irradiated to the mask 1A through the planar rectangular slit 10fs of the aperture 10f. That is, the slit-shaped exposure area (exposure zone) SA1 included in the effective exposure area 10ga of the projection lens 10g is used as an effective exposure area. Although not particularly limited, the width (short dimension) of the slit 10 fs is usually, for example, about 4 to 7 mm on the wafer 9. Then, the slit-shaped exposure area SA1 is continuously moved (scanned) in the width (short) direction of the slit 10fs (that is, in a direction orthogonal or obliquely intersecting with the longitudinal direction of the slit 10fs), and image forming optics. The main surface of the wafer 9 is irradiated through the system (projection lens 10g). Thereby, the mask pattern (integrated circuit pattern, line pattern in the first embodiment) in the transfer areas 2A and 2B of the mask 1A is transferred to each of the plurality of chip areas CA of the wafer 9. Here, only the part necessary for explaining the function of the scanner 10 is shown, but the other parts necessary for the ordinary scanner are the same in the ordinary range.

  FIG. 22 shows an exposure area SA2 (hatched for easy viewing) when a stepper is used. In the stepper, when exposure of one shot (one chip or a plurality of chips) is completed, the stage is moved to the next shot position, and the same exposure is repeated to expose the entire main surface of the wafer. In the case of a stepper, a planar square exposure area SA2 within the effective exposure area 10ga of the projection lens 10g is used as an effective exposure area. The four corners of the exposure area SA2 are inscribed in the effective exposure area 10ga. In the method of the first embodiment, a stepper can be used as an exposure apparatus. However, since the projection lens 10g usually has various aberrations, a multiple exposure using a stepper provides a good pattern as designed. It is difficult to form. On the other hand, in the exposure process using the scanner 10, a positional shift caused by lens aberration occurs in a direction orthogonal to the scanning direction, but the same shape is maintained because the lens aberration is the same in the scanning direction. The first embodiment uses the characteristics of this scanner. When a scanner is used, the patterns transferred in the transfer areas 2A and 2B are almost the same in the direction perpendicular to the scan direction. However, they are formed in substantially the same shape in the scanning direction. This is also why the transfer areas 2A and 2B for performing overlay exposure are arranged along the scanning direction. Therefore, even with double exposure, a pattern can be formed with high overlay accuracy.

(Embodiment 2)
In the second embodiment, the processing of the shifter pattern end will be described.

  FIGS. 23 and 24 are plan views of the main part of the mask 1A, and show the state of the end portions of the light shielding patterns 3b and 3c and the shifters 7a and 7b arranged in the transfer regions where the overlay exposure is performed. FIG. 25 shows planar contour lines of the light intensity obtained when the exposure is performed with the images shown in FIGS. 23 and 24 show the coordinates x30 to x34 and the coordinate y30 so that the positional relationship of the overlay exposure can be understood, and the shading patterns 3b and 3c and the shifters 7a and 7b are hatched for easy understanding of the drawings. .

  As shown in FIGS. 23 and 24, when the pattern end portions of the shifters 7a and 7b are aligned with the end portions of the light shielding patterns 3b and 3c, the light intensity decreases at the end portions of the light shielding patterns 3b and 3c. As shown in FIG. 3, there is a case where the end of the transfer pattern transferred to the photoresist film due to the overexposure of the light shielding patterns 3b and 3c may be thickened. In this case, it is necessary to arrange the end portions of adjacent shifters so as not to be close to each other. An example of this avoidance method will be described with reference to FIGS.

  26 and 27 are plan views of the main part of the mask 1B according to the second embodiment, in which the light shielding patterns 3b and 3c and shifters 7a and 7b arranged in each of the transfer regions where the overlay exposure is performed. The state of the end is shown. 26 and 27 show the coordinates x30 to x34 and the coordinate y30 so that the positional relationship of the overlay exposure can be understood, and the shading patterns 3b and 3c and the shifters 7a and 7b are hatched for easy understanding of the drawings. . Here, in each transfer region, intermediate shifters 7as and 7bs are arranged at the ends of the shifters 7a and 7b. The intermediate shifters 7as and 7bs are auxiliary shifters for eliminating the thickening of the pattern end, and the phase of the light transmitted through the intermediate shifters 7as and 7bs is relative to the phase of the light transmitted through the shifters 7a and 7b. Is shifted 90 degrees. That is, the light transmitted through the shifters 7a and 7b is transmitted through the intermediate shifters 7as and 7bs while the phase is 180 degrees out of phase with respect to the light transmitted through the light transmission region where the shifters 7a and 7b are not disposed. The phase of the transmitted light is shifted by 90 degrees with respect to the light transmitted through the light transmission region where the shifters 7a and 7b are not disposed. FIG. 28 shows planar contours of the light intensity obtained when the above FIG. 26 and FIG. 27 are overlaid and exposed. It can be seen that the thickness of the end of the transfer pattern transferred to the photoresist film by the overlap exposure of the light shielding patterns 3b and 3c is almost eliminated.

  FIG. 29 shows an example of a cross-sectional view taken along the line YA-YA in FIG. The shifter 7b (7a) and the intermediate shifter 7bs (7as) are formed by digging a groove in the main surface of the mask substrate 6. The depth of the groove of the intermediate shifter 7bs (7as) is approximately half the depth of the groove of the shifter (7b7a). Thereby, the phase of the light transmitted through the shifter 7b (7a) is shifted by 180 degrees with respect to the phase of the light transmitted through the light transmission region without the shifter, whereas the phase of the light transmitted through the intermediate shifter 7bs (7as) is changed. The phase is shifted by 90 degrees with respect to the phase of the light transmitted through the light transmission region without the shifter. 30 to 32 show an example of a fragmentary cross-sectional view of the mask 1B shown in FIG. 29 during the manufacturing process. First, as shown in FIG. 30, as in the first embodiment, the light shielding pattern 3c (3b) is formed on the main surface of the mask substrate 6 using the resist pattern ER1 as an etching mask, and then the resist pattern ER1 is removed. . Subsequently, as shown in FIG. 31, after forming a resist pattern ER2 in which the formation region of the shifter 7b (7a) is exposed and the others are covered, this is used as an etching mask in the same manner as in the first embodiment. A groove 7b1 (7a1) for forming the shifter 7b (7a) is formed in the mask substrate 6. The depth J of the groove 7b1 (7a1) at this time is 90 degrees out of phase with the light transmitted through the groove 7b1 (7a1) with respect to the phase of the light transmitted through the light transmission region without the groove 7b1 (7a1). Make the depth like this. Thereafter, after removing the resist pattern ER2, through an electron beam lithography process, as shown in FIG. 32, the formation regions of the intermediate shifters 7bs (7as) and the shifters 7b (7a) are exposed and the others are covered. A resist pattern ER3 is formed. Subsequently, an intermediate shifter 7bs (7as) and a shifter 7b (7a) are formed using the resist pattern ER3 as an etching mask. At this time, the depth of the groove at the intermediate shifter 7bs (7as) is set to the depth J. Thereby, in the intermediate shifter 7bs (7as), the phase of the transmitted light can be shifted by 90 degrees with respect to the phase of the light transmitted through the light transmission region without the shifter. In the shifter 7b (7a), the depth K of the groove is twice the depth J, so that the phase of the transmitted light is shifted by 180 degrees with respect to the phase of the light transmitted through the light transmission region without the shifter. Can be.

  FIG. 33 shows another example of a cross-sectional view taken along line YA-YA of FIG. The shifter 7b (7a) and the intermediate shifter 7bs (7as) are formed by depositing a film on the main surface of the mask substrate 6 (shifter film top placement method or top placement shifter). That is, the shifter 7b (7a) is formed of a laminated film of the shifter film 7f1 and the shifter film 7f2 thereon. The intermediate shifter 7bs (7as) is formed of a single film of the shifter film 7f1. The thickness L of the shifter film 7f1 is such that the phase of the light transmitted through the single film of the shifter film 7f1 is shifted by 90 degrees with respect to the phase of the light transmitted through the light transmission region without the shifter film 7f1. ing. The thickness M of the laminated film of the shifter film 7f1 and the shifter film 7f2 is twice the thickness L of the shifter film 7f1, and the phase of the light transmitted through the laminated film is light transmission without the laminated film. The thickness is 180 degrees with respect to the phase of the light transmitted through the region.

  The shifter films 7f1 and 7bf2 are made of, for example, a resist film or an SOG (Spin On Glass) film. When the shifter films 7f1 and 7f2 are formed of resist films, they can be exposed and developed as they are, so that the shifters 7a and 7b can be easily formed, and the pattern formation accuracy of the shifters 7a and 7b can be improved. On the other hand, when the shifter films 7f1 and 7f2 are formed of SOG films, the durability can be greatly improved as compared with the resist film, so that the life of the mask 1B can be improved.

  As described above, in the second embodiment, in addition to the effects obtained in the first embodiment, the following effects can be obtained. That is, by providing the intermediate shifters 7as and 7bs at the pattern ends of the shifters 7a and 7b, the thickness of the pattern ends transferred to the positive photoresist film can be reduced or eliminated.

(Embodiment 3)
In the third embodiment, a method in which a shifter is formed of a film (shifter film top placement method or top placement shifter) will be described.

  34 shows a cross-sectional view of a portion corresponding to the XA-XA line in FIG. 1 of the transfer region 2A of the mask 1C of Embodiment 3, and FIG. 35 shows the transfer region 2B of the mask 1C integrated with FIG. Sectional drawing of the location corresponded to the XB-XB line of is shown.

  In the mask 1C of the third embodiment, the shifters 7a and 7b are formed of, for example, a resist film or an SOG (Spin On Glass) film. The planar shape of the mask 1C is the same as FIG. When the shifter is formed of a film, the thickness of the shifter in the main surface of the mask substrate 6 may vary depending on the in-plane position and shape of the underlying pattern, and may not be uniform as a whole. If the shifters 7a and 7b have different thicknesses, the phase of transmitted light also changes, which is a problem in the exposure process in which the pattern is transferred by only one exposure. When a pattern is transferred by only one exposure, the transparency of the resist film for forming the shifter or the SOG film may be a problem. On the other hand, in the third embodiment, by performing the overlay exposure as described above, the absolute value control (error tolerance) of the phase of the transmitted light can be relaxed, so that each transfer region 2A, Even if the thickness of the shifters 7a and 7b slightly changes in 2B, exposure can be performed without any problem. Further, the transparency of the shifter resist film and the SOG film may not be 100%. It should be noted that since the position and shape of the main surface of the mask substrate 6 are substantially the same in the area where the transfer areas 2A and 2B are subjected to the overlay exposure, the thickness N of the shifter 7a in the area where the overlay exposure is performed and the shifter 7b Is substantially equal to the thickness Q. Therefore, there is no problem of the phase of transmitted light at the overlapping portion.

  In order to manufacture such a mask 1C, after forming the light shielding patterns 3a and 3b on the main surface of the mask substrate 6 as described in the first embodiment, a resist is formed on the main surface of the mask substrate 6. A shifter film made of a film, an SOG film, or the like is deposited, and the shifter film is patterned through a lithography process to form shifters 7a and 7b. When the shifter film is formed of a resist film, it can be exposed and developed as it is, so that the shifters 7a and 7b can be easily formed, and the pattern formation accuracy of the shifters 7a and 7b can be improved. On the other hand, when the shifter film is formed of an SOG film, the durability can be greatly improved as compared with the resist film, so that the life of the mask 1C can be improved.

(Embodiment 4)
In the fourth embodiment, a modified example of the mask will be described.

  FIG. 36 shows a cross-sectional view of the main part of the mask 1D of the fourth embodiment (a cross-sectional view of a portion corresponding to the XA-XA line of FIG. 1). In this mask 1D, a shifter film 7f is deposited on the main surface of the mask substrate 6, and light shielding patterns 3a, 3b, 3c are formed thereon.

  The shifter film 7f is formed with a thickness (= the above formula of Z) suitable for the purpose of acting as a phase shifter. That is, the phase of the transmitted light is inverted by 180 degrees between the light transmitted through the shifter film 7f and the light transmitted through the light transmission region without the shifter film 7f. The shifter film 7f is made of, for example, an SOG (Spin On Glass) film having a light transmittance and a refractive index equivalent to or similar to those of the mask substrate 6.

  The groove-type shifter 7a (7b) is formed by removing the shifter film 7f in the light transmission region, and the main surface of the mask substrate 6 is exposed from the bottom surface of the shifter 7a (7b). When the shifter 7a (7b) is formed, the etching selectivity between the mask substrate 6 and the shifter film 7f is increased so that the etching rate of the shifter film 7f is higher than the etching rate of the mask substrate 6. . That is, the groove type shifter 7a (7b) is formed using the mask substrate 6 as an etching stopper. Accordingly, the depth of the groove-type shifter 7a (7b) (that is, the thickness of the shifter film 7f) and the flatness of the bottom surface of the groove-type shifter 7a (7b) can be formed with extremely high accuracy. For this reason, the phase error of the transmitted light can be greatly reduced or eliminated, so that the dimensional accuracy of the pattern transferred to the main surface of the wafer 9 can be greatly improved. Note that the plan view, the exposure method, the exposure conditions, and the like of the mask 1D are the same as those in the first to third embodiments, and thus description thereof is omitted.

(Embodiment 5)
In the fifth embodiment, an example in which the exposure method using the masks of the first to fourth embodiments is applied to, for example, a DRAM (Dynamic Random Access Memory) manufacturing method will be described.

  FIG. 37 is a plan view of the main part of the memory cell region of the DRAM manufactured using the masks of the first to fourth embodiments. Further, the left side of FIG. 38 is a cross-sectional view taken along the line XC-XC in FIG. 37, and the right side of FIG.

  First, the memory area will be described. The substrate 9S is a part constituting a planar quadrilateral chip cut out from the wafer 9, and is made of, for example, p-type single crystal silicon. A p-type well PWL is formed on the main surface of the substrate 9S, and DRAM memory cells are formed in the p-type well PWL. Note that the p-type well PWL in the area where the memory cells are formed (memory array) is formed in the lower part of the substrate 9S in order to prevent noise from entering from an input / output circuit or the like formed in another area of the substrate 9S. It is electrically isolated from the substrate 9S by the buried n-type well DNW.

  The memory cell has a stacked structure in which an information storage capacitive element (simply referred to as a capacitor) 16 is disposed above a memory cell selection MISFET (simply referred to as a select MIS) 15. The selection MIS 15 is composed of an n-channel MISFET and is formed in the active region LR of the p-type well PWL. The active region LR is configured by an elongated island pattern extending straight along the first direction XX in FIG. 37, and each active region LR has one of a source and a drain (n-type semiconductor region). Two selection MISs 15 sharing each other are formed adjacent to each other in the first direction XX. The element isolation region surrounding the active region LR is formed by a groove-type isolation portion (trench isolation) 17. The groove-type isolation part 17 is formed by embedding an insulating film made of silicon oxide or the like in a shallow groove opened in the p-type well PWL.

  The selection MIS 15 has a gate insulating film 18, a gate electrode 19m, and a pair of n-type semiconductor regions 20 and 20 constituting a source and a drain. The gate insulating film 18 is made of, for example, silicon oxide. The gate electrode 19m is formed by a part of the word line WL (a portion overlapping the active region LR), and linearly extends along the second direction YY with the same width and the same space. The gate electrode 19m (word line WL) is, for example, a barrier metal made of a low resistance polycrystalline silicon film doped with an n-type impurity such as P (phosphorus) and a WN (tungsten nitride) film formed thereon. It has a polymetal structure composed of a layer and a refractory metal film such as a W (tungsten) film formed thereon. Since the gate electrode 19m (word line WL) having a polymetal structure has a lower electrical resistance than a gate electrode formed of a polycrystalline silicon film or a polycide film, the signal delay of the word line can be reduced. However, the gate electrode 19m may be composed of a single film of a polycrystalline silicon film, or may have the polycide structure in which a silicide film such as tungsten silicide is stacked on the polycrystalline silicon film. A cap insulating film 21 made of a silicon nitride film or the like is formed on the gate electrode 19m (word line WL). The upper and side walls of the cap insulating film 21 and the side wall of the gate electrode 19m (word line WL) For example, an insulating film 22 made of, for example, a silicon nitride film is formed. The cap insulating film 21 and the insulating film 22 of the memory array function as an etching stopper when a contact hole is formed on the source and drain (n-type semiconductor regions 20 and 20) of the selection MIS 15 by self-alignment (self-alignment). .

The capacitor 16 has a lower electrode (storage electrode) 16a, an upper electrode (plate electrode) 16b, and a capacitive insulating film (dielectric film) 16c made of Ta ₂ O ₅ (tantalum oxide) or the like provided therebetween. doing. The lower electrode 16a is made of, for example, a low resistance polycrystalline silicon film doped with P (phosphorus), and the upper electrode 16b is made of, for example, a TiN film. The lower electrode 16a of the capacitor 16 is electrically connected to one of the source and drain n-type semiconductor regions 20 of the selection MIS 15 through plugs PLG1 and PLG2. Plugs PLG1 and PLG2 are made of, for example, polycrystalline silicon containing phosphorus (P).

  The other n-type semiconductor region 20 of the source and drain of the selection MIS 15 is electrically connected to the bit line BL through the plug PLG1 at the center of the memory cell. The bit line BL is made of a refractory metal film such as tungsten, for example, and is disposed above the groove-type separation part 17 and linearly extends along the first direction XX with the same width and the same space. doing. The bit line BL and the first layer wiring ML1 of the peripheral circuit are formed in the same process. By forming the bit line BL with a metal (tungsten) having high heat resistance and electromigration resistance, disconnection can be reliably prevented even when the width of the bit line BL is reduced.

  Next, the peripheral circuit area will be described. A p-type well PWL and an n-type well NWL are formed on the substrate 9S in the peripheral circuit region. An nMIS 25N is formed in the p-type well, and a pMIS 25P is formed in the n-type well. The nMIS 25N includes a gate insulating film 18, a gate electrode 19p, and a pair of n-type semiconductor regions 26 and 26 constituting a source and a drain. The n-type semiconductor region 26 contains, for example, phosphorus or arsenic (As). The nMIS 25P has a gate insulating film 18, a gate electrode 19p, and a pair of p-type semiconductor regions 27 and 27 constituting a source and a drain. The p-type semiconductor region 27 contains, for example, boron (B). The n-type semiconductor region 26 and the p-type semiconductor region 27 have an LDD (Lightly Doped Drain) configuration. The gate electrodes 19p of the nMIS 25N and pMIS 25P in the peripheral circuit region have the same configuration as the gate electrode 19m of the selection MIS 15. A sidewall 28 made of, for example, silicon oxide is formed on the side surface of the gate electrode 19p in the peripheral circuit region. The first layer wiring ML1 in the peripheral circuit region is electrically connected to the n-type semiconductor region 26 and the p-type semiconductor region 27 through the plug PLG3 in the contact hole CH. Reference numerals 29a to 29e on the substrate 9S indicate an insulating film made of, for example, silicon oxide, and reference numeral 30 indicates an insulating film made of, for example, silicon nitride. A symbol ML2 indicates a second layer wiring. The second layer wiring ML2 is mainly made of aluminum (Al), for example, and is patterned by a photolithography process and a dry etching process.

  Next, in the fifth embodiment, a method of forming the gate electrodes 19m and 19p in the memory region and the peripheral circuit region using the masks 1A to 1D described in the first to fourth embodiments will be described with reference to FIGS. Will be described.

  First, as shown in FIG. 39, the conductor film 19 is deposited on the main surface (device forming surface) of the substrate 9S (the wafer 9 at this stage) after the gate insulating film 18 in the memory region and the peripheral circuit region is formed. . The conductor film 19 is formed by depositing, for example, a low resistance polycrystalline silicon film, a barrier film such as tungsten nitride, and a metal film such as tungsten sequentially from the lower layer by a CVD (Chemical Vapor Deposition) method or the like. Subsequently, after depositing a cap insulating film 21 made of, for example, silicon nitride on the conductor film 19, a photoresist film PR1 is applied thereon. Thereafter, the substrate 9S and the mask 1A are placed on the scanner 10, and then the scanning exposure process (double exposure process) is performed as described above using the scanner 10 and the mask 1A, whereby the main part of the substrate 9S. The gate electrode pattern is transferred to the photoresist film PR1 on the surface. Thereafter, development processing is performed to form a pattern of the photoresist film PR1 for forming the gate electrode as shown in FIG. At this time, the pattern of the photoresist film PR1 for forming the gate electrode in the memory area (left side of FIG. 40) is transferred by the light shielding patterns 3b1, 3b2, 3c1, 3c2 for transferring the fine pattern of the mask 1A. is there. On the other hand, the pattern of the photoresist film PR1 for forming the gate electrode in the peripheral circuit region (right side in FIG. 40) is transferred by the light shielding patterns 3b3 and 3c3 for transferring the relatively wide pattern of the mask 1A. is there. Thereafter, the substrate 9S (that is, the wafer 9) is etched using the pattern of the photoresist film PR1 as an etching mask to pattern the cap insulating film 21, as shown in FIG. The PR1 pattern is removed. Thereafter, the substrate 9S is etched using the remaining pattern of the cap insulating film 21 as an etching mask to form the word line WL and the gate electrode 19m in the memory region, and the gate electrode 19p in the peripheral circuit region. Form.

  As described above, according to the fifth embodiment, a DRAM having a wiring dimension of 65 nm node (for example, about 70 to 90 nm) can be manufactured using an ArF excimer laser as an exposure light source. In addition, since the number of defects in the chip can be reduced, the number of bit relief chips can be reduced.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

For example, in the first to fifth embodiments, the double exposure has been described. However, the present invention is not limited to this, and various modifications can be made. Also good. In this embodiment, since a phase shift mask is used, the number of overlays is preferably an even number in consideration of the occurrence of phase inversion. By increasing the number of times of overexposure in this way, pattern defects can be reduced or eliminated, so that occurrence of disconnection failure, short-circuit failure, and the like can be reduced or eliminated. Further, an i-line with an exposure wavelength of 365 nm, a KrF excimer laser with an exposure wavelength of 248 nm, or an F ₂ excimer laser with an exposure wavelength of 157 nm may be used as the exposure light source. Further, as the modified illumination for the exposure light source (illumination with reduced illuminance at the center), for example, multipole illumination such as oblique illumination, quadrupole illumination, and pentapole illumination may be used. Also, a super-resolution technique using a pupil filter equivalent to modified illumination may be used.

  In the first to fifth embodiments, the case where the wafer is a semiconductor wafer having silicon as a substrate has been described. However, the present invention is not limited to this, and the wafer may be a sapphire substrate, a glass substrate, other insulation, In some cases, it may be an anti-insulating or semiconductor substrate or a composite substrate thereof. In addition to semiconductor devices such as silicon wafers and sapphire substrates, which are made on a semiconductor or insulator substrate, semiconductor devices are TFT (Thin-Film-Transistor) and STN (Super-) unless otherwise specified. It includes those made on other insulating substrates such as glass such as Twisted-Nematic) liquid crystal.

  In the fifth embodiment, the case where the method is applied to a photoresist pattern transfer method for forming word lines and gate electrodes of a DRAM has been described. However, the present invention is not limited to this. For example, impurities are added to a wafer. The present invention can also be applied to a transfer method of a photoresist pattern used as a mask at the time of introduction.

  In the above description, the case where the invention made mainly by the present inventor is applied to the method of manufacturing a semiconductor device which is a field of use as the background has been described. However, the present invention is not limited to this and can be applied in various ways. The present invention can also be applied to manufacturing methods other than semiconductor devices such as liquid crystal display devices and micromachines.

  The present invention can be applied to the manufacturing industry of products that require fine processing.

It is a whole top view of the mask used with the manufacturing method of the semiconductor device which is one embodiment of this invention. It is sectional drawing of the XA-XA line | wire of FIG. It is sectional drawing of the XB-XB line | wire of FIG. It is a graph of an example of light intensity distribution on the wafer of the exposure light which permeate | transmitted the coordinate x3-x14 of FIG. 2, and its vicinity. It is explanatory drawing for demonstrating the unnecessary pattern erasing effect resulting from a phase shifter edge, Comprising: It is explanatory drawing of the light intensity distribution obtained by a part of upper transfer area | region of the mask of FIG. It is explanatory drawing for demonstrating the unnecessary pattern erasing effect resulting from a phase shifter edge, Comprising: It is explanatory drawing of the light intensity distribution obtained in a part of lower transfer area | region of the mask of FIG. It is explanatory drawing for demonstrating the unnecessary pattern erasing effect resulting from a phase shifter edge, Comprising: It is explanatory drawing of the light intensity distribution obtained by superimposing and exposing the transfer area | region of the upper and lower stages of the mask of FIG. It is explanatory drawing for demonstrating the improvement effect of the pattern dimension difference resulting from a phase shifter, Comprising: It is explanatory drawing of the light intensity distribution obtained by a part of one transcription | transfer area | region superimposed. It is explanatory drawing for demonstrating the improvement effect of the pattern dimension difference resulting from a phase shifter, Comprising: It is explanatory drawing of the light intensity distribution obtained by a part of other transcription | transfer area | region superimposed. It is explanatory drawing for demonstrating the improvement effect of the pattern dimension difference resulting from a phase shifter, Comprising: It is explanatory drawing of the light intensity distribution obtained by superimposing and exposing the transfer area | region of FIG. 9 and FIG. It is a principal part enlarged plan view of the mask which shows the example of arrangement | positioning of the light-shielding pattern and phase shifter of the transfer area | region of a mask for forming an actual device pattern. FIG. 13 is an enlarged plan view of a main part of a mask showing an example of arrangement of a light shielding pattern and a phase shifter in a portion overlapping with the transfer region in FIG. 11, which is a main part of a mask transfer region for forming an actual device pattern. is there. It is sectional drawing of the mask substrate in the manufacturing process of the mask of FIG. It is sectional drawing of the mask substrate following FIG. FIG. 12 is a cross-sectional view of the mask substrate following FIG. 11. It is the whole wafer top view at the time of a multiple exposure process. FIG. 17 is an overall plan view of a wafer during a multiple exposure process subsequent to FIG. 16. FIG. 18 is an overall plan view of a wafer in a multiple exposure process subsequent to FIG. 17. It is explanatory drawing of an example of the exposure apparatus used with the manufacturing method of the semiconductor device which is one embodiment of this invention. It is explanatory drawing of the principal part of the exposure apparatus of FIG. It is explanatory drawing of the exposure area | region of the exposure apparatus of FIG. 19 and FIG. It is explanatory drawing of the exposure area | region of the exposure apparatus different from FIG. It is a principal part top view of the mask for demonstrating the malfunction by the method of shifter arrangement | positioning. It is explanatory drawing of the malfunction by the method of arrangement | positioning of a phase shifter, Comprising: It is the principal part top view of the mask of the part of the mask of FIG. It is explanatory drawing of the contour line of the plane of the light intensity obtained when FIG. 23 and FIG. 24 are overlaid and exposed. It is a principal part top view of the mask used with the manufacturing method of the semiconductor device which is other embodiment of this invention. It is a principal part top view of the mask of the part of the mask of FIG. It is explanatory drawing of the contour line of the plane of the light intensity obtained when FIG. 25 and FIG. It is sectional drawing of an example of the YA-YA line | wire of FIG. FIG. 30 is an essential part cross sectional view of the mask of FIG. 29 during a manufacturing step. FIG. 31 is an essential part cross sectional view of the mask during a manufacturing step following FIG. 30; FIG. 32 is an essential part cross-sectional view of the mask during the manufacturing process following FIG. 31; FIG. 30 is a cross-sectional view of another example of the mask different from FIG. 29 and taken along line YA-YA in FIG. 27. It is sectional drawing of the location corresponded to the XA-XA line | wire of FIG. 1 of the mask used with the manufacturing method of the semiconductor device which is other embodiment of this invention. FIG. 35 is a cross-sectional view of the same mask as in FIG. 34 and corresponding to the XB-XB line in FIG. 1. It is sectional drawing of the location corresponded to the XA-XA line | wire of FIG. 1 of the mask used with the manufacturing method of the semiconductor device which is further another embodiment of this invention. It is a principal part top view of the memory area | region of the semiconductor device which is other embodiment of this invention. It is principal part sectional drawing of the memory area | region and peripheral circuit area | region of the semiconductor device which is other embodiment of this invention. FIG. 39 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device of FIGS. 37 and 38; FIG. 40 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device following that of FIG. 39; FIG. 41 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device following that of FIG. 40; It is principal part sectional drawing of the phase shift mask which this inventor examined. FIG. 43 is a graph showing an intensity distribution on a semiconductor wafer of light transmitted through the phase shift mask of FIG. 42. FIG. 43 is a plan view of a principal part of a semiconductor wafer showing a pattern transferred to the photoresist film of the semiconductor wafer by the phase shift mask of FIG. It is principal part sectional drawing of the phase shift mask which has a saddle type groove | channel phase shifter which this inventor examined. It is a graph which shows intensity distribution on the semiconductor wafer of the light which permeate | transmitted the phase shift mask of FIG. FIG. 46 is a substantial part plan view of the semiconductor wafer showing a pattern transferred to the photoresist film of the semiconductor wafer by the phase shift mask of FIG. 45.

Explanation of symbols

1A, 1B, 1C, 1D Mask 2A, 2B Transfer area 3 Light shielding film 3a Light shielding pattern 3b, 3b1, 3b2, 3b3 Light shielding pattern 3c, 3c1, 3c2, 3c3 Light shielding pattern 6 Mask substrate 7a, 7b Phase shifter 7f, 7f1, 7f2 Shifter films 7as, 7bs Intermediate shifter 9 Semiconductor wafer 9S Substrate 10 Scanner 10a Exposure light source 10b Fly eye lens 10c Aperture 10d1, 10d2 Condenser lens 10e Mirror 10f Aperture 10fs Slit 10g Projection lens 10ga Effective exposure area 10h Mask position control means 10i1 Mirror 10i2 Mask Stage 10j Sample stage 10k Z stage 10m XY stage 10n Main control system 10p, 10q Drive means 10r Mirror 10s Laser length measuring instrument 10t Alignment detection optical system 10u Network device 15 MISFET for memory cell selection
16 Capacitance element for information storage 16a Lower electrode 16b Upper electrode 16c Capacitor insulating film 17 Separating part 18 Gate insulating film 19 Conductive film 19m Gate electrode 19p Gate electrode 20 N-type semiconductor region 21 Cap insulating film 22 Insulating film 25N n-channel MISFET
25P p-channel MISFET
26 n-type semiconductor region 27 p-type semiconductor region 28 sidewalls 29a to 29e insulating film 30 insulating film 50 phase shift mask 50a mask substrate 50b light shielding pattern 50c light transmission pattern 50d phase shifters 52a and 52b photoresist patterns 55a and 55b photoresist patterns ER1 to ER3 resist pattern PR1 photoresist film EXL exposure light CA chip area SA1, SA2 exposure area PWL p-type well NWL n-type well DNW buried n-type well LR active areas PLG1, PLG2, PLG3 plug BL bit line WL word line ML1 First layer wiring ML2 Second layer wiring

Claims (19)

(A) depositing a positive photoresist film on the main surface of the wafer;
(B) performing a reduced projection exposure process using a mask on the wafer to transfer a desired pattern to the positive photoresist film,
The step (b) includes a step of exposing the first transfer region and the second transfer region of the mask so as to overlap one region of the positive photoresist film,
The first transfer region and the second transfer region include a light transmission region as a background,
A plurality of light shielding patterns are disposed in each of the first transfer region and the second transfer region,
A phase shifter that reverses the phase of the transmitted light with respect to the light transmitted through the light transmission region is disposed adjacent to the plurality of light shielding patterns in the first transfer region and the second transfer region,
The shape, size and arrangement of the light-shielding patterns of the first transfer area and the second transfer area are the same,
The method of manufacturing a semiconductor device, wherein the phase shifters of the first transfer region and the second transfer region are arranged so as to be inverted with respect to each other.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the first transfer region and the second transfer region are arranged on the same main surface of the same mask.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the reduced projection exposure process is performed by scanning exposure.   4. The method of manufacturing a semiconductor device according to claim 3, wherein the first transfer region and the second transfer region are disposed on the same main surface of the same mask, and in the reduction projection exposure process, A method of manufacturing a semiconductor device, wherein the scanning exposure is performed in a state where a mask is set so that a transfer region and the second transfer region are arranged side by side along the direction of the scanning exposure.   2. The method of manufacturing a semiconductor device according to claim 1, wherein an ArF excimer laser is used as exposure light at the time of the reduced projection exposure process.   2. The method of manufacturing a semiconductor device according to claim 1, wherein a single exposure amount to one region of the positive type photoresist film at the time of the reduction projection exposure process divides the necessary exposure amount by the number of multiple exposures. A method for manufacturing a semiconductor device, characterized by:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the phase shifter is a groove type shifter formed by a groove dug in a mask substrate.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the phase shifter is an upper shifter formed by a phase shifter film deposited on a mask substrate.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the phase shifter film is a resist film.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the phase of the phase shifter is larger than 180 degrees ± 5 degrees.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the desired pattern transferred to the positive photoresist film is a pattern for forming a line pattern. (A) depositing a positive photoresist film on the main surface of the wafer;
(B) performing a reduced projection exposure process using a mask on the wafer to transfer a desired pattern to the positive photoresist film,
The step (b) includes a step of exposing the first transfer region and the second transfer region of the mask so as to overlap one region of the positive photoresist film,
The first transfer region and the second transfer region include a light transmission region as a background,
A plurality of light shielding patterns are disposed in each of the first transfer region and the second transfer region,
Among the plurality of light shielding patterns in the first transfer area and the second transfer area, a phase shifter is arranged at the adjacent position so that the phase of the transmitted light is inverted with respect to the light transmitted through the light transmission area. There are a first light shielding pattern and a second light shielding pattern in which the phase shifter is not disposed,
The shape, size and arrangement of the light-shielding patterns of the first transfer area and the second transfer area are the same,
The method of manufacturing a semiconductor device, wherein the phase shifters of the first transfer region and the second transfer region are arranged so as to be inverted with respect to each other.   13. The method of manufacturing a semiconductor device according to claim 12, wherein a dimension in a short direction of the first light shielding pattern is smaller than a dimension in a short direction of the second light shielding pattern. (A) depositing a conductor film on the main surface of the wafer;
(B) depositing a positive photoresist film on the conductor film;
(C) transferring a desired pattern to the positive photoresist film by subjecting the wafer to a reduced projection exposure process using a mask;
(D) forming a pattern of a positive type photoresist film by performing development processing on the positive type photoresist;
(E) forming a line pattern made of the conductor film on the main surface of the wafer by etching the conductor film exposed from the pattern of the positive photoresist film;
The step (c) includes a step of exposing the first transfer region and the second transfer region of the mask so as to overlap one region of the positive photoresist film,
The first transfer region and the second transfer region include a light transmission region as a background,
A plurality of light shielding patterns are disposed in each of the first transfer region and the second transfer region,
A phase shifter that reverses the phase of the transmitted light with respect to the light transmitted through the light transmission region is disposed adjacent to the plurality of light shielding patterns in the first transfer region and the second transfer region,
The shape, size and arrangement of the light-shielding patterns of the first transfer area and the second transfer area are the same,
The method of manufacturing a semiconductor device, wherein the phase shifters of the first transfer region and the second transfer region are arranged so as to be inverted with respect to each other.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the reduced projection exposure process is performed by scanning exposure.   16. The method of manufacturing a semiconductor device according to claim 15, wherein the first transfer region and the second transfer region are disposed on the same main surface of the same mask, and in the reduction projection exposure process, A method of manufacturing a semiconductor device, wherein the scanning exposure is performed in a state where a mask is set so that a transfer region and the second transfer region are arranged side by side along the direction of the scanning exposure.   15. The method of manufacturing a semiconductor device according to claim 14, wherein the line pattern is a word line of a DRAM. (A) depositing a conductor film on the main surface of the wafer;
(B) depositing a positive photoresist film on the conductor film;
(C) transferring a desired pattern to the positive photoresist film by subjecting the wafer to a reduced projection exposure process using a mask;
(D) forming a pattern of a positive type photoresist film by performing development processing on the positive type photoresist;
(E) forming a line pattern made of the conductor film on the main surface of the wafer by etching the conductor film exposed from the pattern of the positive photoresist film;
The step (c) includes a step of exposing the first transfer region and the second transfer region of the mask so as to overlap one region of the positive photoresist film,
The first transfer region and the second transfer region include a light transmission region as a background,
A plurality of light shielding patterns are disposed in each of the first transfer region and the second transfer region,
Among the plurality of light shielding patterns in the first transfer area and the second transfer area, a phase shifter is arranged at the adjacent position so that the phase of the transmitted light is inverted with respect to the light transmitted through the light transmission area. There are a first light shielding pattern and a second light shielding pattern in which the phase shifter is not disposed,
The shape, size and arrangement of the light-shielding patterns of the first transfer area and the second transfer area are the same,
The method of manufacturing a semiconductor device, wherein the phase shifters of the first transfer region and the second transfer region are arranged so as to be inverted with respect to each other.   19. The method of manufacturing a semiconductor device according to claim 18, wherein, among the line patterns, the first line pattern to which the first light shielding pattern is transferred is a word line of a DRAM, and the second light shielding pattern is transferred to the first line pattern. A method of manufacturing a semiconductor device, wherein the two-line pattern is a gate electrode of a field effect transistor in a peripheral circuit region of the DRAM.

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