JP2001267208A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the dimensional accuracy of a transferred pattern. SOLUTION: A prescribed pattern is transferred onto a semiconductor wafer by performing exposure by using a photomask 2 on which the most proximate light transmitting areas PA1 and PA2 in a pattern for forming a mask pattern are laid out in a direction in which the areas PA1 and PA2 are hardly affected by the aberration of the optical system of an aligner.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique effective when applied to a semiconductor device manufacturing method having a step of transferring an integrated circuit pattern by exposure using a photomask. Things.

[0002]

2. Description of the Related Art Heretofore, a reduction projection exposure method, which is one of optical lithography methods, has been mainly used for forming an extremely fine pattern in a solid-state device such as a large-scale semiconductor integrated circuit. In this method, a mask pattern formed on a photomask or a reticle (hereinafter, collectively referred to as a mask) is reduced and transferred onto a substrate using an imaging optical system.

[0003] The improvement of the resolution in the reduced projection exposure method is as follows.
It has been promoted by increasing the numerical aperture (NA) of the imaging optical system and shortening the wavelength of exposure light. However, since there is a demand for miniaturization of the minimum processing size of the solid-state element more than that, the modified illumination exposure method,
A so-called super-resolution exposure method such as a phase shift mask exposure method has been developed and applied.

As the size of such a transfer pattern becomes finer, various process factors affect the dimensional accuracy of the transfer pattern. Factors affecting the transfer pattern dimensional accuracy include variations in mask pattern dimensions, errors (aberrations) in the imaging optical system, resist film thickness, process variations in development uniformity, and the like.

[0005] Among these factors, the influence of the aberration of the imaging optical system on the transfer pattern has become more evident with the miniaturization of the minimum processing size. In order to evaluate this effect, a technique for measuring the amount of aberration of the imaging optical system of the exposure apparatus has been developed. This method uses the fact that, for example, when a mask pattern having a different pattern pitch is transferred onto a substrate, a position shift occurs in the transfer pattern depending on the amount of aberration. There is a method of obtaining the amount, a method of obtaining the amount from a transfer asymmetry of a side lobe pattern generated when a pattern is transferred using a halftone phase shift mask, and the like. For these,
For example, IEICE, IEICE Technical Report, Technical Report
t of IE'ICE. SDM 99-157 (1999-11) pp9-1
6, Proceedings of the 46th JSAP Lecture Meeting p7
59 etc. The quantification of the aberration amount by these methods has been performed on the exposure apparatus user side, and accordingly, the exposure apparatus maker side has been further reducing the aberration amount. In this way, the transfer pattern accuracy is being improved by reducing the aberration amount.

The light exposure apparatus is described in, for example, “Industrial Research Institute, Ltd., published on November 25, 1998,“ Electronic Materials November Issued Separate Volume 1999, Ultra LSI Manufacturing and Testing Apparatus Guidebook ”, pp. 76-81. Describes the features of the scanning exposure apparatus, aberrations of the exposure apparatus, and the like.

[0007]

However, the present inventor has found that the above exposure technique has the following problems. As described above, in the exposure technique, the amount of aberration of the exposure apparatus is reduced, but it is impossible to reduce the amount of aberration to zero, and some aberration actually remains in the exposure apparatus. On the other hand, application of the above-described super-resolution technology and the like has been promoted in order to cope with miniaturization of the minimum processing size as described above. Transfer, the ratio of the influence on the transferred pattern increases even if the aberration amount is minute, so that the transfer pattern is deformed due to the aberration, thereby deteriorating the resolution characteristics and reducing the process margin. That's the problem.

An object of the present invention is to provide a technique capable of reducing the deformation of a transfer pattern.

It is another object of the present invention to provide a technique capable of improving the resolution characteristics of a transfer pattern.

It is another object of the present invention to provide a technique capable of improving the dimensional accuracy of a transfer pattern.

It is another object of the present invention to provide a technique capable of improving a process margin of a transfer pattern.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0013]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the present invention, a predetermined pattern is transferred onto a semiconductor wafer by an exposure process using a photomask in which a pattern is arranged in a direction in which the optical system of the exposure apparatus is hardly subjected to aberration.

Further, according to the present invention, when exposure light emitted from an exposure light source of a scanning type exposure apparatus is scanned and exposed on a main surface of a semiconductor wafer through a photomask, aberrations of an optical system of the scanning type exposure apparatus are provided. A predetermined pattern is transferred onto the main surface of the semiconductor wafer by using a photomask in which patterns are arranged in a direction that is hard to receive.

According to the present invention, a predetermined pattern is transferred onto the main surface of the semiconductor wafer by irradiating the main surface of the semiconductor wafer with exposure light emitted from an exposure light source of the exposure apparatus via a photomask. The photomask uses a photomask in which a pattern is arranged in a direction that is less susceptible to aberration of the optical system of the exposure apparatus, and the exposure apparatus has the same or similar tendency of the aberration distribution of the optical system. An exposure apparatus selected from the group of exposure apparatuses described above is used.

According to the present invention, a predetermined pattern is transferred onto the main surface of the semiconductor wafer by irradiating the main surface of the semiconductor wafer with exposure light emitted from an exposure light source of the exposure apparatus via a photomask. The photomask, the pattern is arranged in a direction less likely to receive the aberration of the optical system of the exposure apparatus, and, using a photomask having a phase shifter that causes a phase difference in transmitted light, The predetermined pattern is a hole pattern for connecting different layers of the semiconductor wafer.

According to the present invention, a phase shifter is arranged on the photomask.

Further, in the present invention, the predetermined pattern is a hole pattern for connecting different layers of a semiconductor wafer.

In the present invention, the aberration is a coma aberration or a trefoil aberration.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In describing the embodiments of the present invention, the basic meanings of terms in the present application will be described as follows.

1. A semiconductor wafer (semiconductor substrate) is a silicon single crystal substrate (generally a substantially circular plane shape), a sapphire substrate, a glass substrate, other insulating, anti-insulating or semiconductor substrates, etc. used for manufacturing a semiconductor integrated circuit, and a composite substrate thereof. Say In the present application, a semiconductor device is not limited to a device formed on a semiconductor such as a silicon wafer or a sapphire substrate or an insulator substrate, and unless otherwise specified, a TFT (Tin-Film-Trans
This includes those made on other insulating substrates such as glass such as istor) and STN (Super-Twisted-Nematic) liquid crystal.

2. “Light-shielding area”, “light-shielding pattern”,
When the term “light-shielding film” or “light-shielding” is used, it indicates that the region has an optical characteristic of transmitting less than 1% of exposure light applied to the region. Generally, those having a content of 0.1% or less are used. On the other hand, "light transmission area", "light transmission pattern",
When we say "transparent area", "transparent film" or "transparent",
It indicates that it has an optical property of transmitting 60% or more of exposure light applied to the region. Generally, 90% or more is used.

3. "Photoresist pattern" refers to a film pattern obtained by patterning a photosensitive organic film by a photolithography technique. Note that this pattern includes a simple resist film having no opening in the relevant portion.

4. In the field of semiconductors, ultraviolet light is classified as follows. If the wavelength is less than about 400 nm and 350 nm
Ultraviolet light of about 300 nm or more, near ultraviolet light of 350 nm or more, 300
Less than 200 nm and 200 nm or more are defined as far ultraviolet rays, and less than 200 nm are defined as vacuum ultraviolet rays.

[5] A photomask or a mask is a mask structure in which a pattern image is formed on a mask substrate. A pattern that is 1 to 10 times the size of the actual pattern is formed, and a “reticle” used for projection exposure by a scanner or a photo repeater is also included in the photomask. It also includes a phase shift mask. In the present application, a general photomask that has a light-shielding region and a light-transmitting region but does not have a phase shifter (that is, does not cause a phase difference in transmitted light) is referred to as a normal photomask.

6. A phase shift mask (or a phase shift reticle) is a photomask (or a reticle) in which contrast is improved when transferring a pattern by selectively shifting the phase of light using a phase shifter on a substrate on which the pattern is formed. ). Levenson type,
There are a halftone type, a shifter edge type, and the like.

7. The phase shifter refers to a substance or means that generates a phase difference by modulating the wavelength of light in a phase shift mask. Further, the phase difference refers to a phase difference caused by a speed difference of light when the light passes through two substances having different refractive indexes. When the refractive index of air is 1, the thickness (or depth) d of the phase shifter is d = λ / (2 (n
When -1)) is satisfied, a phase difference of 180 degrees can be generated. Here, λ is the wavelength of light, and n is the refractive index at the exposure wavelength of the phase shifter.

8. "Levenson-type phase shift mask"
Is a type of phase shift mask that is also called a spatial frequency modulation type phase shift mask and inverts the phases of adjacent openings separated by a light-shielding region to obtain a clear image by the interference action. .

9. Normal illumination refers to illumination in which the effective illumination light source shape is circular.

10. The modified illumination refers to illumination in which the effective illumination light source shape is other than circular, and includes multi-pole illumination such as annular illumination, quadrupole illumination, and quintuple illumination.

11. The mask pattern is a pattern formed on a photomask for transferring a predetermined pattern, and is generally formed of a light transmitting area and a light shielding area. In a phase shift mask, a phase shifter is arranged in a predetermined light transmission region, and thus the phase shifter is also included in the mask pattern.

12. The arrangement direction of the mask pattern is a direction determined with respect to the aberration of the optical system of the exposure apparatus. Physically, it can be set as the arrangement of the photomask with respect to the optical system, but in general, once the relative arrangement positional relationship between the exposure apparatus and the photomask can be determined, it cannot be easily changed. To change, it is necessary to change the arrangement direction of the mask pattern in the photomask. As a specific example, it can be expressed as an arrangement direction of a plurality of closest patterns.

In the following embodiments, when necessary for the sake of convenience, the description will be made by dividing into a plurality of sections or embodiments, but they are not unrelated to each other, unless otherwise specified. One has a relationship with some or all of the other, such as modified examples, details, and supplementary explanations.

Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, amount, range, etc.), it is particularly limited to a specific number and is clearly limited to a specific number in principle. Except in some cases, the number is not limited to the specific number, and may be more than or less than the specific number.

Furthermore, in the following embodiments, the constituent elements (including element steps, etc.) are not necessarily essential, unless otherwise specified, and when it is deemed essential in principle. Needless to say, there is nothing.

Similarly, in the following embodiments, when referring to the shapes, positional relationships, and the like of the constituent elements, etc., unless otherwise specified, and unless otherwise apparently in principle, it is substantially the same. And those similar or similar to the shape or the like. This is the same for the above numerical values and ranges.

In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

(Embodiment 1) FIG. 1 is a flowchart showing a main part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

First, in the first embodiment, the aberration of the optical system of the exposure apparatus is measured (Step 101). continue,
The design data of the mask pattern of the photomask is designed in consideration of the measurement result of the aberration. Here, based on the measurement result of the aberration, the arrangement direction of the mask pattern is determined so as to be hardly affected by the aberration (Step 102). Thereafter, a mask pattern is formed on the mask substrate of the photomask based on the design data of the mask pattern, and a photomask is manufactured (step 103). Next, a predetermined pattern is transferred to a photoresist film on the semiconductor wafer by an exposure process using the photomask (step 104).
Subsequently, a photoresist pattern is formed on the semiconductor wafer by performing a development process (step 105). Thereafter, using the photoresist pattern as an etching mask, the portion to be processed in the lower layer is processed to form a predetermined pattern on the semiconductor wafer (Step 106).

A specific example of the first embodiment will be described. Hereinafter, in the first embodiment, for example, a 1 G (giga) bit DR having a minimum design dimension of about 130 nm is used.
In the manufacturing method of AM (Dynamic Random Access Memory),
The case where the technical idea of the present invention is applied will be described as an example.
In the following description, a case will be described in which, for example, a contact hole pattern having a minimum arrangement pitch of 130 nm and a minimum design dimension of 180 nm is transferred on a semiconductor wafer among the contact hole patterns of the DRAM.

First, an example of the exposure apparatus used in the first embodiment will be described with reference to FIGS. The exposure apparatus 1 is, for example, a scanning reduction projection exposure apparatus (hereinafter, also referred to as a scanner) having a reduction ratio of 4: 1. The exposure conditions of the exposure apparatus 1 are, for example, as follows. That is, for example, a KrF excimer laser beam having an exposure wavelength of 248 nm is used as the exposure light, the numerical aperture NA of the projection lens is 0.68, and coherency (σ) is used.
Value = 0.3. As the photomask 2, for example, a Levenson-type phase shift mask was used.

The light emitted from the exposure light source 1a includes a fly-eye lens 1b, an aperture 1c, and a condenser lens 1d.
The photomask 2 is illuminated via 1, 1d2 and a mirror 1e. Among optical conditions, coherency is aperture 1
Adjustment was made by changing the size of the opening f.
A pellicle 2p is provided on the photomask 2 for preventing pattern transfer failure or the like due to adhesion of foreign matter. The mask pattern drawn on the photomask 2 is projected onto a semiconductor wafer 3 as a sample substrate via a projection lens 1g. The photomask 2 is a mask position control means 1
h and mask stage 1i controlled by mirror 1i1
2 and the center thereof is precisely aligned with the optical axis of the projection lens 1g.

The semiconductor wafer 3 is vacuum-adsorbed on the sample table 1j. The sample stage 1j is mounted on a Z stage 1k movable in the optical axis direction of the projection lens 1g, that is, in the Z direction, and further mounted on an XY stage 1m.
Z stage 1k and XY stage 1m are main control system 1n
Drive means 1p, 1q in response to a control command from
, And can be moved to a desired exposure position. Its position is mirror 1 fixed to Z stage 1k
The position of r is accurately monitored by the laser length measuring device 1s. In addition, the surface position of the semiconductor wafer 3 is measured by a focus position detecting means included in a normal exposure apparatus. By driving the Z stage 1k according to the measurement result, the surface of the semiconductor wafer 3 can always be made to coincide with the imaging plane of the projection lens 1g.

The photomask 2 and the semiconductor wafer 3 are driven synchronously according to the reduction ratio, and the mask pattern is reduced and transferred onto the semiconductor wafer 3 while the exposure light irradiation area scans over the photomask 2. At this time, the surface position of the semiconductor wafer 3 is also dynamically driven and controlled with respect to the scanning of the semiconductor wafer by the above-described means. When the circuit pattern formed on the semiconductor wafer 3 is overlaid with the circuit pattern formed on the photomask 2 for exposure, the position of the mark pattern formed on the semiconductor wafer 3 is detected using the alignment detection optical system 1t. From the detection result, the semiconductor wafer 3
Is positioned and transferred by superposition. The main control system 1n is electrically connected to the network apparatus 1u, and enables remote monitoring of the state of the exposure apparatus 1 and the like.

FIGS. 3 and 4 are schematic diagrams showing the exposure areas of the exposure apparatus (scanner) 1 and the stepper in comparison. In the case of the above-described exposure apparatus 1, a planar rectangular slit area S inscribed in the exposure-possible area PP of the optical system of the exposure apparatus 1 is arranged. The slit area S scans the photomask 2 in the Y direction to transfer an exposure shot.
Therefore, the aberration amount distribution is basically distributed only in the slit direction. In the case of the stepper of FIG. 4, the exposure shot PS having a square planar shape is arranged so as to be inscribed in the exposure area PP of the optical system, so that the aberration amount distribution is two-dimensional.

FIG. 5 is a view schematically showing an exposure operation of the exposure apparatus 1. As shown in FIG. Since the photomask 2 and the semiconductor wafer 3 have a mirror-symmetrical relationship, the scanning direction of the photomask 2 and the
Is opposite to the scanning direction. When the driving distance is 4: 1, the moving amount of the semiconductor wafer 3 is 1 with respect to the moving amount 4 of the photomask 2. At this time, the exposure light P is applied to the photomask 2 through the slit region S.
Is irradiated on the semiconductor wafer 3 via an image forming optical system (projection lens 1g), and thereby the transfer area 2A of the photomask 2 is irradiated. Is transferred to each of the plurality of chip forming areas CA of the semiconductor wafer 3.

Next, the photomask 2 will be described. FIG. 6 shows a pattern layout example of the photomask 2. The light-shielding area DA is hatched to make the drawing easier to see. The light shielding area DA is formed of, for example, chromium, chromium oxide, or a laminated film of these. In this light-shielding film, for example, an opening in a plane square shape is formed, and the mask substrate is partially exposed, thereby forming the light transmission areas PA (PA1 to PA3). On the photomask 2, a plurality of light transmission areas PA (P
A1 to PA3) are regularly arranged. Of these, the light transmission areas PA1 to PA3 are arranged close to each other. Here, for example, since the minimum pattern arrangement pitch in the X and Y directions is 260 nm, which is twice the minimum design dimension, the center-to-center distance between the light transmitting areas PA1 and PA2 is, for example, 260 nm. The center distance between the light transmitting areas PA1 and PA3 and the center distance between the light transmitting areas PA1 and PA3 are, for example, about 368 nm. In order to transfer a pattern with such a fine arrangement pitch onto the semiconductor wafer 3 with practical resolution characteristics, it is necessary to provide a Levenson-type phase shift mask portion in the mask pattern. In the Levenson-type phase shift mask, a 180-degree phase difference is introduced into the exposure light on the photomask 2 in order to introduce a 180-degree phase difference (that is, mutually inverted) into the exposure light that has passed through the adjacent mask pattern. A phase shifter pattern is provided. Specifically, for example, as schematically shown in FIG. 7, in the mask substrate 2 a constituting the photomask 2, one of the light transmitting regions PA adjacent to each other is provided with both light transmitting regions PA.
The phase shifter 2b1 is provided so that the phase difference of the light transmitted through is 180 degrees. Here, the case where the phase shifter 2b1 is a groove dug in the mask substrate 2 is illustrated.
The depth of the groove forming the phase shifter 2b1 satisfies the above equation d (that is, a phase difference of 180 degrees is generated). Note that the width of the phase shifter 2b1 is wider than the width of the light transmission area PA opened in the light shielding film 2c.
In the arrangement region of the phase shifter 2b1, the eaves of the light-shielding film 2c are formed. This makes it possible to suppress the deterioration of pattern transfer accuracy due to the light waveguide phenomenon. Further, the phase shifter is not limited to the groove type, and can be changed. For example, as shown in FIG. 8, a transparent film (SOG (Spin On Glass))
The phase shifter 2b2 made of a film or the like may be arranged in any one of the light transmission areas PA adjacent to each other.

By the way, in the case of the photomask 2 shown in FIG. 6, since the three light transmitting areas PA1 to PA3 are close to each other at a distance where the arrangement of the phase shifter 2b is required, all the light transmitting areas PA1 The phase difference cannot be set to 180 degrees between -PA3. That is, the photomask 2 of FIG. 6 cannot use a Levenson-type phase shift mask. Therefore, in the present embodiment, as shown in FIGS. 9 and 10, in order to transfer such a pattern, a Levenson-type phase shift mask can be applied, as shown in FIGS.
The mask pattern of the photomask 2 shown in (1) is divided into two types of patterns and separately superimposed and transferred. 9A and 10A are plan views of the photomask 2, and FIGS. 9B to 9D are AA in FIG. 9A.
It is sectional drawing of the line, BB line, and CC line. In addition, different hatchings are added to the light-shielding area DA and the arrangement area of the phase shifter 2b1 to make the drawing easier to see.

In the photomask 2 shown in FIG.
The phase shifter 2b1 is arranged in the light transmission area PA2 such that the phase difference between the transmitted lights of the adjacent light transmission areas PA1 and PA2 is 180 degrees. The light transmission area PA3 indicated by a broken line in the photomask 2 in FIG. 9 indicates the position of the light transmission area PA3 in the photomask 2 in FIG. 10 and is actually formed on the photomask 2 in FIG. It is not something.
The phase shifter 2b1 is, for example, a groove type, but is not limited thereto, and may be provided with the above-mentioned transparent film or translucent film.

In the photomask 2 shown in FIG. 10, the light transmitting area PA3 shown in FIG. 6 and the auxiliary light transmitting area PAs are arranged around the light transmitting area PA3. This auxiliary light transmission area PAs
Is formed in such a small size that it contributes to generate a phase difference of 180 degrees in the exposure light with the light transmission area PA3, but is not transferred as a pattern to the photoresist film on the semiconductor wafer. In the photomask 2 of FIG. 10, the phase shifter 2b1 is disposed closer to the light transmission area PA3 in consideration of the phase shifter workability in a fine pattern, and the light transmitted therethrough and the light transmitted through the auxiliary light transmission area PAs are transmitted. The phase difference with respect to the applied light was set to 180 degrees. Light transmission area PA3
The mask pattern dimension was 200 nm square in terms of dimensions on a transfer substrate (semiconductor wafer), and the dimension of the auxiliary light transmission area PAs was 90 nm square in terms of dimensions on a transfer substrate (semiconductor wafer).

Incidentally, as described above, the image forming optical system of the exposure apparatus has an aberration which is an error thereof. When a mask pattern of a photomask is transferred onto a semiconductor wafer via an image forming optical system of an exposure apparatus, for example, deterioration of a transfer pattern shape,
An effect such as a transfer position shift occurs. The aberration of the image forming optical system of the exposure apparatus is distributed in the exposure field. This aberration amount can be represented by, for example, a Zernike aberration function, and the magnitude of each aberration component corresponds to the coefficient of each term. It is known that, among various aberrations, for example, third-order coma aberration and Trefoil aberration cause deterioration of the shape of the transfer pattern and position shift. In particular, the influence of these aberrations depends on the dimensions of the transfer pattern,
It has been found from the results of our experiments that it varies depending on the shape and arrangement. This aberration is distributed with a direction and a magnitude in the exposure field. For this reason,
The size of the influence on the transfer pattern characteristics changes depending on the arrangement of the transfer pattern in the exposure shot. Here, in the case of the above scanner, the lens aberration is basically distributed only in the extending direction (X direction) of the slit region, and the lens aberration is distributed in the scanning direction (Y direction).
Direction) are basically the same value.

FIGS. 11 and 12 show the results of measuring the amount of aberration in an exposure shot in the scanner 1 used in the present embodiment. Such a distribution can be obtained by an aberration measurement method using the above-described halftone phase shift mask (a method obtained from a transfer asymmetry of a side lobe pattern generated when a pattern is transferred using a halftone phase shift mask). it can. FIG. 11 shows the 0 ° component of Trefoil, and FIG. 12 shows the measurement results of the 45 ° component of Trefoil. In this scanner 1, 0 of Trefoil
The 45 ° component of Trefoil is about 0.04λ, which is larger than the 90 ° component of Trefoil, while the ° component is about ± 0.02λ or less.

Next, the relationship between the aberration of such an exposure apparatus and the arrangement direction of the mask pattern in the photomask will be described.

FIGS. 13 and 14 show the photomask 2 shown in FIG. 9 and the photomask 2 obtained by rotating the photomask 2 by 90 degrees. That is, FIG. 13 and FIG.
4, the arrangement direction of the photomask pattern is different by 90 degrees. In the present embodiment, the aberration of the exposure apparatus was measured in each pattern arrangement. The Y direction coincides with the scanning direction of the exposure device.

FIGS. 15 and 16 show projected optical images when the mask pattern of the photomask 2 shown in FIGS. 13 and 14, respectively, is projected onto a semiconductor wafer via the imaging optical system of the exposure apparatus. FIG. The figure shows only the case of in-focus. The numbers in the figure represent the light intensity values (low units) of each contour line. 15 and 16
(A) is a plan view of the photomask 2 measured, and (b) of each drawing is a measurement result of (a) of each drawing. The measurement target is the closest pattern (light transmission area PA1, PA2) surrounded by a frame in FIGS. 15 and 16A.

The leftmost part of FIG.
The uppermost part of (b) shows the ideal case where there is no aberration,
The second from the left in FIG. 15B and the second from the top in FIG. 16B are the third from the left in FIG. 15B and FIG. 16B when the third-order frame is 0.05λ in the X direction. (B) Third from the top, if the third-order frame is 0.05λ in the Y direction,
The fourth from the left of FIG. 15B and the fourth from the top of FIG. 16B have a Trefoil aberration (0 °) of 0.05λ.
In some cases, the fourth from the left in FIG.
The fourth from the top of 6 (b) is a projection optical image (light intensity distribution) when the Trefoil aberration (45 °) is 0.05λ.
FIG.

As shown in FIG. 15, the light transmitting areas PA1, PA1,
When the PA2 (hole pattern on the semiconductor wafer: specifically, a contact hole or a through hole) is arranged in the Y direction (vertical direction in FIGS. 13 and 15A), the transfer pattern deformation due to the coma causes Also Trefoil (Tref
Oil) It can be seen that the transfer pattern deformation due to aberration is larger. In particular, in the case of Trefoil 45 °, the difference between the upper and lower light intensities is large (the symmetry is low), and it is expected that a large difference will occur in the transfer pattern dimensions.

Further, as shown in FIG.
When A1 and PA2 (hole patterns on a semiconductor wafer) are arranged side by side in the X direction (horizontal direction in FIGS. 14 and 16A), similarly to the Y direction arrangement, Trefoil (Trefoil) rather than a coma is used. It can be seen that the influence of aberration is greater and, unlike the above arrangement in the Y direction, the difference in light intensity distribution is greater for Trefoil 0 ° with rotation of the pattern arrangement.

According to the study by the inventor, in an exposure apparatus using the latest KrF excimer laser beam as an exposure light source, the value of the frame is 0.05.
Since it has become smaller than λ, the change in the light intensity distribution due to the coma is smaller than that shown in the figure. On the other hand, regarding the Trefoil aberration, even if the aberration amount is the same, the influence on the transfer pattern is large,
Since the value is about 05λ, it is conceivable that a transfer pattern dimensional difference may occur due to the light intensity distribution difference shown in the figure.

As described above, in the case of the scanner used in the first embodiment, the value of the refoil (Trefoil) 45 ° is larger than that of the trefoil (Trefoil) 0 °.
Also, as shown in FIG. 16A, it is understood that the influence of trefoil aberration can be reduced by arranging the light transmission areas PA1 and PA2 (hole patterns on the semiconductor wafer) side by side in the X direction. .

In the first embodiment, since the chip size of the semiconductor chip is such that a mask pattern for two semiconductor chips can be arranged on one photomask, two semiconductor chips are provided on the photomask. The mask patterns for the chips were arranged side by side. At this time, the arrangement of the semiconductor chips on the photomask with respect to the mask pattern layout of FIG. 13 is such that two chip transfer regions CP are formed on the photomask 2 around the light shielding film 2c as schematically shown in FIG.
Are arranged side by side in the Y direction. On the other hand, the semiconductor chip arrangement with respect to the mask pattern layout of FIG. 14 is such that, as schematically shown in FIG. 18, two chip transfer areas CP are surrounded on the photomask 2 by a light shielding film 2c. , X in the X direction.

As described above, in the present embodiment, since the mask pattern is arranged as shown in FIG. 14, the shot arrangement is arranged as shown in FIG. The arrangement of the semiconductor chips on the semiconductor wafer at this time is schematically shown in FIG. The notch 3a of the semiconductor wafer 3 is set to the lower side of FIG.
Are arranged regularly so that the long sides thereof are along the Y direction (vertical direction in FIG. 19).

In contrast to the above, Trefoil (Trefoi
l) When Trefoil 0 ° is larger than 45 °, the pattern arrangement may be rotated 90 °. At this time, the semiconductor chips 3C already transferred onto the semiconductor wafer 3 are
In the case of the arrangement as shown in FIG. 19, as schematically shown in FIG. 20, the relationship between the projection optical system of the exposure apparatus and the pattern arrangement is rotated by 90 degrees with respect to the above case, and the exposure is performed simultaneously. The direction of the semiconductor wafer 3 at the time of processing may be rotated by 90 degrees, placed on an exposure apparatus, and exposed.

It is preferable to select an optimum combination of the arrangement of the semiconductor chips and the pattern direction according to the aberration of the projection optical system of the exposure apparatus.

In the above-described method, the aberration amount distribution in the exposure shot may be considered, or the aberration amount distribution corresponding to the arrangement position in the exposure shot where the pattern susceptible to aberration is arranged. Should be considered. For example, in the example shown in FIG. 21, only in the area 2A1 within the transfer area 2A of the photomask 2, a mask pattern (for example, as shown in FIG. The minimum arrangement pitch is 26
A pattern for forming a 0 nm pattern is arranged, and a mask pattern (for example, on a semiconductor wafer) in which the influence on the transfer pattern due to the aberration is within an allowable range in the process is provided in the other area 2A2. , The minimum dimension is, for example, 200 nm or more, the arrangement pitch is, for example, 400
(pattern for forming a pattern of nm or more). At this time, the aberration amount distribution in the exposure field of the exposure apparatus corresponding to the area 2A1 is Trefoil 0 °.
Has a maximum value of about 0.02λ, and the maximum value of Trefoil 45 ° is about 0.05λ, the latter being a larger value.
On the other hand, in the other area 2A2, on the contrary, Trefoi (Trefoi
l) There was a region where the value of 0 ° was larger than that of 45 ° of Trefoil, but no transfer pattern abnormality that would cause a problem in the wafer process occurred.

Next, a manufacturing process of the DRAM of the present embodiment will be described. FIG. 22 is a sectional view of a principal part of a DRAM, and FIG. 23 is a plan view of a principal part of a memory cell of the DRAM.

At this stage, the semiconductor substrate 3S is a part of the semiconductor wafer 3 having a substantially circular shape in a plane, and is made of, for example, a p-type silicon single crystal. FIG. 22 shows a DRAM.
2 is a cross-sectional view showing a step in which an insulating film is laminated after forming the information storage capacitor element.

First, an embedded element isolation region 4 is formed on the main surface of the semiconductor substrate 3S by using a known element isolation technique. The element isolation region 4 is formed by embedding an insulating film such as silicon oxide in a trench dug in the semiconductor substrate 3S (trench isolation). The planar rectangular island-shaped region surrounded by the element isolation region 4 is the active region L. In the present embodiment, active regions L are laid out obliquely as shown in FIG.

Subsequently, after a well region such as a p-well 5 is formed on the semiconductor substrate 3S, a gate insulating film 6 made of, for example, silicon oxide is formed on the active region L on the main surface of the semiconductor substrate 3S. . Then, on the semiconductor substrate 3S,
For example, a word line WL having a structure in which polycrystalline silicon having a thickness of 150 nm and silicon oxide having a thickness of 200 nm are stacked is formed. The word lines WL are formed in a band-like pattern extending in the horizontal direction in FIG. The portion of the word line WL that overlaps the active region L in plan is the memory cell selection MIS
FET (Metal Insulator Semiconductor Field Effect
Transistor) Qs gate electrode 7. The structure of the word line WL (gate electrode 7) is not limited to this, and can be variously changed. For example, a low-resistance polycrystalline silicon film doped with an n-type impurity such as P (phosphorus), and the like. A polymetal structure composed of a barrier metal layer formed of a WN (tungsten nitride) film or the like formed thereon and a refractory metal film such as a W (tungsten) film formed thereon may be used. The above polycide structure in which a silicide film such as tungsten silicide or the like is stacked on a crystalline silicon film may be used.

Next, the memory cell selecting MIS • FET
After forming the n-type semiconductor region 8 for Qs source / drain, the surface of the word line WL is covered with an insulating film 9 made of, for example, silicon nitride or the like. Subsequently, an SOG (Spin On Glass) film 10a and an insulating film 10b made of silicon oxide or the like are deposited on the main surface of the semiconductor substrate 3S. The upper surface of the insulating film 10b is, for example, a CMP (Chemic
al Mechanical Polish) method. Thereafter, contact holes (hole patterns) 11a and 11b are formed in the SOG film 10a and the insulating film 10b so that the semiconductor region 8 is exposed, and then a plug 12 is formed therein. In the first embodiment, during the exposure processing for forming the contact holes 11a and 11b,
In consideration of the arrangement direction of the mask pattern in the photomask 2, the multiple exposure process using the two photomasks in FIGS. 9 and 10 was applied. Thereby, the contact holes 11a and 11b having fine dimensions and adjacent pitches can be formed satisfactorily with high dimensional accuracy. Plug 12
Is formed, for example, by depositing a low-resistance polycrystalline silicon film on the insulating film 10b by a CVD method or the like, and then polishing the deposited film by a CMP method so as to remain only in the contact holes 11a and 11b.

Next, an insulating film 10c made of, for example, silicon oxide is deposited on the insulating film 10b by a CVD method or the like, and a wiring groove is formed in the insulating film 10c. Subsequently, a conductive film such as tungsten is deposited on the semiconductor substrate 3S by a sputtering method, a CVD method, or the like.
This is polished by a CMP method or the like so as to be left only in the above-mentioned wiring groove, so that the bit line B
L is formed. The bit line BL is formed in a belt-like pattern extending obliquely upward and downward in FIG. 23 (extending so as to be oblique to the extending direction of the word line WL). It is arranged so that it may overlap. That is, the bit line BL is electrically connected to the semiconductor region 8 through the plug 12 in the contact hole 11a. The bit line BL may be formed of, for example, low-resistance polycrystalline silicon, high-melting-point metal silicide, or a laminated film of these.

Subsequently, an insulating film 10d made of, for example, silicon oxide is deposited on the semiconductor substrate 3S by a CVD method or the like, and an insulating film 13 made of, for example, silicon nitride is deposited on the semiconductor substrate 3S by a CVD method or the like. . After that, contact holes (hole patterns) 14 are formed in the insulating films 13, 10d, and 10c so that the plugs 12 are exposed.
Then, after forming a plug 15 in the contact hole 14, a capacitor 16 which is a capacitance element for storing information is formed. The capacitor 16 includes a lower electrode (storage electrode) 16a
And an upper electrode (plate electrode) 16b and a capacitive insulating film (dielectric film) 16c made of a tantalum pentoxide film (Ta ₂ O ₅ ) or the like provided therebetween. Lower electrode 16
a is made of, for example, a low-resistance polycrystalline silicon film doped with P (phosphorus), and the upper electrode 16b is made of, for example, a low-resistance polycrystalline silicon, a titanium nitride (TiN) film, a refractory metal,
Refractory metal silicide, aluminum or copper. The lower electrode 16a is connected to the memory cell selecting MIS • FET Q through the plug 15 in the contact hole 14.
s is electrically connected to the other of the source and the drain (semiconductor region 8). Thereby, the capacitor 16 is connected in series with the memory cell selecting MIS • FET Qs. In addition to the tantalum pentoxide film, for example, BST (Ba _x Sr _1-x ) Ti
O _3), it is also possible to use a ferroelectric film such as _{PZT (Pb (Zr y Ti 1} -y) O 3). After that, insulating films 17 and 18 made of, for example, silicon oxide are formed in order from the bottom by CVD.
It is deposited by a method or the like. Here, only typical manufacturing steps have been described, but other than this, a normal element manufacturing step was used.

According to the first embodiment, the following effects can be obtained. (1). Deformation or the like of the pattern transferred onto the semiconductor wafer 3 can be suppressed or prevented. (2). The resolution of the pattern transferred onto the semiconductor wafer 3 can be improved. (3) According to the above (1) and (2), the dimensional accuracy of the pattern can be improved. (4) According to the above (1) to (3), the arrangement accuracy of the pattern can be improved. (5) According to the above (1) to (4), the performance of the semiconductor integrated circuit device can be improved. (6) According to the above (1) to (4), the process margin of the pattern can be improved. (7) According to the above (1) to (4) and (6), the integration degree of the DRAM can be improved. (8) According to the above (1) to (4) and (6), it is possible to promote downsizing of the DRAM. (9) According to the above (1) to (4) and (6), the reliability of the DRAM can be improved. (10) According to the above (1) to (4) and (6), the yield of the DRAM can be improved. (11) According to the above (10), the manufacturing cost of the DRAM can be reduced.

(Embodiment 2) FIG. 18 is a plan view of a main part of a memory cell of a DRAM according to another embodiment of the present invention.

Here, a case where bit line BL is arranged to cross perpendicularly to word line WL is shown. Here, the mask pattern arrangement of the photomask 2 shown in FIG. 14 was used in the exposure processing for forming the contact holes 14. Other than this, the description is omitted because it is the same as the first embodiment.

(Embodiment 3) When the same mask pattern is transferred onto a semiconductor wafer by using an exposure apparatus, if the pattern of aberrations of the exposure apparatus is similar, for example, a pattern of the same product is exposed to a plurality of exposure patterns. When starting construction with equipment,
There is an advantage that the layout of the mask pattern and the shot arrangement on the semiconductor wafer need not be changed depending on the exposure apparatus.

Here, for example, in the case of a scanner, if the distribution of the magnitude relationship between 0 ° and 45 ° with respect to the slit direction is the same,
By applying the mask pattern arrangement as described above, it is possible to improve throughput and productivity while suppressing deterioration of transfer pattern accuracy.

Therefore, if this is further expanded,
In a specific production line in a certain factory, by configuring the exposure apparatus group having the same (similar or similar) tendency of the aberration, that is, selecting the exposure apparatus group having the similar aberration tendency in advance. By doing so, it is not necessary to limit the exposure apparatus when exposing a predetermined mask pattern. Therefore, according to the third embodiment, in addition to the effects obtained in the first and second embodiments, it is possible to improve the throughput and productivity in manufacturing the semiconductor integrated circuit device.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. Needless to say,

For example, the exposure conditions of the exposure apparatuses of the first to third embodiments are not limited to those described above, and can be variously changed. For example, as the exposure light, for example, an exposure wavelength of 1
A 93 nm ArF excimer laser may be used. Further, the reduction ratio of the optical lens may be, for example, 5: 1.

In the first to third embodiments, the case where the scanner is mainly used has been described as an example. However, even in the case of the stepper, the aberration amount distribution in the exposure shot is as described above.
For example, Trefoil 0 °
(efoil) If 45 ° is distributed with a larger value, the same pattern arrangement method can be applied.

In the above description, the invention made mainly by the inventor has been described in terms of the DRA which is the application field in which the invention is based.
M has been described, but the present invention is not limited to this. For example, SRAM (Static Random Acce
ss Memory) or flash memory (EEPROM; E)
Semiconductor device having a memory circuit such as an electric erasable programmable read only memory (RAM), a semiconductor device having a logic circuit such as a microprocessor, or a hybrid semiconductor device in which the memory circuit and the logic circuit are provided on the same semiconductor substrate. Applicable to devices. Further, the present invention can be applied to the formation of a pattern on a liquid crystal substrate or a magnetic head.

[0084]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows. (1) According to the present invention, the deformation of a transfer pattern caused by the aberration of the optical system is reduced by using a photomask in which patterns are arranged in a direction that is less likely to receive the aberration of the optical system of the exposure apparatus during the exposure processing. It becomes possible. (2) According to the above (1), the resolution characteristics of the transfer pattern can be improved. (3) According to the above (1) and (2), the dimensional accuracy of the transfer pattern can be improved. (4) According to the above (1) to (3), the process margin of the transfer pattern can be improved. (5) According to the above (1) and (2), the performance of the semiconductor device can be improved. (6) According to the above (1) to (4), the yield of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a flowchart showing a main part of a manufacturing process of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of a configuration of an exposure apparatus used in a manufacturing process of the semiconductor device of FIG.

FIG. 3 is an explanatory diagram of an exposure area of a scanner.

FIG. 4 is an explanatory diagram of an exposure area of a stepper.

FIG. 5 is an explanatory diagram for explaining an operation of the exposure apparatus of FIG. 2;

FIG. 6 is a plan view of a principal part showing an example of a layout of a mask pattern of a photomask used in a manufacturing process of the semiconductor device of FIG. 1;

7 is a fragmentary cross-sectional view of an example of a phase shift mask used in the manufacturing process of the semiconductor device of FIG. 1;

8 is a cross-sectional view of a main part of an example of another phase shift mask used in the manufacturing process of the semiconductor device of FIG. 1;

9A is a plan view of a main part of a photomask used in the manufacturing process of the semiconductor device of FIG. 1, and FIGS. 9B to 9D are AA line, BB line, and C line of FIG. 9A, respectively. It is sectional drawing of the -C line.

10A is a photomask used in the manufacturing process of the semiconductor device shown in FIG. 1; FIG. 10B is a plan view of a main part of the photomask paired with the photomask shown in FIG. 9; It is sectional drawing of the AA line, the BB line, and the CC line of (a).

11 is an explanatory diagram of a measurement result of an aberration amount distribution in an exposure shot in the optical system of the exposure apparatus in FIG. 2;

12 is an explanatory diagram of a measurement result of an aberration amount distribution in an exposure shot in the optical system of the exposure apparatus in FIG. 2;

13 is an explanatory diagram of an example of a mask pattern arrangement in a photomask used in the manufacturing process of the semiconductor device of FIG. 1;

14 is an explanatory diagram showing an example of the arrangement of mask patterns in a photomask used in the manufacturing process of the semiconductor device of FIG. 1, which is different from the example of FIG.

15A is an explanatory diagram of a mask pattern arrangement of the photomask of FIG. 13; FIG. 15B is an explanatory diagram of a calculation result of a projection optical image distribution on a semiconductor wafer when the photomask of FIG. 13A is used; It is.

16A is an explanatory diagram of a mask pattern arrangement of the photomask of FIG. 14; FIG. 16B is an explanatory diagram of a calculation result of a projection optical image distribution on a semiconductor wafer when the photomask of FIG. 14A is used; It is.

FIG. 17 is an explanatory diagram schematically showing an example of a chip transfer area on a photomask for obtaining the mask pattern arrangement of FIG. 13;

FIG. 18 is an explanatory diagram schematically showing an example of a chip transfer region on a photomask for obtaining the mask pattern arrangement of FIG. 14;

FIG. 19 is an explanatory diagram schematically showing an exposure shot arrangement on a semiconductor wafer.

FIG. 20 is an explanatory diagram schematically showing an exposure shot arrangement on a semiconductor wafer.

FIG. 21 is an explanatory diagram of a layout example of a mask pattern in a photomask according to another embodiment of the present invention.

FIG. 22 is a fragmentary cross-sectional view of an example of a semiconductor device manufactured by applying the present invention.

FIG. 23 is a plan view of relevant parts of an example of a semiconductor device manufactured by applying the present invention.

FIG. 24 is a plan view of relevant parts of an example of another semiconductor device manufactured by applying the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Exposure apparatus 1a Exposure light source 1b Fly-eye lens 1c Aperture 1d1, 1d2 Condenser lens 1e Mirror 1f Aperture 1g Projection lens 1h Mask position control means 1i1 Mirror 1i2 Mask stage 1j Sample stage 1k Z stage 1m XY stage 1n Main control system Driving means 1r mirror 1s laser length measuring device 1t alignment detecting optical system 1u network device 2 photomask 2p pellicle 2A transfer region 2A1, 2A2 region 2a mask substrate 2b1 phase shifter 2b2 phase shifter 2c light shielding film 3 semiconductor wafer 3a notch 3C semiconductor chip 3S Semiconductor substrate 4 element isolation region 5 p well 6 gate insulating film 7 gate electrode 8 semiconductor region 9 insulating film 10a SOG film 10b-10d insulating film 11a, 11b contact Hole (hole pattern) 12 Plug 13 Insulating film 14 Contact hole (Hole pattern) 15 Plug 16 Capacitor 16a Lower electrode 16b Upper electrode 16c Capacitive insulating film 17, 18 Insulating film PP Exposing area S Slit area CA Chip forming area DA Light shielding area PA (PA1 to PA3) Light transmission area PAs Auxiliary light transmission area CP Chip transfer area L Active area WL Word line Qs MIS / FET for memory cell selection

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Nobuo Hasegawa 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Device Development Center, Hitachi, Ltd. (Reference) 2H095 BA02 BB02 BB31 5F046 AA20 AA25 BA04 BA05 BA04 CA04 CB05 CB17 CB23 DA13

Claims (5)

[Claims] A step of transferring a predetermined pattern onto the main surface of the semiconductor wafer by irradiating the main surface of the semiconductor wafer with exposure light emitted from an exposure light source of the exposure apparatus via a photomask. A method of manufacturing a semiconductor device, wherein the pattern of the photomask is arranged in a direction that is less susceptible to aberration of an optical system of the exposure apparatus. 2. A predetermined pattern is transferred onto a main surface of a semiconductor wafer by scanning exposure light emitted from an exposure light source of a scanning type exposure apparatus onto a main surface of the semiconductor wafer via a photomask. In this case, a method of manufacturing a semiconductor device, wherein the photomask uses a photomask in which a pattern is arranged in a direction less likely to receive aberration of an optical system of the scanning exposure apparatus. 3. A step of transferring a predetermined pattern onto the main surface of the semiconductor wafer by irradiating the main surface of the semiconductor wafer with exposure light emitted from an exposure light source of the exposure apparatus via a photomask. The photomask uses a photomask in which a pattern is arranged in a direction less likely to receive the aberration of the optical system of the exposure apparatus. The exposure apparatus is a group of exposure apparatuses in which the tendency of the aberration distribution of the optical system is the same or similar. A method for manufacturing a semiconductor device, comprising using an exposure apparatus selected from the group consisting of: 4. A step of transferring a predetermined pattern onto the main surface of the semiconductor wafer by irradiating the main surface of the semiconductor wafer with exposure light emitted from an exposure light source of the exposure apparatus via a photomask. A semiconductor, wherein the photomask uses a photomask in which a pattern is arranged in a direction that is hardly subjected to aberration of an optical system of the exposure apparatus, and a phase shifter that causes a phase difference in transmitted light is arranged. Device manufacturing method. 5. A step of transferring a predetermined pattern onto the main surface of the semiconductor wafer by irradiating the main surface of the semiconductor wafer with exposure light emitted from an exposure light source of the exposure apparatus via a photomask. When manufacturing the photomask, measuring the aberration of the optical system of the exposure apparatus, based on the measurement result, of the pattern on the photomask, determining the arrangement direction of the closest pattern, A method of manufacturing a semiconductor device, comprising: laying out a pattern in consideration of the arrangement direction of a closest pattern; and forming a pattern on a mask substrate according to the layout.