JP2010145594A - Method for driving simple matrix homeotropic alignment mode liquid crystal panel, and simple matrix homeotropic alignment type liquid crystal display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that a dynamic alignment instability (DMA) phenomenon viewed as a black low transmittance area (shadow-like area) in a homeotropic alignment type liquid crystal layer of white dots when a voltage is applied can not be suppressed. <P>SOLUTION: One line (n=1), two lines (n=2), three lines (n=3) fifth lines (n=5) or ten lines (n=10) of a common electrode is set to an OFF signal line (black signal line) to suppress the occurrence of the DMA phenomenon. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a driving method of a simple matrix vertical alignment type liquid crystal display panel and a simple matrix vertical alignment type liquid crystal display device.

  In general, in a simple matrix vertical alignment type liquid crystal display panel, the liquid crystal molecules are aligned vertically with respect to the substrate when no voltage is applied, so that black display is very good, and the vertical alignment type between two polarizing plates. By inserting an optical compensator having negative optical anisotropy into one or both of the liquid crystal layers, the viewing angle characteristics are very good (see Patent Document 1).

  In addition, in the vertical alignment type liquid crystal layer, multi-domain by processing such as mono-domain alignment by applying rubbing alignment, ultraviolet alignment, etc. to the alignment layer, or providing slits on the electrodes, providing protrusions on the substrate, etc. Orientation has been proposed. In particular, the monodomain alignment treatment can be controlled so that the alignment state in the vertical alignment type liquid crystal layer is uniform irrespective of the presence or absence of voltage application.

  Furthermore, in order to prevent alignment defects when a voltage is applied to the vertical alignment type liquid crystal layer, a pretilt angle is given, and even when no voltage is applied, the liquid crystal molecules of the vertical alignment type liquid crystal layer are slightly slightly perpendicular to the substrate. Inclined.

There is a multiplex driving method as a driving method of a simple matrix vertical alignment type liquid crystal display panel which does not use a thin film transistor (TFT). The optimum bias method is used as a general multiplex drive method, and the drive waveform is an in-frame inversion drive or 1-line inversion drive waveform (hereinafter referred to as A waveform), a frame inversion drive waveform (hereinafter referred to as B waveform). And N line inversion drive waveform (hereinafter referred to as C waveform). Currently, the B waveform with the lowest power consumption is widely used.
JP 2005-234254 A

  However, in the conventional simple matrix vertical alignment type liquid crystal display panel described above, the liquid crystal azimuth angle is deviated from the set direction due to some external factor because the regulation force of the liquid crystal azimuth angle is weaker than that of the horizontal alignment type such as the TN mode. As a result, the retardation partially changes, and as a result, a black low transmittance region may be visually recognized as a “shadow” region in the vertical alignment type liquid crystal layer of white pixels (dots) when a voltage is applied. . In addition, the shaded area of black dots may be visually recognized not only as the front (normal direction) of the liquid crystal display panel but also as a “roughened” area when the viewing angle is swung. Furthermore, the shaded area of black dots has continuity and may reach the adjacent dots and be visually recognized as an “uneven” area. The phenomenon visually recognized as the shadow area, the rough area, or the uneven area is called a so-called dynamic misalignment (DMA) phenomenon, which lowers the dot display uniformity and displays the dots. There is a problem of missing patterns.

  The state of occurrence of the above-described DMA phenomenon is considered to change due to various internal factors, for example, the pretilt angle and the frame response phenomenon of the liquid crystal caused by the azimuth angle regulation force.

  As an external factor, there is an oblique electric field generated between two electrode layers, that is, a segment electrode layer and a common electrode layer. An oblique electric field is generated between the edge of the segment electrode of the segment electrode layer and the flat portion of the common electrode of the common electrode layer, and between the edge of the common electrode of the common electrode layer and the flat portion of the segment electrode of the segment electrode layer In particular, the influence is large in the case of the vertical alignment type. That is, since the negative type liquid crystal in the vertical alignment type is tilted in the vertical direction with respect to the electric lines of force of the electric field, it is also tilted in the vertical direction with respect to the electric lines of force of the oblique electric field. As a result, when the liquid crystal director is in a different direction from the liquid crystal director by the alignment treatment, it is visually recognized as a black shadow region at the boundary portion.

  The shadow area described above is not a line but a wide area. It is considered that the shadowed region becomes a wide region because the liquid crystal molecules easily move in the substrate in-plane direction (azimuth angle direction). The state in which the liquid crystal molecules are easy to move includes a state in which the pre-tilt angle is near 90 ° near vertical and the orientation regulating force (anchoring) in the azimuth direction is weak, and the liquid crystal has good responsiveness. The high pretilt in which the former pretilt angle is close to 90 °, which is close to vertical, is necessary to improve sharpness and to obtain high contrast characteristics and wide viewing angle characteristics when performing high duty driving. Further, the latter state in which the liquid crystal has good response is when the liquid crystal material is a low-viscosity material, when the thickness of the liquid crystal layer is small, when the operating temperature is high, and the like. In any case, the liquid crystal molecules are more likely to fall in the azimuth direction of the oblique electric field than the azimuth direction regulated by the pretilt angle by the pulse waveform of the simple matrix drive. A liquid crystal director that deviates from the alignment processing direction from a point where an oblique electric field is generated in a different direction is developed. The liquid crystal molecules are aligned with each other in the alignment direction, and, as described above, the environment where the regulation force due to the alignment process is weak, the area where the liquid crystal director is displaced gradually expands from the base point to the periphery. As a result, the liquid crystal director is displaced from the alignment processing direction in a wide region.

  As a technique for preventing the occurrence of the shadow area described above, it is conceivable to suppress the frame response phenomenon. In other words, the frame frequency is increased, and the A waveform, C waveform, or multiline addressing (MLA) waveform is used to perform a high frequency driving method that shortens the pulse interval by simple matrix driving, thereby reducing the frame response phenomenon. Suppress. However, such a high-frequency driving method has problems that power consumption increases and a crosstalk phenomenon due to the resistance component of the electrode layer increases.

  Accordingly, an object of the present invention is to suppress the DMA phenomenon of a simple matrix vertical alignment type liquid crystal display panel without using a high frequency driving method.

  To solve the above problems, a simple matrix vertical alignment type liquid crystal display panel having a plurality of segment electrodes, a plurality of common electrodes, and a vertical alignment type liquid crystal cell provided at the intersection of each segment electrode and each common electrode is provided. In the driving method for simple matrix driving, at least one line of the common electrode is an off signal line (black signal line).

  A simple matrix vertical alignment type liquid crystal display device according to the present invention includes a plurality of segment electrodes, a plurality of common electrodes, and a vertical matrix type liquid crystal cell provided at the intersection of each segment electrode and each common electrode. The vertical alignment type liquid crystal display panel, the display data memory for storing the display content of the simple matrix vertical alignment type liquid crystal display panel for each data line, and each segment electrode is driven based on the storage content for each data line of the display data memory A segment drive circuit, a common drive circuit that scans and drives each common electrode, and a control circuit that writes off data to at least one data line of the display data memory are provided. That is, by supplying an off data signal to all of the segment electrodes, at least one line of the common electrode is set as an off signal line (black signal line).

  Further, the simple matrix vertical alignment type liquid crystal display device according to the present invention includes a plurality of segment electrodes, a plurality of common electrodes, and a vertical matrix type liquid crystal cell provided at the intersection of each segment electrode and each common electrode. The vertical alignment type liquid crystal display panel, the display data memory for storing the display content of the simple matrix vertical alignment type liquid crystal display panel for each data line, and each segment electrode is driven based on the storage content for each data line of the display data memory A segment drive circuit, a common drive circuit that scans and drives each common electrode, and an off signal supply circuit that is connected to the common drive circuit and supplies an off signal to at least one of the common electrodes. That is, by supplying an off signal to at least one of the common electrodes, at least one line of the common electrode is set as an off signal line (black signal line).

  According to the present invention, propagation of the DMA phenomenon is prevented by setting at least one line of the common electrode as an off signal line (black signal line). As a result, the DMA phenomenon can be suppressed. In addition, power consumption can be reduced and crosstalk can be reduced because high frequency driving is not required. Since the DMA phenomenon in the high temperature region is suppressed, the operating margin of the driving condition can be widened, and the power consumption can be reduced. Furthermore, since the high pretilt can be achieved, sharpness can be improved, that is, contrast and wide viewing angle characteristics can be improved.

  FIG. 1 is a block circuit diagram showing a first embodiment of a simple matrix vertical alignment type liquid crystal display device according to the present invention.

  In FIG. 1, reference numeral 1 denotes a simple matrix vertical alignment type liquid crystal display panel in which segment electrodes SEG0, SEG1,..., SEG319 as signal lines extending in the Y direction are arranged in parallel in the X direction. Common electrodes COM0, COM1,..., COMk,..., COM63 as scanning lines extending in the direction are arranged in parallel in the Y direction. Further, a vertical alignment type liquid crystal cell such as C11 is provided at the intersection of each segment electrode SEG0, SEG1,..., SEG319 and each common electrode COM0, COM1,. In this case, for example, the segment electrode layer 114 (see FIG. 3) constituting the segment electrodes SEG0, SEG1,..., SEG319 is located on the upper side, and the common electrodes COM0, COM1,. The common electrode layer 124 (see FIG. 3) is located on the lower side, whereby 320 × 64 pixels (dots) are formed between these electrode layers. In these electrode layers 114, 124, the electrodes SEG0, SEG1,..., SEG319; COM0, COM1,..., COMk, ..., COM63 have a line width of 405 μm and a space between the lines of 30 μm.

  The display data memory 2 is a bidirectional RAM for storing the display contents of the simple matrix vertical alignment type liquid crystal display panel 1 for each data line, and the display data latch circuit 3 is read from the display data memory 2 according to the clock signal CK1. The display contents of one data line are temporarily stored. The segment drive circuit 4 drives the segment electrodes SEG0, SEG1,..., SEG319 based on the display content of one data line of the display data memory 2 held in the display data latch circuit 3. The segment drive circuit 4 includes a digital / analog (D / A) converter, which sequentially converts each digital data signal of the display data latch circuit 3 into an analog data signal and sequentially supplies it to the segment electrodes SEG0, SEG1,. To do.

  The shift register 5 shifts the synchronization signal SYNC according to the clock signal CK2 to sequentially generate 64 output signals OUT0, OUT1,..., OUTk,. , 5-k,..., 5-63, and as a result, the common drive circuit 6 drives the common electrodes COM0, COM1,.

  The output signals of the segment drive circuit 4 and the common drive circuit 6 are inverted, for example, every frame in accordance with the clock signal CK3. An example of output signals OUT0, OUT1,..., OUTk,..., OUT63 of the shift register 5 and output signals of the common drive circuit 6 is shown in FIG.

  In the display data memory 2, data lines having the number of common electrodes are provided, and data D having the number of segment electrodes is written from the control circuit 9 to the data line designated by the write address ADDW from the control circuit 9. The data D of the number of segment electrodes is read from the data line designated by the read address ADDR and held in the display data latch circuit 3. The read address ADDR is generated by the address counter 7 which is reset by the synchronization signal SYNC and incremented by +1 by the clock signal CK2.

  The display timing generation circuit 8 generates clock signals CK1, CK2, and CK3.

  The control circuit 9 is constituted by a computer including a CPU, for example, and generates the above-described write address ADDW, data line data D and period signal SYNC, and controls the display timing generation circuit 8.

  FIG. 3 is a sectional view of the simple matrix vertical alignment type liquid crystal display panel 1 of FIG.

  The upper structure 11 includes the segment electrode layers 114 constituting the segment electrodes SEG0, SEG1,..., SEG319 of FIG. 1, and the lower structure 12 constitutes the common electrodes COM0, COM1,. The vertical alignment type liquid crystal layer 13 (liquid crystal cell Cij) is provided between the upper structure 11 and the lower structure 12 including the common electrode layer 124.

  The upper structure 11 includes a polarizing plate 111, an optical compensation plate 112, a glass substrate 113, a transparent segment electrode layer 114, an insulating layer 115, and a polymer vertical alignment layer 116. Similarly, the lower structure 12 includes a polarizing plate 121. , An optical compensation plate 122, a glass substrate 123, a transparent common electrode layer 124, an insulating layer 125, and a polymer vertical alignment layer 126.

  The polarizing plates 111 and 121 are made of an iodine-based material, a dye-based material or the like, and for example, Sola-13U manufactured by POLATECHNO is used. The crossing angle of the polarizing plates 111 and 121 is 90 °, and the crossing of + 45 ° and −45 ° with respect to the set liquid crystal director of the vertical alignment type liquid crystal layer 13 so that the change in phase difference when voltage is applied becomes the largest. It is a combination of Nicols. Note that 90 ° may be shifted by several degrees. The liquid crystal director of the vertical alignment type liquid crystal layer 13 is set to the upper side (12 o'clock direction) or the lower side (6 o'clock direction) when the dot is viewed from the front. A viewing angle display is obtained.

The optical compensators 112 and 113 are uniaxial retardation plates called negative C plates, and are composed of one C plate having an in-plane retardation value ΔR = 0 nm and a thickness direction retardation value ΔR _th = 220 nm. In place of the C plate, an A plate or a B plate which is a biaxial retardation plate may be used.

  The segment electrode layer 114 and the common electrode layer 124 are formed of indium tin oxide (ITO) or the like.

  The insulating layers 115 and 125 are for insulating the segment electrode layer 114 and the common electrode layer 124. There is an effect of preventing a short circuit between the substrate and the electrode due to foreign matters in the vertical alignment type liquid crystal layer 13 described later.

The polymer vertical alignment layers 116 and 126 are formed of polyimide, an inorganic film, or the like, and the alignment is controlled by protrusion alignment, rubbing treatment, ultraviolet alignment, or the like. For example, a film is formed by flexographic printing, then baked, and a pretilt angle θ _p of 89.5 ° or 89.9 ° is given by rubbing. In this case, the pretilt angle of the lower polymer vertical alignment layer 126 is the 12 o'clock direction (when the right is 0 degree, the counterclockwise 90 ° position), and the pretilt angle of the lower polymer vertical alignment layer 116 is Is antiparallel orientation in the 6 o'clock direction.

  The vertical alignment type liquid crystal layer 13 constitutes the vertical alignment type liquid crystal cell of FIG. 1, and is a negative type liquid crystal having a negative Δε, for example, a negative type liquid crystal having Δε = −2.6 and optical anisotropy Δn = 0.20. The thickness of the vertical alignment type liquid crystal layer 13 is 4.0 μm. A chiral agent for taking a twist structure can also be added.

  FIG. 4 is a flowchart for the control circuit 9 of FIG. 1 to write off data into the display data memory 2 together with the display data. Note that the control circuit 9 includes a frame memory for storing display data of 320 × 64 pixels.

  First, in step 401, the value j is reset (j ← 0).

  Next, in step 402, it is determined whether j = k. K is a value from 0 to 63-n + 1 (n = 1, 2,...). When j = k, the process proceeds to steps 403 to 407, and when j ≠ k, the process proceeds to step 408.

  Steps 403 to 407 will be described.

  In step 403, off data (= 0) is written to n data lines k, k + 1,..., K + n−1 of the display data memory 2.

  In step 404, the value k is incremented by +1. This is a step for moving the data line for writing off data in the scanning direction of the common electrode. Instead of +1, any value of +2,..., N may be used in order to increase the moving speed. +1 may be a value greater than n.

  In steps 405 and 406, the value k of the data line k is guarded with the maximum value 63-n + 1. That is, in step 405, it is determined whether or not k> 63-n + 1. Only when k> 63-n + 1, the value k is reset in step 406 (k ← 0). That is, the initial position of the off signal line (black signal line) is set to the first line of the screen to improve display uniformity. However, the reset value of the value k may be other than 0.

In step 407, the next data line of the display data memory 2 is written.
j ← j + n
Calculate by

  On the other hand, in step 408, the display data of the data line j of the frame memory is written into the data line j of the display data memory 2.

In step 409, the next data line of the display data memory 2 is written.
j ← j + 1
Calculate by

  The value j calculated in steps 407 and 409 is guarded at the maximum value 63 in step 410. That is, it is determined whether j> 63. As a result, when j> 63, the process proceeds to step 401. After the value j is reset (j ← 0), the flow of steps 402 to 409 is repeated. When j ≦ 63, the flow of steps 402 to 409 is directly performed. Is repeated.

  Based on the stored contents of the display data memory 2 in which the ON data of the frame memory is written together with the OFF data of one data line (n = 1) according to the flowchart of FIG. 4, the simple matrix vertical alignment type liquid crystal display panel 1 is driven to invert the frame. FIG. 5A shows the experimental results of driving with 1/64 duty and 1/9 bias drive frequency of 120 Hz using the B waveform. Further, FIG. 5B shows a comparative example 1 driven under the same conditions based on the stored contents of the display data memory 2 in which OFF data for dividing one data line into two at an arbitrary position is written. FIG. 5C shows a comparative example 2 driven under the same conditions based on the stored contents of the display data memory 2 written with on-data. In addition, the drive temperature in the case of (A), (B), (C) of FIG. 5 is the same. In FIGS. 5A, 5B, and 5C, the moire pattern on the right side of the screen is not a DMA phenomenon.

  In (A), (B), and (C) of FIG. 5, a difference was found in the DMA phenomenon. In order to more clearly understand the occurrence of the DMA phenomenon, the same as the simple matrix vertical alignment type liquid crystal display panel 1 based on the storage contents of the display data memory 2 in which the off data of 5 data lines (n = 5) is written. The experimental results driven under the conditions are shown in FIGS. 6 (A), 6 (B) and 6 (C).

  That is, in FIGS. 5A and 6A, the DMA phenomenon is suppressed in the scanning direction of the off signal line (black signal line). Further, in Comparative Example 1 in FIGS. 5B and 6B, the DMA phenomenon is suppressed in the scanning direction of the off signal line (black signal line), but the off signal line is divided into two. The DMA phenomenon spreads from the part in the direction opposite to the scanning direction. That is, it is considered that the liquid crystal director is propagating in the same manner as the wave travels. Furthermore, in the comparative example 2 of FIG. 5C and FIG. 6C, the DMA phenomenon occurs from the last row in the scanning direction.

  Since the above-mentioned DMA phenomenon occurs on the opposite side to the scanning direction, when steps 404 to 406 in FIG. 4 are deleted and the off signal line (black signal line) is stopped, k = 63−n + 1 is turned off. If the signal line (black signal line) is arranged in the last line (j = 63), the DMA phenomenon can be effectively suppressed.

  Further, in order to improve the display uniformity, the DMA phenomenon propagates in the direction opposite to the scanning direction, so the off signal line (black signal line) is made the same as the scanning direction by steps 404 to 406 in FIG. The movement of the DMA phenomenon can be suppressed by moving in the direction. Further, the visibility of the off signal line (black signal line) itself is also lowered, so that desired display data can be visually recognized.

  As described above, the DMA phenomenon can be more effectively suppressed by increasing the number n of the off signal lines (black signal lines). (A), (B), (C), (D), and (E) of FIG. 7 show cases where n = 1, 2, 3, 5, and 10. Here, in (A), (B), (C), (D), and (E) of FIG. 7, the moire pattern in the right portion of the screen is not a DMA phenomenon. That is, when the off signal line (black signal line) is increased, the area where the occurrence of the DMA phenomenon on the scanning direction side of the off signal line (black signal line) is suppressed increases. Incidentally, the line spacing of 30 μm between the common electrodes COM0, COM1,..., COMk,..., COM63 also acts as an off signal (black signal) region, but the DMA phenomenon cannot be suppressed as shown in FIG. Therefore, as the line width of the off signal (black signal) region, at least one data line, that is, each of the common electrodes COM0, COM1,..., COMk, the line width of 405 μm, or 435 μm obtained by adding 30 μm between the lines to the line width of 405 μm, Alternatively, 465 μm is required, which is obtained by adding 30 μm between lines on both sides of each line to 405 μm in each line width.

  FIG. 8 is a block circuit diagram showing a second embodiment of a simple matrix vertical alignment type liquid crystal display device according to the present invention. In FIG. 8, an off signal supply circuit 10 is inserted between the shift register 5 and the common drive circuit 6 in FIG. 1, so that the off signal supply circuit 10 can execute the flow of steps 403 to 407 in FIG. It is a thing.

  The off signal supply circuit 10 receives the output signals OUT0, OUT1,..., OUTk,..., OUT63 of the shift register 5 and also receives the off signal DOF from the control circuit 9, and receives this off signal from the display timing generation circuit 8. As a result, the output signals OUT0 ′, OUT1 ′,..., OUTk ′,. It is assumed that the frequency of the clock signal CK4 is significantly smaller than the frequency of the clock signal CK2.

  FIG. 9 is a detailed circuit diagram of the off signal supply circuit 10 of FIG. That is, the off-signal supply circuit 10 includes D flip-flop circuits 10-1, 10-2,..., 10-k, ..., 10-63 and AND circuits 11-0, 11-1,. 11-k, ..., 11-63.

  The D flip-flop circuits 10-0, 10-1, ..., 10-k, ..., 10-63 shift the off signal DOF by the clock signal CK4. For example, if the off signal DOF (= 0) is one bit of the clock signal CK4, as shown in FIG. 10, D flip-flop circuits 10-0, 10-1,..., 10-k,. One of 63 output signals DOF0, DOF1,..., DOFk,. Note that the output signals OUT0, OUT1,..., OUTk,..., OUT63 of the D flip-flop circuits 5-0, 5-1,. Yes.

  AND circuits 11-0, 11-1, ..., 11-k, ..., 11-63 are output signals DOF0 of D flip-flop circuits 10-0, 10-1, ..., 10-k, ..., 10-63, AND of DOF1, ..., DOFk, ..., DOF63 and D flip-flop circuits 5-0, 5-1, ..., 5-k, ..., 5-63 output signals OUT0, OUT1, ..., OUTk, ..., OUT63 The logic is calculated to generate output signals OUT0 ′, OUT1 ′,..., OUTk ′,. In the case of FIG. 11, the output signal OUTk 'is an off signal. As a result, as shown in FIG. 11, the off signal is supplied to the common electrode COMk. The common electrode COMk supplied with the OFF signal is moved in the same direction as the scanning direction of the common electrode by the D flip-flop circuits 10-0, 10-1, ..., 10-k, ..., 10-63.

  Further, by changing the length of the off signal DOF supplied to the off signal supply circuit 10, the number of common electrodes to which the off signal is supplied can also be changed.

  FIG. 12 is a flowchart for the control circuit 9 of FIG. 8 to write only display data into the display data memory 2. Note that the control circuit 9 includes a frame memory for storing display data of 320 × 64 pixels. As described above, since it is not necessary to write off-data, in FIG. 12, steps 402 to 407 in FIG. 9 are deleted, and the flow of step 401 proceeds directly to step 408.

  Further, the present invention can be applied to both transmissive and reflective simple matrix vertical alignment type liquid crystal display devices. In the case of the reflective type, a reflective layer is provided on one outer side of the polarizing plate, and incidence / emission is performed from the other polarizing plate.

1 is a block circuit diagram showing a first embodiment of a simple matrix vertical alignment type liquid crystal display device according to the present invention. FIG. FIG. 2 is a timing diagram showing an output signal of the shift register of FIG. 1 and an output signal of a common drive circuit. FIG. 2 is a cross-sectional view of the simple matrix vertical alignment type liquid crystal display panel of FIG. 2 is a flowchart for explaining the operation of the control circuit of FIG. 1. It is a photograph figure which shows the experimental result which driven the simple matrix vertical alignment type liquid crystal display device of FIG. It is a photograph figure which shows the experimental result which driven the simple matrix vertical alignment type liquid crystal display device of FIG. It is a photograph figure which shows the experimental result which driven the simple matrix vertical alignment type liquid crystal display device of FIG. It is a block circuit diagram which shows 2nd Embodiment of the simple matrix vertical alignment type liquid crystal display device based on this invention. FIG. 2 is a detailed circuit diagram of an off signal supply circuit in FIG. 1. FIG. 10 is a timing chart showing an output signal of the shift register 10 and an output signal of the shift register 5 of the off signal supply circuit of FIG. 9. FIG. 10 is a timing chart showing an output signal of the off signal supply circuit 10 of FIG. 9 and an output signal of the common drive circuit 6. It is a flowchart explaining operation | movement of the control circuit of FIG.

Explanation of symbols

SEG0, SEG1, ..., SEG319: Segment electrodes
COM0, COM1, ..., COMk, ..., COM63: Common electrode 1: Simple matrix vertical alignment type liquid crystal display panel 2: Display data memory 3: Display data latch circuit 4: Segment drive circuit 5: Shift register 6: Common drive circuit 7 : Address counter 8: Display timing generation circuit 9: Control circuit 10: Off signal supply circuit 11: Upper structure 12: Lower structure 13: Vertical alignment type liquid crystal layer 111: Polarizing plate 112: Optical compensator 113: Glass substrate 114: Segment electrode layer 115: insulating layer 116: polymer vertical alignment layer 121: polarizing plate 122: optical compensator 123: glass substrate 124: common electrode layer 125: insulating layer 126: polymer vertical alignment layer

Claims (8)

In a driving method for driving a simple matrix vertical alignment type liquid crystal display panel having a plurality of segment electrodes, a plurality of common electrodes, and a vertical alignment type liquid crystal cell provided at an intersection of each segment electrode and each common electrode, in a simple matrix drive ,
A driving method of a simple matrix vertical alignment type liquid crystal display panel, wherein at least one line of the common electrode is an off signal line.   2. The method of driving a simple matrix vertical alignment type liquid crystal display panel according to claim 1, wherein the off signal line moves in the scanning direction of the common electrode with time.   2. The method of driving a simple matrix vertical alignment type liquid crystal display panel according to claim 1, wherein the off signal line is achieved by supplying an off data signal to all of the segment electrodes.   2. The method of driving a simple matrix vertical alignment type liquid crystal display panel according to claim 1, wherein the off signal line is achieved by supplying an off signal to at least one of the common electrodes. A simple matrix vertical alignment type liquid crystal display panel having a plurality of segment electrodes, a plurality of common electrodes, and a vertical alignment type liquid crystal cell provided at the intersection of each segment electrode and each common electrode;
A display data memory for storing the display content of the simple matrix vertical alignment type liquid crystal display panel for each data line;
A segment drive circuit for driving each segment electrode based on the storage content of each data line of the display data memory;
A common drive circuit for scanning and driving each of the common electrodes;
A simple matrix vertical alignment type liquid crystal display device comprising: a control circuit for writing off data to at least one data line of the display data memory.   6. The simple matrix vertical alignment type liquid crystal display device according to claim 5, wherein the control circuit moves the off-data write data line of the display data memory in a scanning direction of the common electrode. A simple matrix vertical alignment type liquid crystal display panel having a plurality of segment electrodes, a plurality of common electrodes, and a vertical alignment type liquid crystal cell provided at the intersection of each segment electrode and each common electrode;
A display data memory for storing the display content of the simple matrix vertical alignment type liquid crystal display panel for each data line;
A segment drive circuit for driving each segment electrode based on the storage content of each data line of the display data memory;
A common drive circuit for scanning and driving each of the common electrodes;
A simple matrix vertical alignment type liquid crystal display device comprising: an off signal supply circuit connected to the common drive circuit and configured to supply an off signal to at least one of the common electrodes. 8. The simple matrix vertical alignment type liquid crystal display device according to claim 7, wherein the off signal supply circuit moves the common electrode supplied with the off signal in a scanning direction of the common electrode.

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