JP2010135030A - Semiconductor memory and method for analyzing defect of semiconductor memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory in which productivity is improved, and a method for analyzing defect of the same. <P>SOLUTION: The semiconductor memory includes the following respective circuits. A memory circuit includes a memory array and a memory control circuit, and write-in and read-out of memory information are performed. A test circuit performs test determination by write-in and read-out for the memory array. A latch circuit stores a determined defective address. A defective information analyzing circuit determines a defective mode by analyzing a defective address. A nonvolatile memory circuit stores defective mode information in accordance with the defective mode. The defective mode information is output through the memory control circuit. In a test by tester handler, the defective mode stored in the nonvolatile memory circuit for a defective product is read out during defect analysis, a defective product having a defective mode required for analysis is selected. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory and a semiconductor memory failure analysis method, for example, a technology effective for use in a semiconductor memory failure analysis technology before shipment.

The semiconductor memory chip is obtained by using a semiconductor failure analysis system including a failure classification workstation and an analysis workstation, which obtains a defective address from a semiconductor memory chip completed on the wafer without interfering with wafer testing of the semiconductor memory in mass production. Japanese Patent Laid-Open No. 2000-306395 proposes a method for classifying and analyzing defects.
Japanese Patent Laid-Open No. 2000-306395

  The production volume of semiconductor memory is controlled based on the production capacity of the factory and the shipment volume of each product. Therefore, the post-process period from assembly to warehousing / shipping tends to be shortened. Based on this, the inventors of the present application examined the risk of hindering the shipment due to the suspension of flow due to the occurrence of an abnormality in the sorting process. In other words, in the pre-shipment test, for a lot that is stagnant because it is not possible to determine whether or not to ship a good product in the lot due to an abnormality, etc. Need to flow. When the defect classification workstation and the analysis workstation used in the wafer test as described in Patent Document 1 are to be applied to the pre-shipment test, the equipment for acquiring and storing the failure address and the data processing equipment for each tester are connected. It is necessary to build a system. When there are many same numbers in the sorting process etc., it is not realistic because a large cost is required.

  When obtaining a product (semiconductor memory) that is subject to failure analysis, it is desirable to separate the defective chip into defective items at the end of screening in the pre-shipment test. However, the number of items that can be separated is limited due to tester handler restrictions. Limited. For this reason, it is necessary to re-sort semiconductor memory that has been determined to be defective before failure analysis, and it takes time for long-term tests, tests with poor reproducibility, and when using a small number of analysis testers. As described above, there is a risk that shipping may be hindered due to the suspension of flow due to the occurrence of an abnormality in the sorting process. In view of this, the inventors of the present application have studied a method for confirming even the failure mode in the sorting step and assigning failure information or the like to the semiconductor memory for identification.

  An object of the present invention is to provide a semiconductor memory and a failure analysis method for improving the productivity. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  One embodiment disclosed in the present application is as follows. The semiconductor memory has the following circuits. The memory circuit includes a memory array and a memory control circuit, and writes and reads stored information. The test circuit performs a test determination by writing to and reading from the memory array. The latch circuit stores the determined defective address. The failure information analysis circuit analyzes the failure address and determines a failure mode. The nonvolatile memory circuit stores failure mode information corresponding to the failure mode. The failure mode information can be output through a memory control circuit.

  Another embodiment disclosed in the present application is as follows. The semiconductor memory has the following circuits. The memory circuit includes a memory array and a memory control circuit, and writes and reads stored information. The test circuit performs a test determination by writing to and reading from the memory array. The latch circuit stores the determined defective address. The failure information analysis circuit analyzes the failure address and determines a failure mode. The nonvolatile memory circuit stores failure mode information corresponding to the failure mode. The failure mode information can be output through a memory control circuit. In the test by the tester handler after the process of assembling the semiconductor memory as a product, the test circuit of the semiconductor memory is operated to determine whether it is good or bad, and the failure mode for the defective product is stored in a nonvolatile memory circuit. Remember me. The failure mode stored in the nonvolatile memory circuit for the defective product at the time of the failure analysis is read, and the defective product having the failure mode necessary for the analysis is selected.

  Yet another embodiment disclosed in the present application is as follows. The semiconductor memory has the following circuits. The memory circuit includes a memory array and a memory control circuit, and writes and reads stored information. The test circuit performs a test determination by writing to and reading from the memory array. The latch circuit stores the defective address determined by the test circuit. The failure information analysis circuit analyzes a failure address held in the latch circuit to determine a failure mode. In a test by a tester handler having a marking portion after the step of assembling the semiconductor memory as a product, the test circuit of the semiconductor memory is operated to make a pass / fail judgment, and the marking portion causes the package surface to Perform marking corresponding to the failure mode. A defective product having a failure mode necessary for analysis is selected based on the mark given by the marking for the defective product at the time of the failure analysis.

  Productivity can be improved by shortening the flow stoppage time of lots due to abnormalities in the sorting process.

  FIG. 1 is a schematic block diagram showing an embodiment of a semiconductor memory according to the present invention. The semiconductor memory of this embodiment includes a memory array 1 that holds data, a memory control circuit 2 that controls the memory array 1 to write and read data, a failure information latch circuit 3 that stores failure information, and a power shutdown Thereafter, in order to hold the failure information, the failure information storage unit 4 made of a nonvolatile element and the failure information analysis circuit 5 for determining the failure mode based on the failure address / information are configured.

  The memory control circuit 2 receives a command, an address and data from the outside, and when a write operation is instructed by the command, selects the memory cell of the memory array 1 by the address and writes the input data. When a read operation is instructed by the command, the memory cell 1 of the memory array 1 is selected by the address and the stored data is read. Although not particularly limited, the memory control circuit 2 is provided with a test circuit BIST (BIST stands for built-in-self-test).

  The test circuit BIST includes a test address signal generation circuit, a test data generation circuit, a test data determination circuit, and the like, and tests from a standard test input circuit such as JTAG or a combination of input signals such as the command and address. When the mode is instructed, the operation state is set. In this test mode, the test circuit BIST writes a test pattern to the memory array 1 using a test address. The memory array 1 has a plurality of memory blocks, and the test pattern is written by simultaneously selecting the plurality of memory blocks and writing the same test data. The test data is determined by comparing all the data output from each memory block by reading. If all the bits match, it is determined to be good, and if one bit does not match the other bits, it is determined to be defective. The address from which the inconsistent data is output is determined as a defective address and held in the defective information latch circuit 3.

  FIG. 2 is a flowchart for explaining an example of the test operation of the semiconductor memory. This test operation is performed after the assembly of the semiconductor memory, that is, after the post-process is completed. In step (1), the tester-handler semiconductor memory to be tested is transferred to the measuring unit and electrically connected to the tester, so that the test can be started. In step (2), a test mode is instructed from the tester to the semiconductor memory under test, and defective address collection operation / entry is performed.

  In step (3), an internal determination test is performed. That is, the test circuit BIST is in an operating state, a test pattern is written to the memory array 1 by a test address, and test data is determined by reading. In this test data determination, if even one bit does not match, it is determined as fail, and the address is latched as a defective address in the defect information latch circuit 3 in step (4). In step (3), a plurality of times of writing and reading necessary for verifying that the storage operation of logic 1 and logic 0 is correctly performed for all the memory cells of the memory array 1 are performed. Fail / pass determination is performed. In the figure, the repetition is omitted, and when the fail / pass is performed for all addresses, the test of step (5) is ended.

  In step (6), the failure information analysis circuit 5 enters an operating state and enters a failure mode determination operation. In the failure mode determination operation in step (7), failure mode determination is performed by the failure information analysis circuit 5 using the failure address stored in the failure information latch circuit. In the failure mode reading in step (8), the determined failure mode is output to an external tester or the like via the memory control circuit 2. In writing of defect information and the like in step (9), information such as a defective address and a determined failure mode is held as nonvolatile data in the defect information storage unit 4 formed of an antifuse, a nonvolatile memory, or the like.

  In this embodiment, the determined failure mode is output to an external tester or the like via the memory control circuit 2. Therefore, the failure mode for the defective product in one lot is accumulated in real time on the tester side, so that the failure that normally occurs in the subsequent process of the semiconductor memory and the abnormal failure that is clearly different from the failure that normally occurs are early. Can be detected at the time. As described above, there is a case where it is not necessary to analyze as in the case where the cause of assembly or the cause of deterioration can be estimated by only acquiring the failure mode information at the time of sorting before shipment. It is possible to determine whether to stop shipping or to ship at an early stage.

  When the number of defective products for a lot is large after the sorting process, defect information and the like can be given and held for each semiconductor memory, so that a specific defect mode to be analyzed can be selected by outputting it. The defective product possessed can be identified from all the defective products, and the conventional re-sorting or the like is not necessary, so that the failure analysis time can be shortened. Further, the cause of assembly or the cause of deterioration can be estimated from the failure mode information at the time of selection, and the quality control standard can be optimized, so that the quality control standard can be optimized.

  FIG. 3 is an explanatory diagram showing an example of data held in the defect information latch circuit 3 of FIG. The defect information latch circuit 3 can store defect address data, defect mode determination data, and other defect information data. The row address is composed of 12 bits including 3 bits for mat selection and 9 bits for word line selection. The column address is composed of 9 bits including 1 bit for mat selection and 8 bits for data (bit) line selection. The failure mode determination data also includes a 12-bit row address change flag and a 9-bit column address change flag corresponding to the defective address data. The defective address data may be able to store a plurality of addresses, but the circuit scale becomes large. Therefore, in this embodiment, the failure mode determination data as described above is used, and a simple failure mode is determined by overwriting one failure address data as will be described later.

  FIG. 4 is an explanatory diagram showing an outline of the operation of the defect information latch circuit of FIG. The first defective address during the test is stored as defective address data. In this case, each change flag remains 0 in the failure mode determination data. The defective address data may be held in the defect information storage unit 4 of FIG. By holding it in the defect information storage unit 4, it is possible to confirm the defective address at the time of selection even after the power is shut off.

  The address that becomes defective after the second time is compared with the first defective address data. If there is a change in the defective address in this comparison, one data is stored in the corresponding portion of the defective mode determination data. That is, the first defective address is X = # 002 (000 000000010), Y = # 9 (0 000001001), the second defective address is X = # 084 (000 010000100), and Y = # 9 (0 000001001). ), The row address change flag of the failure mode determination data is set to flag 1 corresponding to the bit changed from 0 to 1 or 1 to 0 from the first time to the second time, and (000 01000110) It becomes like this. On the other hand, the column address is the same at the first time and the second time (0 000001001), so there is no changed bit and it remains the same. The same thing is performed for the defective address data every time a defect occurs from the third time onward. The third and subsequent times are compared with the previous defective address data.

  FIG. 5 is an explanatory diagram of the failure mode determination method according to the present invention. That is, six failure modes are determined based on the bit pattern of the failure mode determination data generated from one or a plurality of failure addresses in one semiconductor memory. As a result, simple failure mode determination can be performed using the one set of failure address data and failure mode determination data.

  When all bits are 0 (no flag), such as row address (000 000000000000) and column address (0 00000000) of failure mode determination data, that is, a failure exists but a failure detected one or more times. Since it indicates that the error occurred only at the same X and Y addresses, it is determined that one bit is defective.

  Adjacent bits when the least significant bit of the column address is 1 (small number of flags (conditions required)), such as the row address (000 000000000000) and the column address (0 00000001) of the failure mode determination data Since it indicates a line defect, it is determined that the pair bit is defective.

  The same bit line for a plurality of word lines when there is no column part flag, such as a row address (000 ******) or a column address (0 00000000) for data for determining a defective mode Since a defect occurs at the time of selection, it is regarded as a data (bit) line defect. Here, * may be 0 or 1. However, when all of them are 0, the 1-bit defect is excluded.

  Select the same word line for multiple bit lines when there is no row part flag, such as the row address (000 000000000000) and the column address (0 ******) for the failure mode determination data Since a defect occurs at this time, it is regarded as a word line defect. Again, * may be 0 or 1. However, when all of them are 0, the 1-bit defect is excluded.

  If there is no other mat part flag, such as the row address (000 *********) and the column address (0 *********) for the failure mode judgment data, the same mat It is determined that the internal failure.

  When there is another mat part flag, such as the row address (************) or column address (**********) of the failure mode judgment data Other defects are considered.

  In the semiconductor memory of this embodiment, one memory mat is divided into a plurality of blocks, and good / bad is determined by comparing read data by simultaneous selection as described above. At this time, a plurality of memory mats may be selected at the same time, and the number of comparison target bits may be increased to shorten the test time.

  The determined failure mode or the like is output to an external tester by a special command. As a result, the tester acquires statistical data such as a failure mode during the selection, enables early failure mode determination as described above, and can be used for quality control.

  The determined failure mode or the like can be held in the failure information storage unit. Thereby, even after the power is shut off, the state at the time of sorting can be confirmed. In other words, if it is determined that an abnormal defect has occurred in a specific lot, the defect mode stored in the defect information storage unit is read out from the defective product, and a defect mode that should be subjected to further defect analysis is quickly acquired. Can be sorted. Not only such a failure mode but also arbitrary defect information or the like (number) can be assigned from the outside. Thereby, identification information can be given and held for those that have failed in any test.

  Defect information and the like (lot number, date of manufacture, production line, etc.) held in the semiconductor memory are read out using special commands. As a result, even when the semiconductor memory is judged to be defective with respect to other lots, it is possible to identify the object to be analyzed in a short time by reading the same information.

  FIG. 6 shows a schematic configuration diagram of an embodiment of a tester handler used in the present invention. In this embodiment, the pre-test semiconductor memory is stored in the semiconductor memory tray in the insertion portion. As shown in the flow of the semiconductor memory indicated by the thick dotted line arrow in the figure, the semiconductor memories stored in the pre-test semiconductor memory tray of the input unit are sequentially transferred to the measurement unit by the transfer unit. In the measurement unit, the semiconductor memory is inserted into a socket or the like and electrically connected to the tester, so that the semiconductor memory can be operated from the tester. The tester performs a test using the semiconductor memory as a test mode, as represented by the processing unit.

  The semiconductor memories that have been tested are sorted into good / bad by the transport unit and stored in the semiconductor memory tray after the test of the discharge unit. The marking unit receives the failure mode information from the processing unit, and performs marking corresponding to the failure mode on the package of the semiconductor memory stored in the semiconductor memory tray after the test determined to be defective. In the discharge section, there are two types, a post-test semiconductor memory tray in which a non-defective semiconductor memory corresponding to the sorting is stored and a post-test semiconductor memory tray in which a defective semiconductor memory is stored. Although there is one, it is shown in FIG.

  The failure mode is digitized, and a corresponding binary number notation pattern or the like is marked on the package of the semiconductor memory waiting at the discharge unit. This eliminates the need for a non-volatile element that constitutes the defect information storage unit in the semiconductor memory, thereby reducing the circuit scale. Further, the defective mode may be stored in the nonvolatile element as described above, and marking may be performed.

  FIG. 7 shows an explanatory diagram of an example of the post-test semiconductor memory tray and marking in FIG. As shown in FIG. 7A, the semiconductor memory tray after the test is not particularly limited, but has a 5 × 7 semiconductor memory storage portion and 27 defective semiconductor memories are stored. ing. As one semiconductor memory is shown in an enlarged manner, four white circles aligned in the vertical direction are shown at the left end of the package.

  As shown in the marking example of FIG. 7B, by combining the combination of the presence / absence of five white circles (5 bits) and the position (digits) with binary notation, 32 failure modes such as decimal numbers 0 to 31 are possible. Information can be represented. For example, if six types of failure modes as shown in FIG. 5 are displayed, a combination of 3 bits (three white circles) may be used. When marking is performed in this way, the necessary products to be analyzed can be selected visually, and the tendency of defects in the lot can be determined simply by observing the marks of defective products stored in the semiconductor memory tray after the test. Can be easily determined.

  Although the invention made by the inventor has been specifically described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. For example, if a defective address is stored in the nonvolatile defect information storage unit 4 and the memory array 1 has a redundant circuit, a defective portion, that is, a defective word line, a defective data (bit line) using the defective address is used. ) May be replaced with redundant word lines and redundant data (bit) lines to perform defect relief. A product whose defective state has been eliminated by such defect repair is determined as a non-defective product.

  A semiconductor memory uses a dynamic memory cell whose memory cell is composed of an information storage capacitor and an address selection MOSFET, or a latch circuit in which the input and output of a CMOS inverter circuit are cross-connected to each other and an address selection MOSFET. What is necessary is just to be able to write and read stored information, such as those using static memory cells. The test circuit may be anything as long as it can determine whether the memory array section is good or bad as described above, and the memory control circuit for controlling the write and read operations of the memory array as in the embodiment of FIG. It is not a condition that it is incorporated in. This test circuit may be used in a probe test performed in a pre-process for forming a semiconductor memory chip on a semiconductor wafer. In the probe test, the failure information analysis circuit may be operated to determine the failure mode.

  The present invention can be widely used as a semiconductor memory in which writing and reading are performed, such as a dynamic RAM (random access memory) and a static RAM, and a failure analysis method thereof.

1 is a schematic block diagram of an embodiment of a semiconductor memory according to the present invention. FIG. 6 is a flowchart for explaining an example of a test operation of a semiconductor memory. FIG. 3 is an explanatory diagram of an example of data held in a defect information latch circuit 3 in FIG. 1. FIG. 2 is an explanatory diagram of an outline of operation of the defect information latch circuit of FIG. 1. It is explanatory drawing of the failure mode determination method which concerns on this invention. It is a schematic block diagram of one Example of the tester handler used for this invention. It is explanatory drawing of an example of the semiconductor memory tray after a test of FIG. 6, and marking.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Memory array, 2 ... Memory control circuit, 3 ... Defect information latch circuit, 4 ... Defect information storage part, 5 ... Defect information analysis circuit, BIST ... Test circuit,

Claims (6)

A memory circuit having a memory array and a memory control circuit for writing and reading stored information;
A test circuit for performing test determination by writing and reading to the memory array;
A latch circuit for storing a defective address determined by the test circuit;
A failure information analysis circuit for analyzing a failure address held in the latch circuit and determining a failure mode;
A nonvolatile memory circuit that stores failure mode information corresponding to the failure mode,
The failure mode information stored in the nonvolatile memory circuit can be output through the memory control circuit.
Semiconductor memory. In claim 1,
The memory array has a plurality of memory blocks,
The test circuit stores the same data at a specific address of the plurality of memory blocks, compares a plurality of read data from the addresses of the plurality of memory blocks, and determines whether all the data match. / Perform a test operation for defects.
Semiconductor memory. In claim 2,
The memory array has a redundant circuit for defect relief,
The nonvolatile memory circuit is
A defective address stored in the latch circuit;
The failure mode information is written via the latch circuit,
The redundant circuit is made operable in place of a defective portion by a memory access corresponding to a defective address stored in the nonvolatile memory circuit, and performs defect repair.
Semiconductor memory. A memory circuit having a memory array and a memory control circuit for writing and reading stored information;
A test circuit for performing test determination by writing and reading to the memory array;
A latch circuit for storing a defective address determined by the test circuit;
A failure information analysis circuit for analyzing a failure address held in the latch circuit and determining a failure mode;
A nonvolatile memory circuit that stores failure mode information corresponding to the failure mode,
The failure mode information stored in the nonvolatile memory circuit can be output through the memory control circuit.
In the test by the tester handler after the process of assembling the semiconductor memory as a product,
The test circuit of the semiconductor memory is operated to determine good / failure, and the failure mode information is stored in a nonvolatile memory circuit for a defective product.
Reading the failure mode information stored in the nonvolatile memory circuit for the defective product at the time of the failure analysis, and selecting a defective product having a failure mode necessary for the analysis,
Defect analysis method for semiconductor memory. A memory circuit having a memory array and a memory control circuit for writing and reading stored information;
A test circuit for performing test determination by writing and reading to the memory array;
A latch circuit for storing a defective address determined by the test circuit;
A failure information analysis circuit for analyzing a failure address held in the latch circuit and determining a failure mode;
In a test by a tester handler having a marking part after the process of assembling a semiconductor memory having a product as a product,
The test circuit of the semiconductor memory is operated to determine good / failure, and marking corresponding to the failure mode is performed on the package surface by the marking portion,
The defective product having the defective mode necessary for the analysis is selected by the mark given by the marking for the defective product at the time of the defective analysis.
Defect analysis method for semiconductor memory. In claim 4 or 5,
The failure mode information corresponding to the failure mode determined by the failure information analysis circuit is output to the tester handler to determine the specific failure.
Defect analysis method for semiconductor memory.

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