JP2001101896A - Replacement judging circuit for redundant circuit, semiconductor memory and semiconductor memory test device incorporating this circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a replacement judging circuit which can perform high speed replacement judgement, a semiconductor memory and a semiconductor memory test device incorporating this circuit. SOLUTION: This device is provided with a line counter 32 of a row address, a line defective memory 33 of a row address operated by a carry signal from its counter, a line defective memory 36 of a column address, a line defective memory 35 of a row address operated by a carry signal from its counter, and a bit defective memory 39 storing a defective arbitrary single cell, and also, test method is limited and replacement discrimination can be performed by a tested result and an address signal inputted from the outside in real time, quick judgement can be performed without a defect analyzing memory.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a replacement determination circuit for determining whether or not to switch a cell in which a failure is found as a result of a test to a redundant circuit (spare memory cell) provided in a semiconductor memory device. And a semiconductor memory test device having the same replacement determination circuit.

[0002]

2. Description of the Related Art Since a semiconductor memory device has a large number of fine memory cells and is manufactured through a complicated wafer process, it is difficult to always obtain 100% non-defective cells due to manufacturing technology. For this reason, a spare memory cell (redundant cell or redundant circuit) is provided in advance, and when a defective cell is found as a result of the test, the defective cell is replaced with the redundant cell and used to improve the quality and improve the yield. A so-called redundant circuit system is usually used.

Conventionally, a judgment process for replacing such a defective cell with a redundant circuit has been performed on the memory test apparatus side. In other words, the memory test apparatus has a failure analysis memory having memory cells of the same or larger capacity as the memory under test, which is known in advance to be good, and performs a failure analysis on the test result of the memory under test during the test. It is reproduced on a memory, and after completion of the test, the contents of the failure analysis memory are searched to determine whether the memory under test can be rescued.

[0004] Hereinafter, the determination of replacement of a conventional semiconductor memory device with a redundant cell will be described in detail.

FIG. 4 shows a configuration of a general semiconductor memory. A memory cell array 10 in which a large number of memory cells are arranged in a matrix, a row decoder 11 for selecting memory cells belonging to the same row of the memory cell array 10, A sense amplifier 14 connected to a column line of a memory cell and amplifying an output from the memory cell, a column decoder 13 for selecting a column line, an address generation circuit 17 for generating an address signal, and a row decoder 11 based on the address signal And a data input / output buffer 15 for transmitting and receiving input data and output data between an address buffer 12 for generating a row address and a column address to be supplied to a column decoder, respectively, and a sense amplifier 14. Control for input / output buffer 15 And a control circuit 16 for generating a degree. Further, a spare memory cell (redundant circuit) and a program circuit (not shown) for selecting the spare memory cell
have. This program circuit is composed of a fuse, and switches between the original memory cell and the spare memory cell by fusing the fuse.

The operation of such a semiconductor memory device will be described. First, at the time of writing, a write signal is enabled, and when an address signal is input from the outside, a memory cell to be written is selected by the row decoder 11 and the column decoder 13, and externally input data is input to the memory cell. The data is written via the output buffer 15 and the sense amplifier 14.

Next, at the time of reading, a read signal is made valid. Similarly, a memory cell to be read is selected by an external address, amplified by a sense amplifier 14, and then output to the outside via a data input / output buffer. You.

In the case where a defective cell is found and a spare memory cell is used, address selection is performed after first selecting a normal memory cell and a spare memory cell by fusing the fuse. Only the writing and reading methods are the same as the normal memory cells.

FIG. 5 is an explanatory diagram showing the concept of a generally performed defective cell replacement determination and replacement method. In this example, it is assumed that two spare cells are provided for both rows and columns in a 16 × 16 memory matrix, and it has been discovered that one row line defect and a 3-bit cell defect exist in the memory cells.

As described above, the conventional semiconductor memory test apparatus is provided with a failure analysis memory for storing failure information. In the example of FIG. 5, the same failure content is stored at the relevant address of the failure analysis memory.

In this state, as a general replacement determination method, the function of the semiconductor memory test method is used, and first, the number of defective cells in each of the row and column directions is counted. In this example, the defect count of the row is 0, 0, 16, 0, 0,
1, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0,
The column defect count is 1, 1, 1, 2, 1, 1 from address 0.
2, 1, 1, 1, 2, 1, 1, 1, 1, 1.

If the number of defective cells is larger than the number of replaceable spares, it is regarded as a line defect. In this example, since address 2 of the row has a defect of 16 cells, it is regarded as a line defect, and one of the spare memory cell rows is allocated for relief.

Next, when this line defect is deleted from the defect analysis memory to make only the cell defect, and the counting process is performed in the same manner, three cell defects remain in this example, and one spare memory cell row is sequentially placed in this order. Since two spare memory cell columns are vacant, they can be sequentially allocated as spares and relieved. On the other hand, for example, when there are four defective cells other than the row line defect, the spare cells are insufficient, and repair is impossible.

[0014]

As described above, in the conventional semiconductor memory test apparatus, replacement determination with a spare memory cell is performed, and it is confirmed that there is no defect in performing this determination. The failed analysis memory must have the same or larger capacity as the non-test memory, so that the cost of the test apparatus cannot be avoided.

Further, in recent years, the memory capacity has been increased and the redundancy circuit has become more complicated, and the processing time for the replacement judgment using the failure analysis memory has increased, thereby increasing the test cost. For example, a memory test performs a test for a very large number of items, but the test time usually takes about one second for each item, resulting in a very long test time as a whole.

In particular, in recent semiconductor devices, the number of types in which a large-capacity memory and a logic IC are mixed is increasing, but in such an embedded memory, the test cost of the logic part and the test cost of the memory part are added. , Test costs tend to rise sharply.

Further, in order to improve productivity, a so-called GO-NO
In the case of the GO test, if the test time for each item is short, the next test cannot be performed during the replacement determination, so that useless time is wasted and the test efficiency is reduced.

The present invention has been made to solve such a problem, and without using a dedicated analyzer,
Further, a circuit for performing replacement determination of a semiconductor memory with a spare memory cell capable of performing replacement determination at the same time as testing and at a high speed, and a semiconductor memory device and a semiconductor memory test device equipped with this circuit are provided. The purpose is to provide.

[0019]

According to the present invention, there is provided a redundancy determining circuit for replacing with a redundant circuit, a first counter for counting a defect at a designated row address of a semiconductor memory cell array, and detecting a change in the row address. Operating with a first detection circuit and a carry signal from the first counter;
A first memory for storing a line defect of a row address;
Second to count failures at specified column addresses
A second detection circuit that detects a change in the column address; a second memory that operates on a carry signal from the second counter and stores a line defect of the column address; A row address comparing circuit for comparing the stored contents of the memory with the row address; a third memory for simultaneously storing the row address and the column address of the cell in which a defect has been detected; An address control circuit for designating a storage address to the third memory based on a carry signal from the second counter and an output of the row address comparison circuit.

In this replacement determination circuit for a redundant circuit, a line counter of a row address, a line defective memory of a row address operated by a carry signal from the counter,
Equipped with a column address line fault memory, a column address line fault memory that operates with the carry signal from the counter, and a bit fault memory that stores any single cell fault, and limits the test method. Since the replacement determination is enabled in real time by the input address signal, quick determination is possible without having a failure analysis memory.

According to the semiconductor memory device of the present invention, in addition to the replacement determining circuit for the redundant circuit, a semiconductor memory cell array, an address generating circuit for supplying an address signal to the semiconductor memory cell array, A data comparison circuit that compares read data of the semiconductor memory cell array with external expected value data,
The replacement determination circuit is operated by a mismatch signal from the data comparison circuit.

In this semiconductor memory device, since the output data comparison circuit and the replacement determination circuit are provided on the same chip, a test result is obtained on the chip, and the replacement determination circuit is used based on the test result and an externally input address signal. Makes it possible to determine the replacement, so that the test time can be shortened and the test apparatus can be simplified.

Further, according to the semiconductor memory test apparatus of the present invention, in addition to the replacement determination circuit for the redundant circuit, an address to be supplied to the semiconductor memory under test is generated and an expected value in the test is generated. And a comparison circuit for comparing read data from the memory under test with expected value data from the pattern generation circuit.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is an overall view of a semiconductor memory device according to the present invention. The memory unit 1 is the same as the memory 1 described in FIG. 3, and has the same address signal, read signal,
A write signal and an input data signal are input, and an output data signal is output.

There is provided a data comparison circuit 2 which receives an output data signal, an input data signal, and a read signal of the semiconductor memory 1, and the data comparison circuit 2 receives the input data signal while the read signal is being supplied. Compare with the output data signal. A replacement determination circuit 3 is provided that receives a FAIL signal, an address signal, and various control signals, which are signals output from the data comparison circuit 2 when the input data signal and the output data signal do not match. In the replacement determination circuit 3, the address signal is FAIL
It is checked whether or not a signal has been issued, and a repair data signal for a defective address to be replaced is output as a determination result signal.

FIG. 2 is a block diagram showing a configuration of the replacement determination circuit 3 in FIG. The replacement determination circuit can be broadly divided into a line defect counting section for a row address, a line defect counting section for a column address, and a memory group for storing an arbitrary cell defect.

The line defect counting unit for the row address receives an address change detection circuit 31 receiving the row address signals RA0-RA3, and outputs the output of the address change detection circuit 31 and the FAIL signal output from the data comparison circuit 2. A line counter 32 of a row address to be input, and a row carry signal RCR output from the line counter 32
It comprises a row address memory 33 having a row address which receives Y and a row address signal, and a row address comparison circuit 34 which receives an output signal of the line error memory 33 and row address signals RA0-3.

The line address counting unit for the column address receives an address change detection circuit 37 to which the column address signals CA0-3 are input, and outputs the output of the address change detection circuit 37 and the FAIL signal output from the data comparison circuit 2 to each other. A line counter 36 of a column address to be input, and a column carry signal C as an output of the line counter 36
It comprises a line defect memory 35 of a column address which receives CRY and a column address signal.

A memory group for storing a cell failure is provided with an address pointer 38 which receives a column carry signal CCRY, a row match signal RMTCH output from the address comparison circuit 34, a FAIL signal, and a PCGO signal for enabling operation. And a bit defective memory 39 to which the output signal of the address pointer 38, the row address signal, and the column address signal are input.

Next, the operation of the replacement determination circuit 3 will be described.

First, a memory test for scanning the column address first is performed. As a result, the row address signal R
In A0-3, the address change detection circuit 31 operates for each word line, sends an initialization signal to the line counter 32, and initializes the counter 32. The counter 32 changes the column address CA0-3 and the FA generated at that time.
Incremented by the IL signal. Counter 32
Is configured with the same size as the spare number of columns, so that when the FAIL signal is generated beyond the counter size by scanning the column addresses CA0-3, the carry signal RCRY is output.
Becomes effective, and recognition as a line defect is performed. This signal RCRY is output to the line defect memory 33 as an increment signal, and the row address is stored in the memory 33 together with the count of the number of line defects. Also,
When the count in the counter 32 exceeds the number of spare rows, a ROVER signal, which is an unrepairable signal, is output.

Next, a memory test for scanning the row address first is performed. At this time, the address change detection circuit 31 outputs an initialization signal every cycle,
Since the carry signal RCRY is always invalid, the contents of the line defect memory 33 of the row address are preserved.

Similarly to the row address group, the address change detection circuit 37 operates the column address signal CA0-3 for each bit line, sends an initialization signal to the line counter 36, and initializes the counter 36. The counter 36 changes the row address RA0-3 and the FAIL generated at that time.
Incremented by signal. Since the counter has the same size as the spare number of rows, if the FAIL signal is generated to be equal to or larger than the counter size by scanning the row addresses RA0-3, the carry signal CCRY becomes valid and the line is recognized as defective. This signal is output to the line defect memory 35 as an increment signal, and the column address is stored in the memory 35 together with the count of the number of line defects. When the number of spare count columns in the counter 36 is exceeded, a COVER signal, which is a non-recoverable signal, is output.

When the signal PCGO for validating the pointer circuit 38 is validated in the test for scanning the row address first, the bit defective memory operates simultaneously with the line count of the column address. Address pointer circuit 3
8 is normally incremented by the FAIL signal, and the address indicated by the pointer circuit 38 is stored in the bit defect memory 39.
Is an address signal.

Therefore, normally, when a defect is detected during the test, the row address and the column address defect address are stored in the bit defect memory 39 simultaneously with the increment of the line defect memory 36. In order to store only the cell failure in the bit failure memory, a failure which has been regarded as a row line failure is compared at any time by the row address comparison circuit 34, and the row address signal RA0 input simultaneously with the FAIL signal is output. -3 is line defective memory 3
If the number matches 3, the address pointer is not incremented.

A line address 3 for a column address
If the carry signal CCRY becomes valid in step 6, since the column defective address does not need to be stored in the bit defective memory because of a line defect, the change from the column address change detection to the output of the carry signal is output. Cycle is decremented. By these operations, the line defect and the cell defect of the row and column are separated from the cell and the address to be replaced is stored in each memory simultaneously with the test.

As described above, according to the present invention, the operation in the test method is limited. That is, first, a line defect in the row direction is detected by performing a test for changing the column first, and if there is a defect, it is stored in the line defect memory of the row address. Next, a test for changing the row first is performed to detect a line defect of the column, and a row address comparison circuit compares the row address of the line defect memory of the row address with the row address at the time of the defect detection together with the storage in the memory. Line defects need not be re-detected, only pure cell defects can be detected. For this reason, the defect analysis memory which has been required conventionally becomes unnecessary.

In this embodiment, it has been assumed that the entire configuration shown in FIG. 1 is on the same semiconductor chip. However, this is not always necessary, and the memory section shown in FIG. It can also be configured as

Further, the circuit for determining the replacement with the redundant circuit can be provided on the test device side of the semiconductor memory.

FIG. 3 is a block diagram showing an example of such a memory test apparatus. The memory test apparatus 20 generates a test pattern and a designated address and sends it to a memory under test (DUT) 30.
1. A comparison circuit 2 which receives an output from the memory under test 30 and compares it with an expected value in a test pattern.
2. A replacement determination circuit 23 for performing replacement determination based on a FAIL signal output from the comparison circuit, and an address failure memory 2 for storing a defective address based on an output of the replacement determination circuit 23.
4 is provided. Here, the replacement determination circuit is basically the same as that shown in FIG. 2, but the memory portion of the replacement determination circuit in FIG.

The operation of this test apparatus is basically the same as that of the above embodiment except that the memory cell array is changed to the semiconductor memory under test. The memory is scanned first in the row direction and then in the column direction. Is adopted.

Therefore, since a line defect and a cell defect are identified in real time in the replacement determination circuit, a defect analysis memory having the same capacity as the semiconductor memory under test is not required, and the cost of the device is reduced, and the test time is reduced. Can also be shortened.

Such a test apparatus is particularly suitable for an application in which a variety whose quality is stable is tested in large quantities.

[0045]

As described above, in the replacement determination circuit for the redundancy circuit according to the present invention, a row address line counter, a row address line fault memory operated by a carry signal from the counter, and a column address line fault. A line failure memory of a column address operated by a memory and a carry signal from a counter thereof, and a bit failure memory for storing an arbitrary single cell failure, and a test method is limited, and a test result and an externally input address signal are provided. Since the replacement determination is made possible in real time, a quick determination can be made without having a failure analysis memory. In the semiconductor memory device according to the present invention, the output data comparison circuit and the replacement determination circuit are provided on the same chip. The test results are obtained on the chip, and the test results and external Due to the possible replacement determination by replacement determining circuit by address signal, together it is possible to shorten the test time, it is possible to simplify the testing equipment.

Further, according to the semiconductor memory test apparatus of the present invention, in addition to the replacement determination circuit for the redundant circuit, a pattern generation circuit for generating an address and a test pattern for the semiconductor memory under test, A comparison circuit that compares the read data with the expected value data from the pattern generation circuit eliminates the need for a large-capacity failure analysis memory, thereby reducing the cost of the apparatus and reducing the test time. it can.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of a semiconductor memory device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a circuit for determining replacement with a redundant circuit in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a semiconductor test apparatus according to the present invention.

FIG. 4 is a block diagram showing a configuration of a conventional general semiconductor memory.

FIG. 5 is an explanatory diagram illustrating a replacement determination process.

[Explanation of symbols]

 Reference Signs List 1 memory section 2 data comparison circuit 3 replacement determination circuit 10 memory cell array 11 row decoder 12 address buffer 13 column decoder 14 sense amplifier 15 data input / output buffer 16 control circuit 21 pattern generation circuit 22 comparison circuit 23 replacement determination circuit 24 address defective memory 31 , 37 Address change detecting circuit 32, 36 Line counter 33, 35 Line defective memory 34 Row address comparing circuit 38 Address pointer 39 Bit defective memory

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[Procedure amendment]

[Submission date] October 12, 1999 (1999.10.
12)

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG.

FIG. 2

FIG. 3

FIG. 4

FIG. 5

Claims (5)

[Claims] A first counter for counting a defect in a designated row address of the semiconductor memory cell array; a first detection circuit for detecting a change in the row address; and a carry signal from the first counter. A first memory for storing a line defect at a row address, and a second memory for counting a defect at a designated column address.
A second detection circuit that detects a change in the column address; a second memory that operates with a carry signal from the second counter and stores a line defect of the column address; A row address comparison circuit for comparing the contents of a memory with the row address; a third memory for simultaneously storing the row address and the column address of a cell in which a defect has been detected; An address control circuit for designating a storage address to the third memory based on a carry signal from the counter of No. 2 and an output of the row address comparison circuit. 2. The method according to claim 1, wherein the first counter has the same count as the number of spare columns, is initialized by the first change detection circuit, and is incremented when a test result is defective. 2. The redundancy according to claim 1, wherein the counter has the same count as the number of spare rows, is initialized by the second change detection circuit, and is incremented when a test result is defective. Replacement determination circuit for the circuit. 3. A semiconductor memory cell array, an address generating circuit for supplying an address signal to the semiconductor memory cell array, a replacement determination circuit for a redundancy circuit according to claim 1, and read data of the semiconductor memory cell array. A semiconductor memory device, comprising: a data comparison circuit for comparing external expected value data; and operating the replacement determination circuit with a mismatch signal from the data comparison circuit. 4. A pattern generating circuit for generating an address to be supplied to a semiconductor memory under test and generating an expected value in a test, a replacement determination circuit for a redundant circuit according to claim 1, and A semiconductor memory test device comprising: a comparison circuit that compares read data from a memory with expected value data from the pattern generation circuit. 5. The semiconductor memory test apparatus according to claim 3, wherein the first to third memory portions in the replacement determination circuit are configured as independent address defective memories.