JP2010134904A5 - - Google Patents
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- Publication number
- JP2010134904A5 JP2010134904A5 JP2009171515A JP2009171515A JP2010134904A5 JP 2010134904 A5 JP2010134904 A5 JP 2010134904A5 JP 2009171515 A JP2009171515 A JP 2009171515A JP 2009171515 A JP2009171515 A JP 2009171515A JP 2010134904 A5 JP2010134904 A5 JP 2010134904A5
- Authority
- JP
- Japan
- Prior art keywords
- data
- memory chip
- control signal
- data output
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004913 activation Effects 0.000 claims 20
- 230000004044 response Effects 0.000 claims 2
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020080124267A KR100968461B1 (ko) | 2008-12-08 | 2008-12-08 | 메모리 모듈 및 데이터 입출력 시스템 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2010134904A JP2010134904A (ja) | 2010-06-17 |
| JP2010134904A5 true JP2010134904A5 (cg-RX-API-DMAC7.html) | 2012-09-06 |
Family
ID=42230874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2009171515A Pending JP2010134904A (ja) | 2008-12-08 | 2009-07-22 | メモリモジュール及びデータ入出力システム |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US7894231B2 (cg-RX-API-DMAC7.html) |
| JP (1) | JP2010134904A (cg-RX-API-DMAC7.html) |
| KR (1) | KR100968461B1 (cg-RX-API-DMAC7.html) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100968458B1 (ko) * | 2008-10-14 | 2010-07-07 | 주식회사 하이닉스반도체 | 반도체 메모리 장치 |
| JP5710992B2 (ja) | 2011-01-28 | 2015-04-30 | ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． | 半導体装置 |
| JP2013114415A (ja) * | 2011-11-28 | 2013-06-10 | Elpida Memory Inc | メモリモジュール |
| US9070572B2 (en) | 2012-11-15 | 2015-06-30 | Samsung Electronics Co., Ltd. | Memory module and memory system |
| US10901734B2 (en) | 2019-03-01 | 2021-01-26 | Micron Technology, Inc. | Memory mapping using commands to transfer data and/or perform logic operations |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5666322A (en) * | 1995-09-21 | 1997-09-09 | Nec Electronics, Inc. | Phase-locked loop timing controller in an integrated circuit memory |
| JPH10302470A (ja) | 1997-04-28 | 1998-11-13 | Nec Corp | 半導体記憶装置 |
| JP3249805B2 (ja) * | 2000-01-01 | 2002-01-21 | 株式会社日立製作所 | 半導体装置 |
| US7078793B2 (en) * | 2003-08-29 | 2006-07-18 | Infineon Technologies Ag | Semiconductor memory module |
| DE102005053625B4 (de) * | 2005-11-10 | 2007-10-25 | Infineon Technologies Ag | Speichermodul mit einer Mehrzahl von Speicherbausteinen |
| US7471538B2 (en) * | 2006-03-30 | 2008-12-30 | Micron Technology, Inc. | Memory module, system and method of making same |
| JP5087886B2 (ja) * | 2006-08-18 | 2012-12-05 | 富士通株式会社 | メモリ制御装置 |
| KR100842403B1 (ko) | 2007-03-08 | 2008-07-01 | 삼성전자주식회사 | 메모리 모듈 및 메모리 모듈 시스템 |
-
2008
- 2008-12-08 KR KR1020080124267A patent/KR100968461B1/ko not_active Expired - Fee Related
-
2009
- 2009-06-12 US US12/483,328 patent/US7894231B2/en not_active Expired - Fee Related
- 2009-07-22 JP JP2009171515A patent/JP2010134904A/ja active Pending