JP2010128793A - Bus clock control device, control method thereof and memory card controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve a smooth frequency change without disturbing a synchronizing state even when a clock frequency on a bus is changed and to obtain efficient bus operation. <P>SOLUTION: A bus clock control device includes: a plurality of bus masters 11, 21 having respectively different frequencies of operation clocks; a plurality of bus slaves 12, 22; a bus 100; a clock generation circuit 30 for obtaining a plurality of operation clocks having respectively different frequencies by using a reference block; and a bus arbiter 40 for controlling the clock generation circuit in response to bus use right request signals from the bus masters and sets operation clocks corresponding to the bus masters and the bus slaves. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a bus clock control device, a control method therefor, and a memory card controller. In particular, the bus clock arbiter is used to obtain an efficient bus operation.

  In a circuit in which a plurality of buses, a plurality of controllers, etc. are constructed in a data processor, an arbiter for arbitrating the right to use the bus is provided (for example, Patent Document 1).

  The bus arbiter lowers or stops the clock frequency during a period not requiring high-speed processing. Also, arbitration is performed to stop clocks to module blocks that do not need to be operated.

In the conventional apparatus, when the bus right is transferred from the first module to the second module having a clock frequency different from that of the first module, the operation of the first module is stopped, and the risk of malfunction is eliminated. A clock is supplied to the second module.
JP 2003-58271 A

  An object of the present invention is to provide a bus clock control device, a control method thereof, and a memory capable of realizing a smooth frequency change without disturbing the synchronization state even when the clock frequency on the bus changes, and obtaining an efficient bus operation. To provide a card controller.

  In order to solve the above problems, in an embodiment according to the present invention, a bus master that operates with an operation clock having a different frequency, a plurality of bus slaves corresponding to the bus master that operates with the different frequency, and the bus master And a connection element for connecting the plurality of bus slaves, a clock generation circuit for selectively obtaining operation clocks of different frequencies, and controlling the clock generation circuit in response to a bus use right request from the bus master And a bus arbiter that sets an operation clock frequency adapted to the bus master and the bus slave that have acquired the right to use the bus.

  According to the above means, the plurality of clocks output from the clock generation unit are in a synchronized state regardless of the frequency, and the bus clock synchronization on the bus is stable regardless of which frequency is switched. The bus master and bus slave also operate stably in synchronization.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a basic circuit configuration of an embodiment of the present invention. Reference numeral 100 denotes a bus. A first bus master 11 and a first bus slave 12 corresponding to the first bus master 11 are connected to the bus 100. Furthermore, a second bus master 21 and a second bus slave 22 corresponding to the second bus master 21 are connected to the bus 100. The bus 100 includes an address bus and a data bus.

  The first bus master 11 is a central processing unit (CPU), for example, and the first bus slave 12 is a register, for example. The second bus master 21 is, for example, a direct memory access unit (DMA unit), and the second bus slave 22 is, for example, a system memory.

  Although two bus masters and two bus slaves are shown in the figure, more bus masters and bus slaves may exist. Although only the bus 100 is shown in the drawing, the elements for connecting the bus master, the bus slave, and the like are not limited to the bus alone, but a buffer, an interface, or the like may be interposed in the middle. Therefore, the bus 100 may be expressed as a connection element or a connection element including a bus.

  Reference numeral 30 denotes a clock generation circuit. In the clock generation circuit 30, a basic clock is input to the gate circuits 301, 302, 303, and 304 via a buffer amplifier. Each of the gate circuits 301 to 304 is controlled by a gate control signal, and can output clocks having different frequencies obtained by dividing the basic clock. The gate circuits 301, 302, 303, and 304 are output via a buffer, and this buffer forms a clock tree, and delay adjustment is performed so that each bus clock (CLK_A or the like) is synchronized. The settings of the outputs (operation clocks) of the gate circuits 301, 302, 303, and 304 are controlled by gate control signals GATE_M0, GATE_S1, GATE_C, and GATE_S0 that are input via the OR circuits OR1-OR4. Gate control signals GATE_M0, GATE_S1, GATE_C, and GATE_S0 are output from the bus arbiter 40.

  Note that the ON / OFF of the outputs (operation clocks) of the gate circuits 301, 302, 303, and 304 is not only the gate control signals GATE_M0, GATE_S1, GATE_C, and GATE_S0 from the bus arbiter 40, but also gates from other circuits as necessary. It may be controlled by a control signal.

  The clock CLK_C from the gate circuit 303 is supplied to the first bus master 11, and the clock CLK_S 0 from the gate circuit 304 is supplied to the first bus slave 12. The clock CLK_M0 from the gate circuit 301 is supplied to the second bus master 21, and the clock CLK_S1 from the gate circuit 302 is supplied to the second bus slave 22.

  The gate control signals GATE_M0, GATE_S1, GATE_C, and GATE_S0 are output from the bus arbiter 40. Here, the bus arbiter 40 is connected to the bus 100 and has a table which is combination information of a bus master and a bus slave. That is, the bus master and the bus slave corresponding to the bus master are recognized. Furthermore, the operation frequency necessary for each bus master and bus slave, that is, the operation clock to be supplied is recognized.

  The bus arbiter 40 is supplied with request signals REQ_C and REQ_M0 for requesting the right to use the bus from the bus master 11 and the bus master 21. The bus arbiter 40 is supplied with the clock CLK_A having the highest frequency in the present apparatus from the clock generation circuit 30. The bus arbiter 40 operates based on this clock CLK_A.

  The bus arbiter 40 uses an algorithm such as a fixed priority method or a round robin method, and when a plurality of bus masters issue a bus access request, adjustment control is performed so that one bus master is selected at a time and the right to use the bus is obtained. I do.

  Here, for example, it is assumed that the bus master 21 has the right to use the bus. The bus master 21 performs bus access, issues an address, and selects, for example, the bus slave 22. Then, when the bus arbiter 40 determines from the combination of the bus master 21 and the bus slave 22 that the path requires, for example, a high-speed clock, the bus arbiter 40 controls the corresponding gate circuits 301 and 302. As a result, supply of the high-speed clocks of the bus clocks CLK_M0 and CLK_S1 to the bus master 21 and the bus slave 22 is started. This function is suitable when the bus master 21 is a DMA and the bus slave 22 is a system memory, and is used when a large amount of data is transferred at high speed.

  It is also assumed that the bus master 11 has obtained the right to use the bus. At this time, the bus master 11 accesses the bus, issues an address, and selects the bus slave 12, for example. Then, if the bus arbiter 40 determines from the combination of the bus master 11 and the bus slave 12 that the path requires, for example, a low-speed clock, it controls the corresponding gate circuits 303 and 304. As a result, supply of the low-speed clocks of the bus clocks CLK_C and CLK_S0 to the bus master 11 and the bus slave 12 is started. This function is suitable when the bus master 11 does not require a high-speed operation such as a CPU and the bus slave 12 does not require a register, and register data can be transferred from the CPU to the register.

  Since the bus arbiter 40 generates the clock gate control signal, the bus master and bus slave clocks may be stopped or the clock frequency may be changed within a range in which no problem occurs in the system when the bus is not accessed. Is possible.

  FIG. 2 shows a timing chart for explaining an operation example of the above-described apparatus. CLK_A is the clock after the clock tree and has the highest frequency, and is supplied to the bus arbiter 40.

  GATE_C / S 0 is a gate control signal supplied to the bus master (CPU) 11 and the bus slave (register) 12. CKL_C / SO is an operation clock supplied to the bus master (CPU) 11 and the bus slave (register) 12.

  GATE_M0 / S1 is a gate control signal supplied to the bus master (DMA) 21 and the bus slave (system memory) 22. CKL_M0 / S1 is an operation clock supplied to the bus master (DMA) 21 and the bus slave (system memory) 22. An example of operation will be described with time t1-t17 added to the clock CLK_A.

  Now, it is assumed that the bus master 11 outputs the request signal REQ_C from time t1 to time t5. The bus arbiter 40 outputs the grant signal GRANT_C from time t3 when, for example, the second clock CLK_A is output from time t1. However, since the request signal is canceled at time t5, the grant signal GRANT_C is also canceled at the same time.

  Further, it is assumed that the bus master 21 outputs the request signal REQ_M0 from time t1 to time t5. The bus arbiter 40 outputs the grant signal GRANT_M0 for the bus slave 22 since the grant signal GRANT_C is canceled at the time t5 when the second clock CLK_A is output from the time t3, for example. The request signal and the grant signal are signals exchanged between each bus master and the bus arbiter 40. The grant signal has a relationship of being canceled at the same time as the corresponding request signal is canceled as described above.

  Next, B_ADDR and B_DATA in FIG. 2 mean addresses and data on the bus 100 (address bus and data bus). When the grant signal is output, the bus master that has obtained the right to use the bus outputs the address of the corresponding bus slave when the second clock CLK_A is output from the time when the grant signal is generated. The data for the bus slave to be output is output.

  In the example of FIG. 2, the bus master 11 outputs and designates an address for the bus slave (register) 12 between time t5 and time t7, and then outputs data between time t7 and time t9. It is timing. However, in this example, since the bus master 21 has obtained the right to use the bus at the time t5, the address designating the corresponding bus slave 22 is output to the address bus at the time t7, and then the data for the bus slave 22 from the time t9. Is output. The address for the bus slave 22 is also output. When the bus master 21 secures the right to use the bus and starts data output, the high-speed operation period starts. The period during which the bus master 11 has the bus use right is a low-speed operation period. When there is no request signal or grant signal, the low-speed operation mode may be set or the operation clock may be stopped.

  FIG. 3 is a flowchart showing the operation of the above apparatus. When there is a request signal from the bus master, the bus master is specified according to a predetermined algorithm, and a grant signal for giving the bus use right to the specified bus master is issued (steps SA1 and SA2). Further, an operation clock is set for the bus master specified by controlling the clock generation circuit 30 and the bus slave corresponding thereto (step SA3).

  In this case, the clock control is not performed immediately after issuing the grant signal, and if there is no master using the bus before (switching timing is t5) or the data phase of the master using the bus before When finished (switching timing is t9), the clock can be switched. If the request signal is canceled, the grant signal is also canceled (step SA4), and the process proceeds to the low speed operation period (step SA5). In this case, after canceling the grant signal, the master does not shift to the low speed operation immediately, but the address phase of the master that can use the bus ends, and the combination of the master and the slave that uses the next bus does not support high speed operation. Next, when there is no master that uses the bus, the low-speed operation period starts.

  With the above circuit configuration, the plurality of clocks output from the clock generation unit are in a synchronized state regardless of the frequency, and the bus clock on the bus is stably synchronized regardless of the frequency. The bus master and bus slave also operate stably in synchronization.

  FIG. 4 shows an SD card controller 400 to which the present invention is applied.

The SD card controller 400 can perform processing such as writing data to an SD (Secure Digital) card, setting a command, erasing data from the SD card, and retrieving data.

  Although referred to as an SD card controller, even a memory card controller is within the scope of the present invention. The memory card controller has a memory card 600 attachment / detachment unit and a connection unit to the personal computer 500. The SD card controller 400 includes a bus 100. A PCI controller 401 is connected to the bus 100.

  Further, a DMA unit 21 as a bus master, a register 12 as a bus slave, and an arbiter 40 that performs bus clock arbitration are connected to the bus 100 of the SD card controller 400.

  The arbiter 40 controls the clock generation circuit 30 and can set an operation clock having an appropriate frequency for the bus master and the bus slave as described with reference to FIG.

  The register 12 and the DMA unit 21 can exchange data with the SD card 600 via the buffer circuit 411 and the interface 412.

  The PCI controller 401 functions as an interface for connecting the SD card controller 400 and the personal computer 500. At this time, the PCI controller 401 operates based on a device driver as PCI standard software, and can access the CPU 502 and the system memory 503 in the personal computer 500 to exchange data. Normally, the CPU 502 and the system memory 503 are not connected to the PCI bus 501 but are related to the PCI bus 501 when accessed by a device driver.

  On the other hand, the PCI controller 401 can operate as a bus master, and can also operate as a bus slave.

  In other words, the PCI controller 401 can request the right to use the bus and obtain the right to use the bus by grant (function as a bus master). At this time, when data is transferred to the register 12, the arbiter 40 controls the clock generation circuit 30 to supply a low-speed clock to the PCI controller 401 and the register 12 (functioning as a bus slave). Thereby, low-speed data communication between the PCI controller 401 and the register 12 is performed.

  Next, the DMA 21 can request the right to use the bus and obtain the right to use the bus by grant (function as a bus master). At this time, when data is transferred to the register 12, the arbiter 40 controls the clock generation circuit 30 to supply a high-speed clock to the PCI controller 401 (functioning as a bus slave) and the DMA 21. As a result, high-speed data communication is performed between the DMA 21 and the PCI controller 401.

  The bus arbiter 40 uses a clock having the highest frequency among a plurality of operation clocks as an operation clock. When there is no request signal, the bus arbiter 40 sets a plurality of operation clocks to a stopped state or the lowest low frequency. When it is determined that there is no request signal, a certain period is monitored, and if there is no request signal even after waiting for a certain period, a low frequency including a stop is set.

  When the above-described processing is executed, the method and apparatus of the present invention can switch between the low-speed and high-frequency bus clocks in accordance with the combination of the bus master and the bus slave. At this time, data and addresses on the bus are switched in synchronism in a safe manner, and troubles such as hang-up are less likely to occur.

  Note that the present invention is not limited to the above-described embodiment as it is, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Further, various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine suitably the component covering different embodiment.

It is a block block diagram which shows the basic composition of this invention. 3 is a timing chart for explaining an operation example of the circuit of FIG. 1. 3 is a flowchart shown for explaining an operation example of the circuit of the present invention. It is a block block diagram which shows the structural example of the apparatus with which this invention was applied.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 ... Bus master (CPU, 12 ... Bus slave (register), 21 ... Bus master (DMA), 22 ... Bus slave (system memory), 30 ... Clock generation circuit, 40. ..Bus arbiter, 100 ... Bus.

Claims (9)

A bus master that operates with an operating clock of at least first and second different frequencies;
A plurality of bus slaves corresponding to the bus masters operating at the different frequencies;
A connection element connecting the bus master and the plurality of bus slaves;
A clock generation circuit that selectively obtains operation clocks of different frequencies;
A bus arbiter that controls the clock generation circuit in response to a bus use right request from the bus master and sets an operation clock frequency adapted to the bus master and the bus slave that have acquired the bus use right; A bus clock control device. 2. The bus clock controller according to claim 1, wherein the bus arbiter uses a clock having the highest frequency among the plurality of operation clocks as an operation clock. 2. The bus clock control device according to claim 1, wherein the bus arbiter stops or switches the plurality of operation clocks to a low-speed frequency state when there is no request signal. 2. The bus clock control apparatus according to claim 1, wherein the operation clocks having different frequencies include a low-frequency operation clock and a high-frequency operation clock. In a memory card controller having a memory card attachment / detachment unit and a connection unit to a personal computer,
A PCI controller that can be driven by operation clocks of multiple frequencies;
A register driven by an operation clock of a first frequency and operating with the PCI controller as a bus master;
A direct memory access unit that is driven by an operation clock of a second frequency and operates with the PCI controller as a bus slave;
A bus clock generation circuit for selectively obtaining operation clocks of the first and second frequencies of the clock tree;
A bus arbiter configured to control the clock generation circuit in response to a bus use right request from the PCI controller or the direct memory access unit, and to set the operation clock of the first or second frequency as a bus clock; And memory card controller. 6. The memory card controller according to claim 5, wherein the memory card is an SD (Secure Digital) card. 6. The memory card controller according to claim 5, wherein the bus arbiter uses a clock having the highest frequency among the plurality of operation clocks as an operation clock. 6. The memory card controller according to claim 5, wherein when there is no request signal, the bus arbiter stops or switches the plurality of operation clocks to a low-speed frequency state. A circuit comprising: a bus master that operates with an operation clock having a different frequency; a plurality of bus slaves corresponding to the bus master that operates with the different frequency; and a connection element that connects between the bus master and the plurality of bus slaves. In contrast, a clock generation circuit for obtaining the operation clock of different frequencies is provided, and a bus clock is controlled by a bus arbiter,
Controlling the clock generation circuit in response to a bus use right request from the bus master;
A bus clock control method, comprising: setting an operation clock frequency adapted to the bus master and the bus slave that have acquired the right to use the bus.

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