CN110008171A - A kind of Bus Clock Rate dynamic switching device of system on chip - Google Patents
A kind of Bus Clock Rate dynamic switching device of system on chip Download PDFInfo
- Publication number
- CN110008171A CN110008171A CN201910164492.0A CN201910164492A CN110008171A CN 110008171 A CN110008171 A CN 110008171A CN 201910164492 A CN201910164492 A CN 201910164492A CN 110008171 A CN110008171 A CN 110008171A
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- bus
- signal
- clock
- bootstrapping
- main equipment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
- G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
Abstract
The present invention relates to a kind of bus clock controlling devices of on-chip system chip, and mainly serving for ensuring the operation of Bus Clock Rate switching at runtime does not influence the correctness of bus transfer more particularly to a kind of Bus Clock Rate dynamic switching device of system on chip.It includes clock control circuit, bootstrapping three component parts of main equipment and bus.Clock control circuit is responsible for sending request signal A, and the frequency error factor of control bus clock signal simultaneously provides clock signal to bus；Bootstrapping main equipment is responsible for sending answer signal B, and bus transfer request can be initiated by bus protocol；Bus works under the control of bus clock signal, can respond the bus transfer request that bootstrapping main equipment issues.The beneficial effect of apparatus of the present invention is: the correctness and integrality of Bus Clock Rate switching at runtime process guarantee bus transfer；Bus Clock Rate dynamic switching device uses hardware realization completely, not will increase software overhead, reduces the influence to system performance.
Description
Technical field
The present invention relates to a kind of Bus Clock Rate dynamic switching devices of system on chip.
Background technique
With the development of integrated circuit technology, the performance and dominant frequency of processor have obtained huge promotion.In system on chip
In chip, on the one hand Bus Clock Rate needs to match with the processor host frequency of high speed, on the other hand also total with variation
Linear load, storage access speed are adapted, this proposes very high requirement to the flexibility of Bus Clock Rate.Wherein when bus
The switching at runtime of clock frequency is a kind of in system operation, the typical operation of real-time adjustment Bus Clock Rate.
In order to realize the switching at runtime of Bus Clock Rate, it is necessary to increase clock control in on-chip system chip design and patrol
Volume, guarantee the correctness of bus transfer during Bus Clock Rate switching at runtime.Traditional Bus Clock Rate dynamic
Handover operation is that the low-power consumption mode of the closing clock based on system is realized.The shortcomings that implementation, mainly increases soft
Part expense, the time used for passing in and out low-power consumption mode is longer, therefore is not suitable for the application scenarios of frequent switching frequency.Except this it
Outside, in bus access piece external equipment, conventional implementation is in order to guarantee that the correctness of bus access, design can become more multiple
It is miscellaneous.
In order to solve problem above, the invention proposes a kind of Bus Clock Rate dynamic switching devices of system on chip.
The interaction that the device passes through handshake between clock control circuit and bus master, it is ensured that the correctness of bus transfer
And integrality, device use hardware realization completely, reduce the influence to system performance.
Summary of the invention
The purpose of the present invention is to provide a kind of Bus Clock Rate dynamic switching devices of system on chip.
To achieve the goals above, the technical scheme adopted by the invention is that:
A kind of Bus Clock Rate dynamic switching device of system on chip, it includes:
Clock control circuit, for sending request signal A to bootstrapping main equipment, the frequency of control bus clock signal is cut
It changes, and provides clock signal to bus；The request signal A is cut for clock control circuit request bus clock signal frequencies
It changes；
Bootstrapping main equipment, for sending answer signal B to clock control circuit, in the control of bootstrapping main equipment clock signal
Lower work initiates bus transfer request by bus protocol；The answer signal B, for main equipment answer bus clock of booting
Signal frequency switching；
Bus is connect with bootstrapping main equipment by bus protocol signal for working under the control of bus clock signal,
The bus transfer request that response bootstrapping main equipment issues.
Preferably, primary complete Bus Clock Rate switching at runtime process, comprising the following steps:
Clock control circuit sends request signal A to bootstrapping main equipment, indicates a Bus Clock Rate switching at runtime mistake
The beginning of journey；
Bootstrapping main equipment continues to complete the bus transfer being carrying out and requests and stop initiating next bus transfer request,
When the bus of the main equipment is idle state, bootstrapping main equipment sends answer signal B to clock control circuit；
Clock control circuit switches the frequency of bus clock signal, and after the completion of switching, clock control circuit is set to bootstrapping master
Preparation sending request signal A；
Bootstrapping main equipment continues to initiate next bus transfer request, and sends answer signal B, table to clock control circuit
Show the end of a Bus Clock Rate switching at runtime process.
Preferably, the Bus Clock Rate switching at runtime process controlled by request signal A and answer signal B, completely by hard
Part is realized.
Preferably, request signal A indicate clock control circuit initiate the request of Bus Clock Rate switching at runtime or when
Clock control circuit completes the frequency error factor of bus clock signal, and implementation includes but is not limited to level, pulse, bit stream
Deng.
Preferably, answer signal B indicate bootstrapping main equipment bus enter idle state wait Bus Clock Rate switching,
Or the end of a Bus Clock Rate switching at runtime process, implementation include but is not limited to level, pulse, bit stream.
Preferably, the concrete form of request signal A and/or answer signal B are one or more signals.
Preferably, when clock control circuit switching Bus Clock Rate, bus clock can be kept to open always, can also first closed
Bus clock is opened after the completion of the to be switched frequency of closed bus clock again.
Preferably, bootstrapping main equipment refer to reset after clock signal control under to bus automatically initiate transmission request set
It is standby, including but not limited to CPU, DSP.
Preferably, bootstrapping main equipment has one or more groups of bus protocol signals；Bus clock is received in bootstrapping main equipment
When the request of frequency dynamic switching, until all bus transfers request of the bootstrapping main equipment is complete and enters idle state
Afterwards, answer signal B is issued to clock control circuit.
Preferably, carry one or more bootstrapping main equipment in bus；It is dynamic that clock control circuit initiates Bus Clock Rate
When the request of state switching, until the bus transfer that all bootstrapping main equipments of the bus carry are initiated requests to be complete and enter
After idle state, clock control circuit is allowed to start to switch Bus Clock Rate.
The beneficial effect of apparatus of the present invention is: 1, Bus Clock Rate switching at runtime process guarantees the correctness of bus transfer
And integrality；2, Bus Clock Rate dynamic switching device uses hardware realization completely, not will increase software overhead；3, with pass through
Traditional approach into low-power consumption mode switching bus time frequency is compared, and can reduce frequency switching operation to system performance
It influences.
Detailed description of the invention
Fig. 1 Bus Clock Rate dynamic switching device structure chart；
A kind of specific implementation flow chart of Fig. 2 Bus Clock Rate switching at runtime process.
Specific embodiment
The present invention will be further explained below with reference to the attached drawings.
According to the Bus Clock Rate dynamic switching device structure chart of system on chip of the present invention shown in Fig. 1, it is by being responsible for
The clock control circuit for switching bus clock signal frequencies, the bootstrapping that bus transfer request can be initiated by bus protocol main are set
Three parts of bus that are standby, can responding bootstrapping main equipment sending request form.Specifically:
Clock control circuit, for sending request signal A to bootstrapping main equipment, the frequency of control bus clock signal is cut
It changes, and provides clock signal to bus.Wherein request signal A is cut for clock control circuit request bus clock signal frequencies
It changes.
Bootstrapping main equipment, for sending answer signal B to clock control circuit, in the control of bootstrapping main equipment clock signal
Lower work initiates bus transfer request by bus protocol.Wherein answer signal B, for main equipment answer bus clock of booting
Signal frequency switching.
Bus is connect with bootstrapping main equipment by bus protocol signal for working under the control of bus clock signal,
The bus transfer request that response bootstrapping main equipment issues.
Wherein, bootstrapping main equipment refer to reset after clock signal control under to bus automatically initiate transmission request set
It is standby, including but not limited to CPU, DSP etc..Request signal A indicates that clock control circuit is initiated a Bus Clock Rate dynamic and cut
Request or clock control circuit is changed to complete the frequency error factor of bus clock signal.Answer signal B indicates the total of bootstrapping main equipment
Line enters idle state and waits Bus Clock Rate switching or the end of a Bus Clock Rate switching at runtime process.Request
The implementation of signal A and answer signal B include but is not limited to level, pulse, bit stream etc., concrete form can be one or
Multibit signal.
Bootstrapping main equipment can have one or more groups of bus protocol signals.Bus Clock Rate is received in bootstrapping main equipment
When the request of switching at runtime, after all bus transfers request of the bootstrapping main equipment is complete and enters idle state,
Just allow to issue answer signal B to clock control circuit.
Bus can carry one or more bootstrapping main equipment.Clock control circuit initiates Bus Clock Rate switching at runtime
When request, until the bus transfer request of all bootstrapping main equipments initiation of the bus carry is complete and enters idle state
Afterwards, just clock control circuit is allowed to switch Bus Clock Rate.
It can be complete by the primary complete Bus Clock Rate switching at runtime process that request signal A and answer signal B is controlled
Entirely by hardware realization.When clock control circuit switches Bus Clock Rate, bus clock can be kept to open always, can also first closed
Bus clock is opened after the completion of bus clock, switching frequency again.
Based on the primary complete Bus Clock Rate switching at runtime process, comprising the following steps:
Clock control circuit sends request signal A to bootstrapping main equipment, indicates a Bus Clock Rate switching at runtime mistake
The beginning of journey；
Bootstrapping main equipment continues to complete the bus transfer being carrying out and requests and stop initiating next bus transfer request,
When the bus of the main equipment is idle state, bootstrapping main equipment sends answer signal B to clock control circuit；
Clock control circuit switches the frequency of bus clock signal, and after the completion of switching, clock control circuit is set to bootstrapping master
Preparation sending request signal A；
Bootstrapping main equipment continues to initiate next bus transfer request, and sends answer signal B, table to clock control circuit
Show the end of a Bus Clock Rate switching at runtime process.
Below as the flow chart of the specific embodiment of the invention of introduction shown in Fig. 2, keep those skilled in the art more clear
Chu understands the present invention.By taking request signal A and answer signal B are realized by a bit level signal respectively as an example, a kind of concrete operations stream
Journey are as follows: 1, clock control circuit request signal A is set to high level；2, bootstrapping main equipment continues to complete the bus being carrying out and passes
Defeated request simultaneously stops initiating next bus transfer request, when the bus of the main equipment being waited to be idle state, main equipment of booting
Answer signal B is set to high level；3, clock control circuit switching bus clock signal frequency, wait it is to be switched after the completion of, when
Request signal A is set to low level by clock control circuit；4, bootstrapping main equipment continues to initiate next bus transfer request, and will answer
It answers signal B and is set to low level.
The present invention guarantees the correctness and integrality of bus transfer by above-mentioned Bus Clock Rate switching at runtime process.And
Bus Clock Rate dynamic switching device uses hardware realization completely, not will increase software overhead, reduces to system performance
It influences.
Above-mentioned embodiment is only a preferred solution of the present invention, so it is not intended to limiting the invention.Have
The those of ordinary skill for closing technical field can also make various changes without departing from the spirit and scope of the present invention
Change and modification.Therefore all mode technical solutions obtained for taking equivalent substitution or equivalent transformation, all fall within guarantor of the invention
It protects in range.
Claims (10)
1. a kind of Bus Clock Rate dynamic switching device of system on chip, it is characterised in that: the Bus Clock Rate is dynamic
State switching device includes:
Clock control circuit is used for bootstrapping main equipment transmission request signal A, the frequency error factor of control bus clock signal, and
Clock signal is provided to bus；The request signal A, for clock control circuit request bus clock signal frequencies switching；
Bootstrapping main equipment, for sending answer signal B to clock control circuit, the work under the control of bootstrapping main equipment clock signal
Make, bus transfer request is initiated by bus protocol；The answer signal B, for main equipment answer bus clock signal of booting
Frequency error factor；
Bus is connect by bus protocol signal with bootstrapping main equipment, is responded for working under the control of bus clock signal
The bus transfer request that main equipment of booting issues.
2. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that primary
Complete Bus Clock Rate switching at runtime process, comprising the following steps:
Clock control circuit sends request signal A to bootstrapping main equipment, indicates a Bus Clock Rate switching at runtime process
Start；
Bootstrapping main equipment continues to complete the bus transfer being carrying out and requests and stop initiating next bus transfer request, the master
When the bus of equipment is idle state, bootstrapping main equipment sends answer signal B to clock control circuit；Clock control circuit switching
The frequency of bus clock signal, after the completion of switching, clock control circuit sends request signal A to bootstrapping main equipment；
Bootstrapping main equipment continues to initiate next bus transfer request, and sends answer signal B to clock control circuit, indicates one
The end of secondary bus clock frequency switching at runtime process.
3. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that by asking
The Bus Clock Rate switching at runtime process for asking signal A and answer signal B to control, completely by hardware realization.
4. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that request
When signal A indicates that clock control circuit initiates a Bus Clock Rate switching at runtime request or clock control circuit to bus
The frequency error factor of clock signal is completed, and implementation includes but is not limited to level, pulse, bit stream.
5. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that response
Signal B indicates that the bus of bootstrapping main equipment enters idle state and waits Bus Clock Rate switching or a Bus Clock Rate
The end of switching at runtime process, implementation include but is not limited to level, pulse, bit stream.
6. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that request
The concrete form of signal A and/or answer signal B are one or more signals.
7. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that clock
When control circuit switches Bus Clock Rate, bus clock can be kept to open always, can also first close the to be switched frequency of bus clock
Bus clock is opened after the completion of rate again.
8. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that bootstrapping
Main equipment refer to reset after clock signal control under to bus automatically initiate transmission request equipment, including but not limited to CPU,
DSP。
9. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that bootstrapping
Main equipment has one or more groups of bus protocol signals；The request of Bus Clock Rate switching at runtime is received in bootstrapping main equipment
When, after all bus transfers request of the bootstrapping main equipment is complete and enters idle state, to clock control circuit
Issue answer signal B.
10. a kind of Bus Clock Rate dynamic switching device of system on chip as described in claim 1, which is characterized in that total
Carry one or more bootstrapping main equipment on line；When clock control circuit initiates the request of Bus Clock Rate switching at runtime, etc.
After the bus transfer request initiated to all bootstrapping main equipments of the bus carry is complete and enters idle state, when permission
Clock control circuit starts to switch Bus Clock Rate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910164492.0A CN110008171B (en) | 2019-03-05 | 2019-03-05 | Bus clock frequency dynamic switching device of system on chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910164492.0A CN110008171B (en) | 2019-03-05 | 2019-03-05 | Bus clock frequency dynamic switching device of system on chip |
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| CN110008171A true CN110008171A (en) | 2019-07-12 |
| CN110008171B CN110008171B (en) | 2021-09-21 |
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| CN201910164492.0A Expired - Fee Related CN110008171B (en) | 2019-03-05 | 2019-03-05 | Bus clock frequency dynamic switching device of system on chip |
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Citations (6)
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| CN1661576A (en) * | 2004-02-25 | 2005-08-31 | 中国科学院计算技术研究所 | Dynamic frequency conversion device of bus in high speed and kermel interface of processor under SOC architecture |
| US7093153B1 (en) * | 2002-10-30 | 2006-08-15 | Advanced Micro Devices, Inc. | Method and apparatus for lowering bus clock frequency in a complex integrated data processing system |
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2019
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Patent Citations (6)
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| US7093153B1 (en) * | 2002-10-30 | 2006-08-15 | Advanced Micro Devices, Inc. | Method and apparatus for lowering bus clock frequency in a complex integrated data processing system |
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| CN1936778A (en) * | 2006-10-27 | 2007-03-28 | 北京中星微电子有限公司 | Method and apparatus for switching-over internal memory clock frequency and system therefor |
| JP2010128793A (en) * | 2008-11-27 | 2010-06-10 | Toshiba Corp | Bus clock control device, control method thereof and memory card controller |
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| CN110008171B (en) | 2021-09-21 |
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