JP2003345455A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To control a clock by using bus right identification information which a bus right arbitration means itself has or to start control so that a function block having a bus right is supplied with a clock of appropriate frequency and low power consumption is realized. <P>SOLUTION: A data processor has a clock control means 3 which controls the clock based on bus master information from the bus arbitration means 2, changes the frequency of the clock based on a bus right request identification signal 21, and selects a function block which supplies the clock based on the bus right request identification signal 21 or selects a function block which changes the frequency of the clock based on the bus right request identification signal 21. In addition, the clock control means 3 has a register for ON/OFF control or has a register for designating a frequency or a function block. <P>COPYRIGHT: (C)2004,JPO

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system in a computer system, and more particularly, to a data processing device provided with clock control means for supplying a clock to each functional block.

[0002]

2. Description of the Related Art Conventionally, in a computer system, a bus system has a plurality of functional blocks connected to a bus, and constitutes a data processing device for transmitting various data via the bus. FIG. 4 is a configuration diagram showing a conventional data processing apparatus, which includes a functional block 11-1n, a bus arbitration unit 2, a clock control unit 3, and a bus 4 for performing data communication between the functional blocks 11-1n. The bus arbitration means 2 receives the bus right request signal 111-1n1 which is asserted when each of the functional blocks 11-1n requests the bus right and negated when the functional block 11-1n withdraws the bus right request. The bus right is given to one functional block. The clock control means 3 controls the supply of a clock to each functional block.
The clock 32 is supplied to each functional block.

[0003] In FIG.
When 1 uses the bus 4, the functional block 11 asserts the bus right request signal 111. When the bus arbitration unit 2 receives the bus right request signal 111 from the function block 11, if another function block has already used the bus 4, the other function block negates the bus right request signal to change the bus right. Until abandonment, the function block 11 is not given a bus right. On the other hand, when no function block has acquired the bus right, the bus arbitration means 2 arbitrates the bus right requests from a plurality of function blocks including the bus right request from the function block 11. Then, the bus right signal for the bus request having the highest priority is asserted, and the other bus right signals are negated. When the priority of the bus right request of the function block 11 is the highest among all the bus right requests,
Asserts the bus right signal 112 and outputs another bus right signal 122.
By negating -1n2, the functional block 11 can obtain the bus right and use the bus 4. When the functional block 11 ends using the bus 4, the functional block 11 negates the bus right request signal 111, thereby relinquishing the bus right.

On the other hand, a clock control means 3 generates a clock 32 from an input clock 31 and supplies it to each functional block. When the clock control means 3 changes the frequency of the clock for the purpose of low power consumption, it is performed by means such as writing a specific value to a specific register.

[0005]

In such a bus system, a technique for changing the clock frequency for the purpose of low power consumption already exists, and data communication is performed between functional blocks via the bus 4. If the clock is stopped or the frequency is changed while the system is in operation, the system becomes unstable. Therefore, there is a technique for releasing the bus right after changing to the clock mode.

However, the change of the clock frequency is
The bus right is released by an external command and by judging a change in the clock mode.

[0007] The present invention has been made in view of the above,
Provided is a data processing device that supplies a clock having an appropriate frequency to a functional block having a bus right and realizes low power consumption by controlling a clock using the bus right identification information of the bus right arbitration means itself. The purpose is to:

[0008]

To achieve the above object, a data processing apparatus according to the present invention includes a bus for performing data communication, a bus right request signal when transmitting data using the bus, and a bus request signal. A plurality of functional blocks for obtaining a right to use a bus by receiving a bus right signal, and receiving a bus right request signal from each of the plurality of functional blocks, arbitrating the one, and arbitrating one of the plurality of functional blocks Clock control means for controlling a clock in accordance with bus master information from said bus arbitration means, in a data processing circuit comprising: a bus arbitration means for giving a bus right signal to said bus; and a clock control means for supplying a clock to each functional block. Means are provided.

According to the present invention, the clock can be directly controlled by using the bus master information from the bus arbitration means as a trigger, and low power consumption can be achieved without external instructions or mode change determination. Can be realized.

In the data processing apparatus according to the next invention, the bus master information from the bus arbitration means to the clock control means is a bus right request identification signal for identifying a functional block requesting the bus right. Clock control means for changing a clock frequency based on a bus right request identification signal is provided.

According to the present invention, the frequency can be changed in a state where the bus right is obtained, and low power consumption can be realized without making an external instruction or judging a mode change.

[0012] In the data processing apparatus according to the next invention, in the above-mentioned invention, the clock control means may turn on / off a function of changing a clock frequency based on a bus right request identification signal.
It is characterized by including a register for controlling OFF.

According to the present invention, ON for changing the frequency
By using a register for controlling / OFF, low power consumption is realized.

In the data processing apparatus according to the next invention, in the above-mentioned invention, the clock control means includes an ON / OFF function for changing the frequency of the clock based on the bus request identification signal.
An external terminal for controlling OFF is provided.

According to the present invention, the frequency is changed to ON.
By using an external terminal for controlling / OFF, low power consumption is realized.

A data processing apparatus according to the next invention is characterized in that, in the above invention, the clock control means includes a register for designating a frequency of a clock to be changed based on the bus right request identification signal.

According to the present invention, low power consumption is realized by providing the register for specifying the clock frequency.

In the data processing apparatus according to the next invention, in the above invention, the bus master information from the bus arbitration means to the clock control means is a bus right request identification signal for identifying a functional block requesting the bus right. Clock control means for selecting a functional block for supplying a clock based on the bus right request identification signal is provided.

According to the present invention, it is possible to select a functional block in a state in which the bus right has been obtained, and it is possible to realize low power consumption without giving an instruction from outside or judging a mode change.

In the data processing apparatus according to the next invention, in the above-mentioned invention, the clock control means includes a register for controlling ON / OFF of a function for selecting a function block to supply a clock based on a bus right request identification signal. It is characterized by having.

According to the present invention, the function block is selected by using the register for controlling ON / OFF.
Low power consumption has been achieved.

A data processing apparatus according to the next invention is characterized in that, in the above invention, the clock control means includes a register for designating a functional block for supplying a clock based on a bus right request identification signal.

According to the present invention, low power consumption is realized by providing a register for designating a functional block.

In the data processing apparatus according to the next invention, in the above invention, the bus master information from the bus arbitration means to the clock control means is a bus right request identification signal for identifying a functional block requesting the bus right. Clock control means for selecting a functional block for changing a clock frequency based on a bus right request identification signal is provided.

According to the present invention, it is possible to select a functional block for changing the clock frequency while obtaining the bus right, and to reduce the power consumption without giving an external instruction or judging a mode change. Can be realized.

In the data processing apparatus according to the next invention, in the above-mentioned invention, the clock control means controls ON / OFF of a function of selecting a function block for changing a clock frequency based on a bus right request identification signal. A register is provided.

According to the present invention, the selection of the functional block for changing the clock frequency uses the register for controlling ON / OFF, thereby realizing low power consumption.

The data processing apparatus according to the next invention is characterized in that, in the above invention, the clock control means includes a register for designating a functional block for changing a clock frequency based on a bus right request identification signal. I do.

According to the present invention, low power consumption is realized by providing a register for designating a functional block for changing a clock frequency.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments according to the present invention will be described below in detail with reference to FIGS. 1 to 3, the same parts as those in FIG. 4 are denoted by the same reference numerals.

Embodiment 1 FIG. 1 is a block diagram showing a configuration of the data processing device according to the first embodiment of the present invention. In FIG. 1, 11-1n is a functional block, 4 is a bus on which the functional block 11-1n performs data communication, 1
11-1n1 is a bus right request signal that is asserted when each of the functional blocks 11-1n requests the bus arbitration means 2 to request the bus right and is negated when the bus right request is withdrawn.
2-1n2 is a bus right signal asserted when the bus arbitration means 2 gives the bus right, 113-1n3 is transmission data sent from each functional block 11-1n, and 2 is a bus from each functional block 11-1n. Right request signal 111-1n
Bus arbitration means for arbitrating a plurality of bus right requests by inputting 1 and asserting one of the bus right signals 112-1n2 to give a bus right to one functional block. The bus arbitration unit 2 outputs to the clock control unit 3 a bus right request identification signal 21 for identifying a functional block that owns the bus right as a result of the adjustment by requesting the bus right. Reference numeral 3 denotes a clock control unit which receives a clock 31 as an input. The clock control unit 3 includes a clock frequency dividing circuit 33 for generating clocks of a plurality of frequencies and a plurality of clocks generated by the clock frequency dividing circuit 33. And a frequency selector 34 for selecting a clock frequency based on the bus request identification signal 21 corresponding to the functional block. Then, a clock of the selected frequency is supplied from the frequency selector 34 to each functional block. In this case, the frequency selector 34 has a register for controlling ON / OFF of the function of changing the clock frequency, or selects a frequency by having a register for specifying the clock frequency.

Next, the operation will be described. When the bus arbitration means 2 receives a bus right request signal from one of the function blocks, if another function block has already used the bus 4, the other function block negates the bus right request signal 111-1n1. Until the bus right is relinquished, no bus right is granted to any of the functional blocks. On the other hand, in a state where no function block has acquired the bus right, the bus arbitration means 2 arbitrates the bus right requests from the plurality of function blocks,
The functional block 11-1n having the highest priority of the bus right request among all the bus right requests can obtain the bus right and use the bus 4.

In this case, the bus arbitration means 2 arbitrates the bus right request from the function block 11-1n, and inputs the arbitrated result as the bus right request identification signal 21 to the frequency selector 34 of the clock control means 3; Frequency selector 34
Selects a clock conforming to the bus right request identification signal 21 and supplies the clock to each functional block.

As described above, according to the first embodiment, the clock control means 3 enables the clock to be selected by the bus request identification signal 21 so that each functional block owns the bus. Sometimes an appropriate frequency clock can be supplied.

Embodiment 2 Next, a second embodiment of the present invention will be described. In the first embodiment described above,
The bus arbitration means 2 controls a frequency selector 34 for selecting a clock frequency based on the bus right request identification signal 21,
Although a clock of an appropriate frequency is supplied to the function block, in the second embodiment, the function block is selected without selecting the frequency.

FIG. 2 is a block diagram showing a data processing device according to the second embodiment of the present invention. In FIG.
In the clock control means 3, reference numeral 35 denotes a block selector for selecting a function block to be supplied with a clock based on a bus right request identification signal 21 for identifying a function block having the bus right. Each of the function blocks 11-1n Are supplied with the corresponding clocks of the clocks 321-32n. In this case, the block selector 35 turns ON / OFF the function of selecting the function block to supply the clock.
Function block is selected, or a register for designating a function block to supply a clock is selected.

Next, the operation will be described. The bus arbitration unit 2 arbitrates a bus right request from the functional block 11-1n, and inputs the arbitrated result as a bus right request identification signal 21 to the block selector 35 of the clock control unit 3, and the block selector 35 Is selected, and a clock is supplied only to the selected function block.

As described above, according to the second embodiment,
By allowing the clock control means 3 to select a functional block to which a clock is supplied by the bus right request identification signal 21, it is necessary to supply a clock when each functional block 11-1n owns the bus right. By supplying a clock only to the functional blocks, power consumption can be reduced.

Embodiment 3 Next, a third embodiment of the present invention will be described. In the first embodiment described above,
The bus arbitration means 2 controls a frequency selector 34 for selecting a clock frequency based on the bus right request identification signal 21,
A clock having an appropriate frequency is supplied to the function block. In the second embodiment, a frequency block is not selected, and a function block is selected. In the third embodiment, the first and second embodiments are combined. Things.

FIG. 3 is a block diagram showing a data processing device according to the third embodiment of the present invention. In FIG.
In the clock control means 3, reference numeral 33 denotes the same clock frequency dividing circuit as in the first embodiment, and reference numeral 36 denotes a frequency / block for selecting a clock having a frequency designated to each functional block based on the bus request identification signal 21. A selector,
Any of the clocks 321 to 32n of the selected frequency is supplied to any of the functional blocks 11-1n. In this case, the frequency / block selector 36 has a register for controlling ON / OFF of a function for selecting a function block for changing the clock frequency, or has a register for specifying a function block for changing the clock frequency. Can select a frequency and a function block.

Next, the operation will be described. The bus arbitration means 2 arbitrates a bus request from the function block 11-1n,
The result of the arbitration is input to the frequency / block selector 36 of the clock control means 3 as the bus right request identification signal 21. The frequency / block selector 36 designates the function block corresponding to the bus right request identification signal 21 and the function block. And the selected clock frequency.

As described above, according to the third embodiment, the clock control means 3 supplies a clock of an appropriate frequency to each functional block to which the clock is supplied by the bus right request identification signal 21, thereby suppressing power consumption. Can be.

[0043]

As described above, according to the present invention, a bus for performing data communication and a bus right request signal and receiving a bus right signal when transmitting data using the bus are used. And a plurality of function blocks for obtaining the right to use the plurality of function blocks, and receives bus request signals from the plurality of function blocks, arbitrates, and provides a bus right signal to one of the plurality of function blocks. In a data processing circuit comprising bus arbitration means and clock control means for supplying a clock to each functional block, a bus control means for controlling a clock based on bus master information from the bus arbitration means is provided. Clock control can be performed directly using this information as a trigger based on the bus master information from the arbitration unit, and instructions from outside and Without decisions over de changes, it is possible to achieve low power consumption.

According to the next invention, the bus master information from the bus arbitration unit to the clock control unit is a bus right request identification signal for identifying a functional block requesting the bus right, and based on the bus right request identification signal. By providing clock control means for changing the clock frequency, the frequency can be changed with the bus right acquired, reducing power consumption without external instructions or mode change judgment. Can be realized.

According to the next invention, the clock control means includes a register for controlling ON / OFF of a function of changing a clock frequency based on a bus right request identification signal. By using a register for controlling / OFF, low power consumption is realized.

According to the next invention, the clock control means has an external terminal for controlling ON / OFF of the function of changing the frequency of the clock based on the bus right request identification signal. By using an external terminal for controlling ON / OFF, low power consumption is realized.

According to the next invention, the clock control means is provided with a register for designating the frequency of the clock to be changed based on the bus right request identification signal, thereby realizing low power consumption.

According to the next invention, the bus master information from the bus arbitration unit to the clock control unit is a bus right request identification signal for identifying a functional block requesting the bus right, and based on the bus right request identification signal. The provision of the clock control means for selecting the functional block that supplies the clock enables the functional block to be selected while obtaining the bus right, thereby reducing power consumption without external instructions or mode change judgment. Electricity can be realized.

According to the next invention, the clock control means includes a register for controlling ON / OFF of a function of selecting a function block to supply a clock based on a bus right request identification signal. Selection is ON
By using a register for controlling / OFF, low power consumption is realized.

According to the next invention, the clock control means is provided with a register for designating a functional block for supplying a clock based on a bus right request identification signal, thereby realizing low power consumption.

According to the next invention, the bus master information from the bus arbitration unit to the clock control unit is a bus right request identification signal for identifying a functional block requesting the bus right, and based on the bus right request identification signal. By providing a clock control means for selecting a functional block for changing the clock frequency, it is possible to select a functional block for changing the clock frequency while obtaining the bus right. Power consumption can be reduced without making a determination.

According to the next invention, the clock control means is provided with a register for controlling ON / OFF of a function of selecting a function block for changing a clock frequency based on a bus right request identification signal. The selection of the function block for changing the frequency of the power supply uses a register for controlling ON / OFF, thereby realizing low power consumption.

According to the next invention, the clock control means is provided with a register for designating a functional block for changing the clock frequency based on the bus right request identification signal, thereby realizing low power consumption.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data processing device according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a data processing device according to a second embodiment of the present invention;

FIG. 3 is a block diagram illustrating a configuration of a data processing device according to a third embodiment of the present invention;

FIG. 4 is a block diagram illustrating a configuration of a data processing device of a conventional example.

[Explanation of symbols]

11-1n functional block, 2 bus arbitration means, 3 clock control means, 4 buses, 21 bus right request identification signal,
33 clock frequency divider, 34 frequency selector, 35
Block selector, 36 Frequency / block selector.

   ────────────────────────────────────────────────── ─── Continuation of front page    F-term (reference) 5B061 BB01                 5B079 AA07 BA12 BA15 BB04 BC01                       DD03

Claims (11)

[Claims] 1. A bus for data communication and a plurality of functional blocks for outputting a bus right request signal and receiving a bus right signal when transmitting data using the bus, thereby obtaining a right to use the bus. Bus arbitration means for receiving a bus right request signal from each of the plurality of functional blocks, arbitrating the bus right request signal to one of the plurality of functional blocks, and providing a clock to each of the functional blocks; A data processing circuit comprising: clock control means for supplying; and clock control means for controlling a clock based on bus master information from the bus arbitration means. 2. The bus master information from the bus arbitration unit to the clock control unit is a bus right request identification signal for identifying a functional block requesting a bus right, and changes a clock frequency based on the bus right request identification signal. 2. The data processing device according to claim 1, further comprising a clock control unit that performs clock control. 3. The clock control means has an ON / OF function of changing a clock frequency based on a bus right request identification signal.
3. The data processing device according to claim 2, further comprising a register for controlling F. 4. The clock control means has an ON / OF function for changing a clock frequency based on a bus right request identification signal.
3. The data processing device according to claim 2, further comprising an external terminal for controlling F. 5. The data processing apparatus according to claim 2, wherein the clock control means includes a register for designating a clock frequency to be changed based on the bus request identification signal. 6. The bus master information from the bus arbitration unit to the clock control unit is a bus right request identification signal for identifying a functional block requesting a bus right, and a function of supplying a clock based on the bus right request identification signal. 2. The data processing device according to claim 1, further comprising clock control means for selecting a block. 7. The clock control means according to claim 6, wherein the clock control means includes a register for controlling ON / OFF of a function for selecting a function block to supply a clock based on the bus right request identification signal. Data processing device. 8. The data processing apparatus according to claim 6, wherein the clock control means includes a register for designating a functional block for supplying a clock based on the bus request identification signal. 9. The bus master information from the bus arbitration unit to the clock control unit is a bus right request identification signal for identifying a functional block requesting a bus right, and changes a clock frequency based on the bus right request identification signal. 2. The data processing apparatus according to claim 1, further comprising clock control means for selecting a functional block to be executed. 10. The apparatus according to claim 9, wherein said clock control means includes a register for controlling ON / OFF of a function of selecting a function block for changing a clock frequency based on a bus right request identification signal. The data processing device according to claim 1. 11. The data processing apparatus according to claim 9, wherein the clock control means includes a register for specifying a functional block for changing a clock frequency based on the bus request identification signal.