JP2010128537A - Sales data processor and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the consumption of an auxiliary power source to be used for the backup of data in the case of interrupting a main power source in a sales data processor. <P>SOLUTION: In an ECR, a CPU (Central Processing Unit) 10 executes the deletion processing of data stored in a memory for hibernation 14 in a spare time in which there is not any other processing to be executed, and when power supply from an AC power source 31 is interrupted, executes the deletion processing of undeleted residual data stored in the memory for hibernation 14, and saves data stored in the main memory 13 into the memory for hibernation 14 by feeding from an auxiliary power source. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a sales data processing apparatus and a program.

  Conventionally, in sales data processing devices such as ECR (electronic registers), data indicating the operating state of the system when the main power supply is shut down is stored in a volatile memory backed up by a battery, which can be used mainly when a power failure occurs. Even when the power is cut off, it can be started immediately in the operating state before the power is cut off. In recent years, however, sales data processing devices have become more sophisticated, and the memory has also increased in capacity. Therefore, a large-capacity backup battery is required in case the main power supply is shut off for a long time due to a summer holiday of the store.

For example, Patent Document 1 describes a product information terminal in which only a central processing unit and a volatile memory are backed up by a battery and a peripheral device with high power consumption is not backed up when a commercial power supply is interrupted or a power failure occurs. Yes.
JP-A-5-11893

  However, in the technology of Patent Document 1, although the capacity of the battery at the time of a momentary interruption of a commercial power source that is a main power source or a power failure can be reduced, A large capacity battery is required.

  On the other hand, when the main power is shut off, it is conceivable to save the data in the volatile memory to the nonvolatile storage means by supplying power from the auxiliary power supply. Since the saved data remains, the data stored in the nonvolatile storage means must first be erased before the data in the volatile memory is saved. For this reason, it takes time until the operation is completely stopped after the main power supply is shut off, and the auxiliary power supply is greatly consumed.

  An object of the present invention is to reduce the consumption of an auxiliary power source used for data backup when a main power source is shut down in a sales data processing apparatus.

In order to solve the above-mentioned problem, the sales data processing device of the invention described in claim 1
Volatile storage means for storing data by power supply from the main power supply;
Nonvolatile storage means for saving data stored in the volatile storage means when the main power supply is shut off;
The data stored in the nonvolatile storage means is erased during the processing free time, and when the main power supply is shut off, the data stored in the nonvolatile storage means is not supplied with power from the auxiliary power supply. Control means for executing erasure processing of residual data for erasure and for saving data stored in the volatile storage means to the nonvolatile storage means;
Is provided.

The invention according to claim 2 is the invention according to claim 1,
A plurality of the nonvolatile storage means;
The control unit distributes and stores data stored in the volatile storage unit to the plurality of nonvolatile storage units.

The invention according to claim 3 is the invention according to claim 1 or 2,
Comprising a switching means for switching between supply and interruption of power from the auxiliary power supply,
The control means causes the switching means to supply power to the auxiliary power supply when the main power is cut off, and causes the switching means to cut off the auxiliary power supply after data saving to the nonvolatile storage means is completed. .

The program of the invention described in claim 4 is:
A sales data processing apparatus comprising: volatile storage means for storing data by power supply from a main power supply; and nonvolatile storage means for saving data stored in the volatile storage means when the main power supply is shut off The computer used for
The data stored in the nonvolatile storage means is erased during the processing free time, and when the main power supply is shut off, the data stored in the nonvolatile storage means is not supplied with power from the auxiliary power supply. Control means for executing erasure processing of residual data for erasure and for saving data stored in the volatile storage means to the nonvolatile storage means;
To function as.

  According to the present invention, in the sales data processing apparatus, it is possible to reduce the consumption of the auxiliary power source used for data backup when the main power source is shut off.

(Embodiment 1)
First, Embodiment 1 of the present invention will be described.
FIG. 1 shows a functional configuration example of the ECR 1 in the first embodiment.
ECR1 is provided in the store, and product registration processing (transaction date and time, product name, number of sales of products, sales data such as sales amount, registration processing of person in charge, etc.), inspection processing, and settlement based on operator operations This is a sales data processing device that performs processing, total sales in a store, and the like. As ECR1, for example, an electronic register or the like is applicable.

  As shown in FIG. 1, the ECR 1 includes a CPU 10, an RTC 11, a program storage memory 12, a main memory 13, a hibernation memory 14, a main display device 151, a sub display device 152, an LED 16, and a printing device. 17, an input device 18, a storage I / F 19, and a communication unit 20, and each unit is configured to be connected via a bus 21.

A CPU (Central Processing Unit) 10 is control means for centrally controlling each part of the ECR 1. The CPU 10 expands various programs stored in the program storage memory 12 in the main memory 13 and executes control of the entire ECR 1 and various processes in cooperation with the programs expanded in the main memory 13.

  For example, when a signal for notifying AC power supply is input from the AC power supply state monitoring circuit 34 (see FIG. 3), the CPU 10 stores the start processing program and the end processing program stored in the program storage memory 12 into the main memory 13. The startup process / end process work area 131 (see FIG. 2) is read and the startup process described later is executed in cooperation with the read startup process program.

  When the ECR 1 is activated by the activation process, the CPU 10 executes an ECR control process, which will be described later, in cooperation with an ECR control program stored in the main memory 13, and controls each part of the ECR 1. Specifically, when there is an input from the input device 18, the CPU 10 activates a processing program corresponding to the input, and performs a product registration process, an inspection process, a checkout process, an in-store sales aggregation process, and the like. When there is no input from the input device 18, that is, when there is no other process to be executed, a write area pre-erasing process described later is executed. Note that “another process to be executed” does not include an “ECR control process” executed by determining whether there is a process to be executed.

  Further, when a signal for notifying AC power supply interruption is input from the AC power supply state monitoring circuit 34 during the operation, the CPU 10 performs a suspend process (first process) in cooperation with the termination process program stored in the main memory 13. Ending process) and a hibernation process (second saving process) are executed.

  Here, in the present embodiment, the suspend process refers to volatile data (program counter (PC), stack pointer (SP), register, system data, etc.) indicating the system operation state of the CPU 10 when the AC power supply 31 is shut off. This is a process of saving to the main memory 13. The hibernation process is a process of saving data indicating the system operation state stored in the main memory 13 to the nonvolatile hibernation memory 14.

  When a signal for notifying the AC power supply is input from the AC power state monitoring circuit 34 during the hibernation process, the CPU 10 interrupts the hibernation process, executes the start process, and saves the system operation state saved in the main memory 13. The system is returned to the state before the AC power supply is cut off based on the data indicating.

An RTC (Real Time Clock) 11 has a built-in clock circuit, clocks the current time and the current date, and outputs them to the CPU 10. The RTC 11 includes an RTC backup power supply 111 (see FIG. 3), and can operate even when no power is supplied from either the AC power supply 31 or the backup power supply 32.

  The program storage memory 12 is configured by a nonvolatile ROM (Read Only Memory) or the like, and as shown in FIG. 2, various programs that can be executed by the ECR1 and unique data of the ECR1 (for example, the MAC address of the ECR1, touch panel calibration) Data).

The main memory 13 is volatile storage means for storing various programs executed by the CPU 10 and various data related to these programs.
As shown in FIG. 2, the main memory 13 has a work area 131 for start processing / end processing, a suspend area 132, a copy area 133, a system data area 134, a setting data area 135, and a user data area 136. .

The start process / end process work area 131 stores a start process program and an end process program (including subroutine processing) read from the program storage memory 12 by the CPU 10 when the AC power is turned on, and these programs operate. It is a work area to do. The work area 131 for start process / end process has an erase block number area 131a. The erase block number area 131a is an area for storing the block numbers (1 to n) of blocks that are finally erased in the hibernation memory 14. The block indicates a data unit in which data can be written and erased at once in the hibernation memory 14. “0” indicates that the hibernation memory 14 is in an unerased state. The suspend area 132 is an area for saving data indicating the system operation state of the CPU 10 (program counter (PC), stack pointer (SP), register, system data, etc.) in the suspend process.
The copy area 133 is an area for writing a copy of the program stored in the program storage memory 12.
The system data area 134 is an area for storing stack, variables, and operating system (OS) system data.
The setting data area 135 is an area for storing various setting data related to peripheral devices (main display device 151, sub display device 152, printing device 17, input device 18, etc.) set via the input device 18.
The user data area 136 is an area for storing user data such as sales data input via the input device 18, display data being displayed on the main display device 151, and print data to be printed on the printing device 17.

The hibernation memory 14 is constituted by a nonvolatile memory such as a flash memory, and is a nonvolatile storage means for saving data stored in the main memory 13 when the AC power supply 31 is shut off. The hibernation memory 14 can write data in n blocks.
Further, in the present embodiment, the hibernation memory 14 is a hibernation memory 14a for storing the upper bit of the data instructed by the CPU 10, and a hibernation for storing the lower bit of the data instructed by the CPU 10. The memory 14b is provided. This is to improve the data writing speed and erasing speed in the hibernation process.

  As shown in FIG. 2, the hibernation memory 14 includes a header area 141, a backup area 142, and a checksum storage area 143. The header area 141 is an area having a hibernation completion flag area 141a for setting a hibernation completion flag indicating that the hibernation process has been completed. The backup area 142 is an area for saving data in an area other than the start / end process work area 131 of the main memory 13 in the hibernation process. The checksum storage area 143 is an area for writing the checksum calculated in the hibernation process.

  The main display device 151 and the sub display device 152 are configured by an LCD (Liquid Crystal Display), an organic EL (Electro-Luminescence) display, or the like, and display various screens according to instructions of a display signal input from the CPU 10. The main display device 151 is a display device provided toward the operator side, and the sub display device 152 is a display device provided toward the customer side.

  An LED (Light Emitting Diode) 16 is driven in response to an instruction signal input from the CPU 10 and is lit and blinks.

  The printing device 17 is, for example, a thermal printer (thermal printer), and has receipt and journal roll paper (thermal paper), and according to an instruction signal input from the CPU 10, the amount of money for each roll paper, etc. Print out the data.

  The input device 18 includes a cash register keyboard having power keys, cursor keys, characters, numeric input keys, and various function keys such as an INIT key and an FC key. Output to. The input device 18 includes a touch panel provided on the screen of the main display device 151. The touch panel is installed so as to cover the upper surface of the main display device 151, detects a desired input position pressed by an operation using an operator's finger or the like, and outputs a detection signal to the CPU 10. The input device 18 includes a barcode reader, a barcode scanner, or the like that reads a barcode provided on a product.

  The storage I / F 19 can be connected to an external storage 19a such as a CF (Compact Flash) card or an SD card (Secure Digital Card), and inputs / outputs data to / from the external storage 19a.

  The communication unit 20 includes a LAN (Local Area Network) adapter, a router, and the like, and performs data transmission / reception with an external device such as the server 100 via a communication network such as a LAN or the Internet.

FIG. 3 shows a configuration example of a main part of the power supply system in ECR1.
3 is connected to an AC power source (main power source) 31 and a backup power source (rechargeable battery) 32 as an auxiliary power source via a switch 35. The power source generation circuit 33 converts AC (alternating current) power source power input from the AC power source 31 into DC (direct current) power source power and supplies it to each unit shown in FIG. The power supply generation circuit 33 supplies the power supply power input from the backup power supply 32 via the switch 35 to the CPU 10, RTC 11, program storage memory 12, main memory 13, and hibernation memories 14 a and 14 b and the LED 16.
The AC power supply state monitoring circuit 34 is a power supply monitoring unit that monitors the power supply state of the AC power supply 31. While power is supplied from the AC power supply 31, a signal (HIGH signal) for notifying the supply of AC power is sent to the CPU 10. While the power is output from the AC power supply 31, a signal (LOW signal) for notifying the AC power supply cutoff is output to the CPU 10.
The switch 35 is switching means for switching ON / OFF (power supply / shutdown) of the backup power supply 32 based on a backup power ON / OFF switch switching control signal from the CPU 10.

  As described above, when the power supply from the AC power supply 31 is in the supply state, the power supply generation circuit 33 supplies the power supply from the AC power supply 31 to each part of the ECR1. When the AC power supply 31 is shut off, the power from the backup power supply 32 is supplied only to the CPU 10, RTC 11, program storage memory 12, main memory 13, hibernation memories 14 a and 14 b, and LED 16 based on the control from the CPU 10. The With this configuration, it is possible to minimize the consumption of the backup power supply 32. Note that the power supply is held in a circuit for a certain time T after the AC power supply 31 is cut off. Within this predetermined time, the CPU 10 switches on the backup power source 32 and maintains the CPU operating power source and the memory operating power source.

  Next, main operations of the ECR 1 in the first embodiment will be described in detail with reference to flowcharts. In the first embodiment, an example in which various processes are executed in a single task will be described.

  First, an ECR control process executed by the CPU 10 after the activation of the ECR 1 will be described. FIG. 4 shows a flowchart of the ECR control process. The ECR control processing is realized by software processing in cooperation with the CPU 10 and the ECR control program.

  First, 0 is set in the erase block number area 131a of the work area 131 for start process / end process (step S1).

  Next, it is determined whether or not an input has been made from the input device 18 (step S2). If it is determined that no input has been made from the input device 18 (step S2; NO), a write area pre-erasing process is executed. (Step S3).

  FIG. 5 shows the write area pre-erasing process executed by the CPU 10 in step S3. The writing area pre-erasing process is executed in cooperation with the CPU 10 and the writing area pre-erasing process program.

  Here, the write area pre-erasing process is a process of erasing data stored in the hibernation memories 14a and 14b. As described above, the data stored in the main memory 13 is saved (written) in the hibernation memories 14a and 14b when the AC power supply 31 is shut off. This data saving is performed by supplying power from the backup power source 32 in an end process to be described later. However, before writing data to the hibernation memories 14a and 14b, it is necessary to first erase the data written at the time of the previous AC interruption from the hibernation memories 14a and 14b. If this process is all performed in the end process, it takes time until the operation is completely stopped after the AC power supply 31 is shut off, and the backup power supply 32 is consumed. Therefore, the AC power supply 31 is executed by executing the write area pre-erasing process in “processing idle time” when there is no other process to be executed in the CPU 10, that is, the product registration process or other process is not requested or executed. The time required for erasing data from the hibernation memories 14a and 14b at the time of interruption is reduced, and the consumption of the backup power source 32 is reduced. In other words, in this embodiment, the “processing idle time” refers to a time during which the CPU 10 does not request or execute a product registration process or other processes.

  In the write area pre-erasure process, first, the number stored in the erase block number area 131a of the main memory 13 is acquired (step S101). Next, it is determined whether or not the acquired number is the last block number n of the hibernation memories 14a and 14b (step S102).

  If it is determined that the acquired number is not the final block number n (step S102; NO), the hibernation memories 14a and 14b are instructed to erase the data of the block having the number next to the acquired number (step S103). ). Then, the process waits for a block erase completion notification from the hibernation memories 14a and 14b. In the hibernation memories 14a and 14b, when the data erase for one block is completed, the CPU 10 is notified of the completion of the block erase.

  When it is notified from the hibernation memories 14a and 14b that data erasure for one block has been completed (step S104; YES), the block number of the block from which data has been erased is written into the erase block number area 131a (step S105). ), The process returns to step S2 of FIG.

  On the other hand, if it is determined in step S102 that the acquired number is the final block number n (step S102; YES), the write area pre-erasing process is terminated, and the process returns to step S2 in FIG.

  If it is determined in step S2 of FIG. 4 that input has been made from the input device 18 (step S2; YES), it is determined whether or not the input is an instruction to register a product (step S4). If it is determined that the input is a product registration instruction (step S4; YES), a product registration process is executed (step S5). The product registration process is a process for registering the date and time when the product was traded, the product name, the sales volume of the product, the sales data such as the sales amount, the person in charge, etc. in the user data area 136. Then, the product name, the number of sales (purchase), the amount of sales (purchase), the deposit amount, the return amount, etc. are printed on the receipt by the printing device 17 (step S6), and the process proceeds to step S8.

  If it is determined that the input from the input device 18 is not a product registration instruction (step S4; NO), another process corresponding to the input is executed (step S7), and the process proceeds to step S8.

  In step S <b> 8, the power state of the AC power supply 31 is determined based on the notification signal input from the AC power supply monitoring circuit 34. If it is determined that the AC power supply 31 is in the supply state (step S8; NO), the process returns to step S2. If it is determined that the AC power supply 31 is in a cut-off state (step S8; YES), an end process is executed (step S9), and the ECR control process ends.

  FIG. 6 shows a flowchart of the end process executed by the CPU 10 in step S9 of FIG. This processing is executed in cooperation with the CPU 10 and the end processing program.

  First, a suspend process (first save process) is executed, and the stack pointer, program counter, register, system data, etc. stored in the CPU 10 are saved in the suspend area 132 of the main memory 13 (step S201).

  Next, the backup power supply 32 is switched ON by switching the switch 35 ON by the backup power ON / OFF switch switching control signal (step S202).

  Next, hibernation processing (second saving processing) is executed, and data in an area other than the activation / termination processing work area 131 in the main memory 13 is saved (backed up) in the hibernation memory 14 (step S203). When a signal for notifying the AC power supply is input by the AC power supply monitoring circuit 34 during the execution of the hibernation process, the process is interrupted by the CPU 10 and the startup process shown in FIGS. 11a to 11b is executed.

  FIG. 7 shows a flowchart of the hibernation process executed by the CPU 10 in step S203 of FIG. This processing is realized by software processing by cooperation between the CPU 10 and the hibernation processing program.

In the hibernation process, first, the LED 16 starts blinking (step S301). Next, a write area erasing process is executed (step S302).
FIG. 8 shows a flowchart of the write area erasing process.
As shown in FIG. 8, in the write area erase process, first, the number stored in the erase block number area 131a is acquired (step S1000). Next, it is determined whether or not the acquired number is the last block number n of the hibernation memories 14a and 14b (step S1001). If it is determined that the acquired number is the final block number n (step S1001; YES), the write area erasing process is terminated, and the process proceeds to step S303 in FIG.

  If it is determined that the acquired number is not the final block number n (step S1001; NO), data deletion of the next numbered block is instructed to the hibernation memories 14a and 14b (step S1002).

  Next, the signal input from the AC power supply state monitoring circuit 34 is monitored to determine the power supply state of the AC power supply 31 (step S1003). If it is determined that the AC power supply 31 is in the cut-off state (step S1003; AC power supply cut-off state), it is determined whether or not erasure of one block is completed in the hibernation memories 14a and 14b. Here, in the hibernation memories 14a and 14b, when the data erase for one block is completed, the CPU 10 is notified of the completion of the block erase. If it is determined that erasure of one block has not been completed (step S1004; NO), the process returns to step S1003.

  If it is determined that the erasure of one block has been completed (step S1004; YES), it is determined whether or not the erasure of all areas of the hibernation memories 14a and 14b has been completed, and if it is determined that the erasure has not been completed ( In step S1005; NO), the process returns to step S1002, and erasure is performed for one block of the next number. If it is determined that erasure of all areas of the hibernation memories 14a and 14b has been completed (step S1005; YES), the write area erasure process is terminated, and the process proceeds to step S303 in FIG.

  On the other hand, when it is determined in step S1003 that the AC power supply 31 is in the supply state (step S1003; AC power supply state), the backup power supply 32 is switched off by the switch 35 (step S1006), and this process is interrupted. Then, the process proceeds to the activation process (hibernation interruption restart) shown in FIGS. 11a to 11b.

In step S303 in FIG. 7, a writing process is executed.
FIG. 9 shows a flowchart of the writing process.
As shown in FIG. 9, in the writing process, first, data to be saved, that is, data stored in an area other than the start / end process work area 131 of the main memory 13 is stored in the hibernation memories 14a and 14b. Are transferred one block at a time, and data writing for one block is instructed (step S2001). One block of data is transferred to the hibernation memory 14a (for example, upper 4 bits for 8 bit data), and the lower bit of data (for example, lower 4 bits for 8 bit data) is transferred to the hibernation memory 14b. ) Is transferred for one block.

  Next, the signal input from the AC power supply state monitoring circuit 34 is monitored, and the power supply state of the AC power supply 31 is determined (step S2002). When it is determined that the AC power supply 31 is in the cut-off state (step S2002; AC power supply cut-off state), it is determined whether or not writing of one block is completed in the hibernation memories 14a and 14b (step S2003). Here, in the hibernation memories 14a and 14b, when the data writing for one block is completed, the CPU 10 is notified of the completion of the block writing. If it is determined that writing of one block has not been completed (step S2003; NO), the process returns to step S2002.

  If it is determined that writing of one block is completed (step S2003; YES), it is determined whether writing of data in all areas other than the activation / end processing work area 131 of the main memory 13 is completed, If it is determined that it has not been completed (step S2004; NO), the process returns to step S2001, and writing for the next block is executed. If it is determined that the writing of data in all the areas other than the work area 131 for start processing / end processing in the main memory 13 is completed (step S2004; YES), the process proceeds to step S304 in FIG. The data written to the hibernation memories 14a and 14b by the above writing process is called backup data.

  On the other hand, when it is determined in step S2002 that the AC power supply 31 is in the supply state (step S2002; AC power supply state), the backup power supply 32 is turned off by the switch 35 (step S2005), and this process is interrupted. Then, the process proceeds to the activation process (hibernation interruption restart) shown in FIGS. 11a to 11b.

In step S304 of FIG. 7, a write content guarantee process is executed.
The written content guarantee process is a process for confirming the consistency between the data to be saved in the main memory 13 and the data saved in the hibernation memory 14.

FIG. 10 shows a flowchart of the write content guarantee process.
As shown in FIG. 10, in the written content guarantee processing, first, the data to be saved to the hibernation memories 14a and 14b stored in the main memory 13, specifically, for the start processing / end processing A verification process (error check) is performed on the data written in the area other than the work area 131 and the data saved in the hibernation memories 14a and 14b (step S3001). If there is an error in the verify process, it is preferable to re-execute the hibernation process.

  Next, a checksum (total value) of data to be saved on the main memory 13 is calculated (step S3002), and the calculated checksum is written to the checksum storage area 143 of the hibernation memories 14a and 14b. (Step S3003). The hibernation completion flag ON is set in the hibernation completion flag area 141a of the hibernation memories 14a and 14b (step S3004), and the process proceeds to step S305 in FIG.

  In step S305 in FIG. 7, the blinking of the LED 16 is stopped (step S305), the hibernation process ends, and the process proceeds to step S204 in FIG.

  In step S204 of FIG. 6, the backup power source 32 is switched off by the switch 35, and the end process ends.

  After the backup power supply 32 is switched off, when the AC power supply 31 is switched from the shut-off state to the supply state, the CPU 10 starts the start processing program and the end processing program in the program storage memory 12 for the start processing and end processing in the main memory 13. Read to work area 131. And the starting process shown to FIG. 11 a-FIG. 11 b is performed.

  11a to 11b show a flowchart of the activation process. This processing is realized by software processing through cooperation between the CPU 10 and the activation processing program. Here, the starting process is started from the position of “reset start” shown in FIGS. 11a to 11b. When the hibernation process is interrupted, the hibernation process program moves to the position of “hibernation interruption restart” shown in FIG. 11a. Since the shift is instructed, the processing is started from the position of “hibernation interruption restart”.

When the process is started from “reset start”, first, a system initialization process is executed (step S10). The system initialization process is a process for the CPU 10 to recognize a system environment to be used and establish a system. For example, a process in which the CPU 10 recognizes what kind of memory is connected can be cited.
Next, start information indicating a reset start is set in the work area 131 for start processing / end processing of the main memory 13 (step S11), and the process proceeds to step S14.

When the process is started from “hibernation interruption restart”, a hibernation system initialization process is first executed (step S12). When the hibernation process is interrupted and the startup process is started, the CPU 10 is operating, and therefore it is not necessary to perform all the system initialization processes. Therefore, in step S12, for example, a part of initialization processing such as initialization of cache information in the CPU 10 is performed.
Next, start information indicating that the hibernation interruption restart is set in the work area 131 for start processing / end processing of the main memory 13 (step S13), and the processing proceeds to step S14.

  In step S14, drivers for peripheral devices such as the main display device 151, the sub display device 152, the printing device 17, and the input device 18 are initialized (step S14).

  Next, it is determined whether or not the INIT key of the input device 18 has been pressed (step S15). Here, the INIT key (initial key) is a key used by the dealer when the ECR 1 is installed, and data in an area other than the start / end processing work area 131 on the main memory 13, that is, setting data, This is a key for instructing to initialize all data including user data. After the power key of the input device 18 is turned off, the INIT key becomes valid when the power key is switched on while pressing the INIT key. That is, at the timing when the INIT key is pressed, in most cases, the restart occurs after the hibernation process is interrupted.

  If the INIT key has been pressed (step S15; YES), the process proceeds to step S35 in FIG. 11b, and a check is made to see if there is an error in the program storage memory 12 program. If the check result is OK (step S35; OK), the program in the program storage memory 12 is copied to the copy area 133 of the main memory 13 (step S36), and ECR1 is started in the INIT state (step S37). The process ends. Activation in the INIT state means that data in the area other than the activation / end process work area 131 from the main memory 13, that is, data in the suspend area 132, the system data area 134, the setting data area 135, and the user data area 136. Means that it will be activated after it is erased. After startup, the ECR control process shown in FIG. 4 is executed. When the check result is NG (step S35; NG), a system error message indicating that a system error has occurred, for example, a character string “system error” is displayed on the main display device 151 (step S38). finish.

  If the INIT key has not been pressed (step S15; NO), it is determined whether or not the FC key has been pressed (step S16). Here, the FC key (flag clear key) is a key for instructing to leave the setting data among the data other than the work area 131 for start processing / end processing on the main memory 13 to initialize. After the power key of the input device 18 is turned off, when the power key is switched on while pressing the FC key, the FC key becomes valid. That is, in most cases, the timing at which the FC key is pressed is a restart after the hibernation process is interrupted. If the FC key has not been pressed (step S16; NO), the process proceeds to step S18. If the FC key has been pressed (step S16; YES), a flag indicating that the FC key has been detected is set in the work area 131 for start processing / end processing on the main memory 13 (step S17), and the processing proceeds to step S18. Transition.

  In step S18, it is determined whether or not the restart is after the hibernation process is interrupted. Specifically, when the start information set in the work area 131 for start processing / end processing is referred to and the set start information is information indicating that the hibernation interruption restart is performed, the hibernation interruption restart is performed. It is judged that. If the set start information is information indicating a reset start, it is determined that the hibernation interrupted restart is not performed. If it is determined that the restart is after the hibernation process is interrupted (step S18; YES), the process proceeds to step S23 in FIG. 11b. That is, the processes in steps S19 to S22 are skipped. In the case of restart after interruption of the hibernation process, the data on the main memory 13 before the AC power supply 31 is cut off remains in the main memory 13, so that it is not necessary to restore the data from the hibernation memory 14.

  If it is determined that the restart is not after the hibernation process is interrupted (step S18; NO), the hibernation completion flag area 141a of the hibernation memory 14 is referred to. If the hibernation completion flag is set to ON (step S19; YES), checksum verification is performed (step S20). That is, it is verified whether or not the checksum stored in the checksum storage area 143 matches the total value of the data stored in the backup area 142. If the checksum verification result is OK (step S20; OK), the backup data stored in the backup area 142 of the hibernation memory 14 is written back to the main memory 13 (step S21).

  Next, it is checked whether or not there is an error in the program written back to the main memory 13 (step S22). If the check result is OK (step S22; OK), it is determined whether or not the FC key has been detected (step S23 in FIG. 11b). If it is determined that the FC key has not been detected (step S23; NO), the program counter, stack pointer, register, system data, etc. on the suspend area 132 are written back to the CPU 10 (step S24). Further, the peripheral device is returned to the state before the AC power supply is cut off (step S25). For example, the display data included in the user data in the main memory 13 is transmitted to the main display device 151, and the display state before the AC power cut-off is restored. Then, the system is restored in a state before the AC power supply is shut off (step S26), and this process ends.

  On the other hand, if it is determined that the FC key has been detected (step S23; YES), the process proceeds to step S27 in FIG. 11b, and a check is made as to whether there is an error in the program in the program storage memory 12. If the check result is OK (step S27; OK), the program in the program storage memory 12 is copied to the copy area 133 of the main memory 13 (step S28), and ECR1 is activated in the FC state (step S29). The process ends. Activation in the FC state means activation after data in the suspend area 132, the system data area 134, and the user data area 136 of the main memory 13 are erased. After startup, the ECR control process shown in FIG. 4 is executed. If the check result is NG (step S27; NG), a system error message indicating that a system error has occurred, for example, a character string “system error” is displayed on the main display device 151 (step S30). finish.

  On the other hand, if it is determined in step S19 that the hibernation completion flag is not ON (step S19; NO), if it is determined in step S20 that checksum verification is NG (step S20; NG), or step S22. If the result of the program check in the main memory 13 is NG (step S22; NG), the process proceeds to step S31 in FIG. 11b to check whether there is an error in the program in the program storage memory 12. If the check result is OK (step S31; OK), the program in the program storage memory 12 is copied to the copy area 133 of the main memory 13 (step S32), and ECR1 is activated in a backup error state (step S33). This process ends. Starting in the backup error state means that a message such as “A backup error has occurred” is displayed on the main display device 151, and data in an area other than the work area 131 for start processing / end processing from the main memory 13, that is, This means that after the data in the suspend area 132, the system data area 134, the setting data area 135, and the user data area 136 are deleted, the data is activated. After startup, the ECR control process shown in FIG. 4 is executed. When the check result of the program is NG (step S31; NG), a system error message indicating that a system error has occurred, for example, a character string “system error” is displayed on the main display device 151 (step S34). The process ends.

  FIG. 12 shows screen display examples of the main display device 151 before the AC power supply 31 is turned off and the main display device 151 after the AC power supply 31 is supplied with power. FIG. 12 shows a case where the AC power supply 31 is interrupted due to a power failure or the like during the product registration process. As described above, in the termination process, data indicating the operating state of the system such as the program counter, stack pointer, register, and system data of the CPU 10 is saved in the main memory 13 and further stored in the nonvolatile memory before the backup power source 32 is turned off. It is saved in a certain hibernation memory 14. When the AC power supply 31 is turned on again, the program counter, stack pointer, register, system data, etc. are read out from the main memory 13 (or the hibernation memory 14) to the CPU 10. Therefore, the execution position of the suspended product registration processing program can be returned to the state before the AC power supply is cut off, and the same screen as before the AC power supply is cut off is displayed on the main display device 151 as shown in FIG. . The user can continue to execute the merchandise registration process without redoing the registration performed before the AC power is shut off.

  In addition, since the data on the main memory 13 is saved in the hibernation memory 14 which is a nonvolatile memory before the backup power supply 32 is turned off, the power supply is turned on after long-term AC power supply cut-off without mounting a large-capacity backup power supply. It becomes possible to return the system to the state before the shutdown.

  Since the data saved in the hibernation memory 14 is erased in advance by the write area pre-erasing process in the idle time when there is no other processing to be executed in the CPU 10, power is supplied from the backup power source 32 when the AC power source 31 is shut off. Therefore, it is possible to reduce the time required for erasing data from the hibernation memories 14a and 14b in the hibernation process executed in response to the above. As a result, the consumption of the backup power source 32 can be reduced.

  Further, since the backup power supply 32 is switched off except when the hibernation process is executed, it is possible to minimize the consumption of the backup power supply 32.

  Further, since a plurality of hibernation memories 14 are provided and data writing and erasing are performed in parallel in the plurality of hibernation memories 14, the data writing speed and erasing speed to the hibernation memory 14 can be improved. As a result, the consumption of the backup power source 32 can be reduced.

  Further, the state of the main memory 13 at the time of AC power interruption is maintained until the hibernation process is completed. During the hibernation process, the power state of the AC power supply 31 is monitored by the CPU 10 and the AC power supply 31 is in the supply state. In such a case, the hibernation process is interrupted and the process proceeds to the start-up process, and data indicating the system operation state stored in the main memory 13 is written back to the CPU 10 so that the operation is returned to the state before the AC power supply is shut off. Is called. Specifically, the hibernation process includes a write area erasure process, a write process, and a write content guarantee process. The CPU 10 uses the AC power supply during data erasure and writing for each block in the hibernation memory 14. When the state is monitored and the AC power supply 31 is in the supply state, control is performed to interrupt the hibernation process and shift to the hibernation interruption restart position of the activation process. Therefore, when the AC power supply 31 is in a supply state during the hibernation process, it is possible to immediately return to the system state before the AC power supply cut-off without waiting for the completion of the hibernation process.

  In the write content guarantee process, a data verify process for checking the consistency between the save target data in the main memory 13 and the data saved in the hibernation memory 14 is performed, the checksum of the written backup data is written, and hibernation is performed. Since the completion flag ON is set, it is possible to guarantee the consistency between the data saved in the hibernation memory 14 and the data written back to the main memory 13 from the hibernation memory 14.

(Embodiment 2)
Next, Embodiment 2 of the present invention will be described.
In the second embodiment, an example in which various processes are executed by multitasking will be described.

  In the second embodiment, the program storage memory 12 stores an operating system. The operating system includes a program for executing ECR control processing (hereinafter referred to as ECR control processing B for distinguishing from the first embodiment), external input event interrupt processing, timer interrupt processing, and termination processing. The program storage memory 12 stores various programs for executing the product registration processing task and the write area pre-erasing processing task. Each task program is constituted by a processing function.

  Since the configuration of the other ECR 1 is the same as that described in the first embodiment with reference to FIGS. 1 to 3, the operation of the second embodiment will be described below with reference to the description.

  FIGS. 13 to 16 show flowcharts of processing executed in cooperation with the CPU 10 and the operating system.

The processing shown in FIGS. 13 to 16 is executed while switching as follows by the cooperation of the CPU 10 and the operating system.
After the activation of ECR1, first, ECR control processing B shown in FIG. 13 is executed. When an input (external input event interrupt) by the input device 18 occurs, the ECR control process B is interrupted and the external input event interrupt process shown in FIG. 14 is executed. When the external input event interrupt process ends, the process is resumed from the execution position where the ECR control process B was interrupted. When a timer interrupt is generated by the internal clock of the CPU 10, the ECR control process B is interrupted and the timer interrupt process shown in FIG. 15 is executed. When the timer interrupt process ends, the process returns to the process at the position where the ECR control process B was interrupted. When a signal for notifying AC power supply interruption is input by the AC power supply state monitoring circuit 34 and a power supply interruption interrupt occurs, the termination process shown in FIG. 16 is executed, and the operation of ECR1 is stopped.

The ECR control process B will be described with reference to FIG.
First, a task registration process is executed (step S41). In the task registration process, for example, a pointer to a process (processing function) serving as a task (system function) and a task execution priority (hereinafter simply referred to as priority) are registered in the system data area 134 of the main memory 13. The process includes a process and a process for securing a task stack area.

FIG. 17 shows an example of information registered as system data of the operating system in the system data area 134 of the main memory 13.
In the task registration process, registered task information 134a with priority level 1, registered task information 134b with priority level 2 and registered task information 134c with priority level 3 shown in FIG. 17 are registered. Here, priority 1 is the highest and priority 3 is the lowest. Each registered task information includes a pointer to a process (processing function) to be a task. In the second embodiment, the product registration processing task (referred to as task A) is written as the priority 1 registration task information 134a, and the write area pre-erase processing task (priority 3 registration task information 134c) Task C) is written. In FIG. 17, the case where the priority of the task is three levels is shown as an example, but the present invention is not limited to this.
In addition, as shown in FIG. 17, other information 134d is written in the system data of the operating system. In the other information 134d, an activation request flag of each registered task is written. In the second embodiment, an activation request flag for task A, an activation request flag for task C, a designated time until the next activation of task C, the next execution position of task C, and the like are written. When the activation request flag of task A and the activation request flag of task C are “1”, it indicates that there is an activation request, and when “0”, there is no activation request. In the task registration process, “0” is written as the initial value of the task A activation request flag, and “1” is written as the initial value of the task C activation request flag.

  Next, the activation request flag for task A in the system data area 134 is referred to, and it is determined whether the activation request flag for task A is “1” (step S42).

  Although the initial value of the task A activation request flag is “0”, when a request for product registration processing is input from the input device 18 and an external input event interrupt is generated by the input device 18, as shown in FIG. External input event interrupt processing is executed and rewritten to “1” (step S51 in FIG. 14).

  If it is determined that the task A activation request flag is “1” (step S42; YES), the task A activation request flag is rewritten to “0” (step S43), and the product registration processing task (task A) ) Is executed (step S44).

In accordance with the input from the input device 18, the product registration processing task registers the date and time when the product was traded, the product name, the sales quantity of the product, the sales data such as the sales amount, the person in charge, etc. in the user data area 136, and the product name In this process, the number of sales (purchase), sales (purchase) amount, deposit amount, return amount, etc. are printed on the receipt by the printing device 17.
If an external input event interrupt or timer interrupt occurs during the execution of the product registration processing task, the product registration processing task is interrupted, and the external input event interrupt processing or timer interrupt processing is executed. At this time, the execution position of the interrupted task is written into the register of the CPU 10, and after completion of the processing by interruption, the product registration processing task is resumed from the interrupted execution position.

When the process of step S44 ends, the process returns to step S42.
If it is determined in step S42 that the task A activation request flag is “0” (step S42; NO), the task C activation request flag in the system data area 134 is referred to, and the task C activation request flag is set. It is determined whether or not “1” (step S45). If it is determined that the task C activation request flag is “1” (step S45; YES), the task C activation request flag is rewritten to “0” (step S46), and the write area pre-erase processing task ( Task C) is executed (step S47).

FIG. 18 shows a flowchart of the write area pre-erasing process task.
Here, the write area pre-erasing process task is a process of erasing data stored in the hibernation memories 14a and 14b. As described above, the data stored in the main memory 13 is saved (written) in the hibernation memories 14a and 14b when the AC power supply 31 is shut off. This data saving is performed by supplying power from the backup power supply 32 in an end process executed by a power-off interrupt described later. However, before the data is written to the hibernation memories 14a and 14b, it is necessary to first erase the data written at the previous AC cutoff from the hibernation memories 14a and 14b. If this process is all performed in the end process, it takes time until the operation is completely stopped after the AC power supply 31 is shut off, and the backup power supply 32 is consumed. Therefore, the hibernation memory when the AC power supply 31 is cut off is executed by executing the write area pre-erase processing task in the idle time when there is no other processing to be executed in the CPU 10, that is, the product registration processing task or the like is not executed. The time required for erasing data from 14a and 14b is shortened, and consumption of the backup power source 32 is reduced.

  First, the number stored in the erase block number area 131a is acquired (step S401). Next, it is determined whether or not the acquired number is the last block number n of the hibernation memories 14a and 14b (step S402).

  If it is determined that the acquired number is not the final block number n (step S402; NO), the hibernation memory 14a, 14b is instructed to erase the data of the block having the number next to the acquired number (step S403). ). In the system data area 134, information on the designated time until the next start of the write area pre-erasing process task (task C) and information on the next execution position of task C (executed when the write area pre-erasing process is resumed) The starting position, specifically, step S405) is written, and the write area pre-erase processing task enters a waiting state (step S404).

Returning to FIG. 13, when the write area pre-erasing process task is in a waiting state, the process returns to the ECR control process B, and the process is executed from step S42.
When the ECR control process B is executed for a predetermined time, a timer interrupt is generated and the timer interrupt process shown in FIG. 15 is executed. Generation of the timer interrupt is managed by the internal clock of the CPU 10.

Here, the timer interrupt process will be described with reference to FIG.
First, it is determined whether or not the specified time written in the system data area 134 until the next activation of task C has elapsed (step S61). Whether or not the designated time until the next activation of task C has elapsed is managed by the internal clock of the CPU 10.

When it is determined that the designated time until the next activation of the task C has not elapsed (step S61; NO), the timer interrupt process ends.
When it is determined that the designated time until the next activation of task C has elapsed (step S61; YES), the activation request flag of task C is rewritten to “1”, and the timer interrupt process ends.

  When the timer interrupt process ends, the process proceeds to step S42 of the ECR control process B shown in FIG. If it is determined in step S42 that the activation request flag for task A is “1” (step S42; YES), the processes of steps S43 and S44 described above are executed. If it is determined in step S42 that the task A activation request flag is “0” (step S42; NO), the task C activation request flag in the system data area 134 is referred to, and the task C activation request flag is set. It is determined whether or not “1” (step S45).

  When it is determined that the task C activation request flag is not “1” (step S45; NO), the process returns to step S42. If it is determined that the task C activation request flag is “1” (step S45; YES), the process proceeds to step S46, the task C activation request flag is rewritten to “0”, and the write area pre-erase is performed. Processing is resumed (step S47).

  Here, since the position of step S405 in FIG. 18 is written in the system data area 134 as the execution position when the write area pre-erase process is resumed, the write area pre-erase process is performed in the step of FIG. The process is resumed from S405.

  In step S405 in FIG. 18, an inquiry as to whether or not the data erasure of the block designated in step S403 has been completed is transmitted to the hibernation memories 14a and 14b, indicating that the data erasure of the designated block has not been completed. When a response is received from the hibernation memories 14a and 14b (step S405; NO), the process returns to step S404. When the hibernation memory 14a, 14b responds that the erasure of the designated block has been completed (step S405; YES), the block number of the data-erased block is written into the erasure block number area 131a (step S405). In step S406, the process returns to step S401 in FIG.

  On the other hand, if it is determined in step S402 that the acquired number is the final block number n (step S402; YES), the write area pre-erasing process task is terminated, and the process proceeds to step S42 in FIG.

  When a signal for notifying AC power supply interruption is input from the AC power supply state monitoring circuit 34, a power supply interruption interrupt occurs, and the termination process shown in FIG. 16 is executed. Since the end process is the same as that described with reference to FIG. 6 in the first embodiment, the detailed description is cited. That is, the suspend process (step S71), the backup power supply 32 is switched on by switching the switch 35 (step S72), the hibernation process (step S73), and the backup power supply 32 is switched off by switching the switch 35 (step S72). Step S74) is performed and the operation is stopped. In the write area erase process (see FIG. 8) of the hibernation process, only unprocessed residual data that could not be erased by the write area pre-erase process task has to be erased. The time required for erasing data from 14a and 14b can be shortened, and consumption of the backup power supply 32 can be reduced.

  When a signal for notifying that the AC power is turned on is input from the AC power supply state monitoring circuit 34, the startup process shown in FIGS. 11a to 11b is executed. Since the activation process is the same as that described in the first embodiment, the description is incorporated.

  As described above, according to the ECR 1 in the second embodiment, the data on the main memory 13 is saved to the hibernation memory 14 which is a non-volatile memory when the AC power supply 31 is cut off, so a large-capacity backup power supply is installed. Without this, the system can be restored to the state before the power shutdown after the AC power shutdown for a long time.

  Since the data saved in the hibernation memory 14 is erased in advance by the write area pre-erase processing task in the idle time when there is no other task to be executed in the CPU 10, the data from the backup power source 32 is cut off when the AC power source 31 is shut off. It is possible to reduce the time required for erasing data from the hibernation memories 14a and 14b in the hibernation process executed with power supply. As a result, the consumption of the backup power source 32 can be reduced.

  Further, since the backup power supply 32 is switched off except when the hibernation process is executed, it is possible to minimize the consumption of the backup power supply 32.

  Further, since a plurality of hibernation memories 14 are provided and data writing and erasing are performed in parallel in the plurality of hibernation memories 14, the data writing speed and erasing speed to the hibernation memory 14 can be improved. As a result, the consumption of the backup power source 32 can be reduced.

  Further, the state of the main memory 13 at the time of AC power interruption is maintained until the hibernation process is completed. During the hibernation process, the power state of the AC power supply 31 is monitored by the CPU 10 and the AC power supply 31 is in the supply state. In such a case, the hibernation process is interrupted and the process proceeds to the start-up process, and data indicating the system operation state stored in the main memory 13 is written back to the CPU 10 so that the operation is returned to the state before the AC power supply is shut off. Is called. Specifically, the hibernation process includes a write area erasure process, a write process, and a write content guarantee process. The CPU 10 uses the AC power supply during data erasure and writing for each block in the hibernation memory 14. When the state is monitored and the AC power supply 31 is in the supply state, control is performed to interrupt the hibernation process and shift to the hibernation interruption restart position of the activation process. Therefore, when the AC power supply 31 is in a supply state during the hibernation process, it is possible to immediately return to the system state before the AC power supply cut-off without waiting for the completion of the hibernation process.

  In the write content guarantee process, a data verify process for checking the consistency between the save target data in the main memory 13 and the data saved in the hibernation memory 14 is performed, the checksum of the written backup data is written, and hibernation is performed. Since the completion flag ON is set, it is possible to guarantee the consistency between the data saved in the hibernation memory 14 and the data written back to the main memory 13 from the hibernation memory 14.

In addition, the description content in the said Embodiment 1-2 is a suitable example of ECR1 which concerns on this invention, and is not limited to this.
For example, the data stored in the main memory 13 is an example and is not limited to this.
In addition, the detailed configuration and detailed operation of each device constituting the ECR 1 can be appropriately changed without departing from the spirit of the invention.

It is a block diagram which shows the function structural example of ECR in embodiment of this invention. FIG. 2 is a diagram illustrating a data storage example and a data flow of the CPU, program storage memory, main memory, and hibernation memory of FIG. 1. It is a figure which shows the principal part structural example of the power supply system of ECR of FIG. It is a flowchart which shows the ECR control process performed by CPU of FIG. It is a flowchart which shows the write-area pre-erasure process performed by CPU of FIG. It is a flowchart which shows the completion | finish process performed by CPU of FIG. It is a flowchart which shows the hibernation process performed by CPU of FIG. 3 is a flowchart showing a write area erasing process executed by a CPU of FIG. 1. It is a flowchart which shows the write-in process performed by CPU of FIG. It is a flowchart which shows the written content guarantee process performed by CPU of FIG. It is a flowchart which shows the starting process performed by CPU of FIG. It is a flowchart which shows the starting process performed by CPU of FIG. It is a figure which shows the example of a display before and after AC power supply interruption | blocking of the main display apparatus of FIG. It is a flowchart which shows the ECR control process B performed by CPU of FIG. It is a flowchart which shows the external input event interruption process performed by CPU of FIG. It is a flowchart which shows the timer interruption process performed by CPU of FIG. It is a flowchart which shows the power-supply-cutting interruption process performed by CPU of FIG. It is a figure which shows an example of the information registered as system data of an operating system in the system data area | region of the main memory shown in FIG. It is a flowchart which shows the write-area pre-erase processing task performed by CPU of FIG.

Explanation of symbols

1 ECR
10 CPU
11 RTC
12 Program storage memory 13 Main memory 131 Work area for start / end processing 131a Erase block number area 132 Suspend area 133 Copy area 134 System data area 135 Setting data area 136 User data area 14 Hibernation memory 141 Header area 142 Backup area 143 Checksum storage area 151 Main display device 152 Sub display device 16 LED
17 Printing device 18 Input device 19 Storage I / F
19a External storage 20 Communication unit

Claims (4)

Volatile storage means for storing data by power supply from the main power supply;
Nonvolatile storage means for saving data stored in the volatile storage means when the main power supply is shut off;
The data stored in the nonvolatile storage means is erased during the processing free time, and when the main power supply is shut off, the data stored in the nonvolatile storage means is not supplied with power from the auxiliary power supply. Control means for executing erasure processing of residual data for erasure and for saving data stored in the volatile storage means to the nonvolatile storage means;
A sales data processing apparatus. A plurality of the nonvolatile storage means;
The sales data processing apparatus according to claim 1, wherein the control unit distributes and saves data stored in the volatile storage unit to the plurality of nonvolatile storage units. Comprising a switching means for switching between supply and interruption of power from the auxiliary power supply,
The control means causes the switching means to supply power to the auxiliary power supply when the main power is cut off, and causes the switching means to cut off the auxiliary power supply after data saving to the nonvolatile storage means is completed. The sales data processing apparatus according to claim 1 or 2. A sales data processing apparatus comprising: volatile storage means for storing data by power supply from a main power supply; and nonvolatile storage means for saving data stored in the volatile storage means when the main power supply is shut off The computer used for
The data stored in the nonvolatile storage means is erased during the processing free time, and when the main power supply is shut off, the data stored in the nonvolatile storage means is not supplied with power from the auxiliary power supply. Control means for executing erasure processing of residual data for erasure and for saving data stored in the volatile storage means to the nonvolatile storage means;
Program to function as.

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