JP2010123588A - Silicon wafer and heat treatment method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a heat treatment method of a silicon wafer, capable of efficiently suppressing the development of slip transition without impairing the effects of heat treatment. <P>SOLUTION: The heat treatment method of the silicon wafer includes repeating a temperature increase/decrease process consisting of a temperature increase section for increasing the temperature of a silicon wafer and a temperature decrease section for decreasing the temperature of the silicon wafer without keeping the silicon wafer at a constant temperature in a temperature range exceeding 800°C. According to this method, the silicon wafer is subjected to temperature increase/decrease at a temperature range exceeding 800°C where slip transition is easily developed without keeping the silicon wafer at a constant temperature, so that the development of slip transition can be easily suppressed. Furthermore, the temperature increase decrease process is repeated at a plurality of times, thereby a summation time in heating can be ensured and a sufficient high-temperature thermal history can be imparted to the silicon wafer. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a heat treatment method for a silicon wafer, and more particularly, to a heat treatment method for a silicon wafer capable of suppressing extension of slip dislocation. The present invention also relates to a silicon wafer manufactured through such heat treatment.

  A silicon wafer used for manufacturing an IC device is manufactured by slicing a silicon single crystal ingot pulled up by the Czochralski method (CZ method) or the like, and performing mirror processing or the like.

  However, the as-grown silicon single crystal contains crystal growth introduction defects (grown-in defects). If such defects exist on the surface of the silicon wafer, the IC device may not operate correctly. There is. For this reason, rapid heating / cooling heat treatment is performed for the purpose of eliminating defects from the surface layer of the silicon wafer. When such a heat treatment is performed on the silicon wafer, the grown-in defects existing on the surface layer of the silicon wafer disappear, and a defect-free layer (Denuded Zone) containing almost no defects can be formed.

  In addition, since a silicon wafer manufactured by the CZ method contains a large amount of oxygen between silicon lattices, when the silicon wafer is rapidly heated and cooled, atomic vacancies injected into the silicon wafer due to rapid heating are reduced. Freezing inside by rapid cooling. Since the frozen atomic vacancies form oxygen precipitates called BMD (Bulk Micro Defect) by the subsequent heat treatment, an IG (Intrinsic Gettering) layer can be formed inside the silicon wafer.

  Therefore, when a heat treatment for rapidly heating and cooling the silicon wafer is performed, a denuded zone containing almost no defects is formed on the surface layer of the silicon wafer, and an IG layer containing high-density BMD is formed inside the silicon wafer. This makes it possible to improve the quality of the silicon wafer.

  Such heat treatment for the silicon wafer is performed using an RTA (Rapid Thermal Anneal) apparatus. The RTA apparatus is an apparatus that rapidly heats and cools a silicon wafer using an infrared lamp or the like, and in the apparatus, the back surface of the silicon wafer is supported by a plurality of support pins. For this reason, the back surface of the silicon wafer is slightly damaged at the contact portions with the support pins, and minute dislocation clusters are generated. The dislocation clusters themselves formed in this way are not actually harmful, but when a strong thermal stress is applied to the dislocation clusters by heat treatment, the dislocation clusters expand and become slip dislocations. Slip dislocation gradually extends during heat treatment.

  In particular, in a large-diameter silicon wafer having a diameter of 300 mm that has been widely used in recent years, the stress due to its own weight is large, so that the extension of slip dislocation is remarkable as compared with a small-diameter silicon wafer. Of course, in a silicon wafer having a larger diameter such as 450 mm in diameter, extension of slip dislocation due to its own weight becomes more remarkable.

  When slip dislocations are formed on the back surface of the silicon wafer in this way, the strength of the silicon wafer is reduced or the silicon wafer is warped. Further, slip dislocation also causes a leakage current in the IC device, which causes a problem of reducing the yield of the IC device. For this reason, suppressing the generation and extension of slip dislocations due to heat treatment is one of the important issues in the silicon wafer manufacturing process.

As a method for suppressing the extension of slip dislocation due to heat treatment, Patent Document 1 describes that the extension of slip dislocation can be suppressed by increasing the ramping rate (temperature decrease rate).
JP 2007-290961 A

  However, a study by the present inventors has revealed that it is difficult to sufficiently suppress the extension of slip dislocation by simply increasing the temperature drop rate. In addition, it has been found that there are cases in which the effect of heat treatment is insufficient by simply increasing the temperature drop rate. That is, in order to inject a sufficient amount of atomic vacancies into a silicon wafer, it is necessary to heat the silicon wafer to a predetermined temperature range or more and hold this state for a certain period of time. However, if the temperature drop rate is increased, the time required for the silicon wafer to pass through a temperature region above a predetermined value is reduced, so that the concentration of vacancies injected into the silicon wafer is insufficient, and as a result, BMD does not sufficiently precipitate. It happens. The present invention has been made to solve such problems.

  Therefore, an object of the present invention is to provide a silicon wafer heat treatment method capable of effectively suppressing the extension of slip dislocation without impairing the effect of the heat treatment. Another object of the present invention is to provide a silicon wafer manufactured through such heat treatment.

  As a result of extensive research on a heat treatment method for a silicon wafer that can effectively suppress the extension of slip dislocation without impairing the effect of the heat treatment, the present inventor has found that the extension of slip dislocation is in a high-temperature state of the silicon wafer. It has become clear that the state in which the silicon wafer is kept at a constant temperature is most likely to cause extension. On the other hand, in order to sufficiently obtain the effect of the heat treatment, it is necessary to ensure an accumulated time for the silicon wafer to pass through a temperature region that is equal to or higher than a predetermined value. For this reason, in order to solve the above-mentioned problem, it is important to secure an integration time while avoiding a temperature state in which slip dislocation is likely to extend. The present invention has been made based on such technical knowledge.

  The silicon wafer heat treatment method according to the present invention includes a temperature rising / lowering process comprising a temperature rising section for raising the temperature of the silicon wafer and a temperature lowering section for lowering the temperature of the silicon wafer without holding the silicon wafer at a constant temperature in a temperature range exceeding 800 ° C. Is repeated a plurality of times.

  According to the present invention, since the temperature is raised and lowered without holding the silicon wafer at a constant temperature in a temperature region exceeding 800 ° C. at which slip dislocations easily extend, it is possible to suppress the extension of slip dislocations. . In addition, since the temperature raising / lowering process is repeated a plurality of times, it is possible to secure an integrated time during heating, and to give a sufficient high-temperature heat history to the silicon wafer. This makes it possible to effectively suppress the extension of slip dislocations while injecting a sufficient amount of atomic vacancies into the silicon wafer. However, the present invention is not limited to the heat treatment for injecting atomic vacancies into the silicon wafer, and may be a heat treatment for forming an epitaxial layer on the surface of the silicon wafer.

  In the present invention, it is preferable that both the temperature increase rate in the temperature increase interval and the temperature decrease rate in the temperature decrease interval are 10 ° C./s or more. This is because the extension of slip dislocation can be more effectively suppressed as compared with the case where the temperature rising rate or the temperature falling rate is less than 10 ° C./s.

  In the present invention, it is preferable that both of the temperature rising rate in the temperature increasing section and the temperature decreasing rate in the temperature decreasing section are less than 200 ° C./s. When the rate of temperature rise or the rate of temperature fall is 200 ° C./s or more, it is necessary to repeat the temperature raising and lowering process many times in order to secure a sufficient integration time, and the control becomes complicated. In addition, when the temperature rising rate or the temperature falling rate is 200 ° C./s or more, the silicon wafer moves in the chamber, and as a result, the silicon wafer may be broken by collision with the support pins. On the other hand, if the temperature increase rate and the temperature decrease rate are less than 200 ° C./s, the number of repetitions of the temperature increasing / decreasing process can be reduced, and control becomes easy.

  In the present invention, it is preferable that the temperature increase rate or the temperature decrease rate is reduced in a region where the temperature of the silicon wafer is higher in at least one of the temperature increase interval and the temperature decrease interval. According to this, it becomes possible to give sufficient high-temperature heat history in a shorter period.

  In addition, the silicon wafer according to the present invention is characterized in that atomic vacancies are implanted therein by the above heat treatment method. Furthermore, the silicon wafer according to the present invention is characterized in that an epitaxial layer is formed on the surface by the above heat treatment method.

  As described above, according to the present invention, it is possible to effectively suppress the extension of slip dislocation without impairing the effect of the heat treatment. In addition, according to the present invention, it is possible to provide a high-quality silicon wafer manufactured through such heat treatment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic diagram showing the structure of an RTA apparatus for performing heat treatment.

  An RTA apparatus 10 shown in FIG. 1 has a chamber 12 made of a quartz plate 11 and heat-treats a silicon wafer 13 in the chamber 12. The silicon wafer 13 is heated by an infrared lamp 14 disposed so as to surround the chamber 12 from above and below. The silicon wafer 13 is held by three support pins 16 formed on the quartz table 15. Instead of the support pin 16, an annular susceptor may be used. The silicon wafer 13 is supported from the back surface 13 a side, and no member is in contact with the main surface 13 b of the silicon wafer 13.

  The chamber 12 is provided with a gas introduction port 17 for introducing an inert gas G for heat treatment and a gas exhaust port 18 for exhausting the inert gas G. In addition, an infrared thermometer (not shown) is provided outside the chamber 12 so that the temperature of the silicon wafer 13 is measured in a non-contact manner.

  FIG. 2 is a schematic diagram for explaining a contact position between the silicon wafer 13 and the support pins 16.

  As shown in FIG. 2, the support pins 16 are in contact at three locations in the vicinity of the outer periphery of the back surface 13 a of the silicon wafer 13. For this reason, the back surface 13a of the silicon wafer 13 is slightly damaged at the contact portions with the support pins 16, and minute dislocation clusters are generated. Such damage becomes more prominent when the silicon wafer 13 has a large diameter of 300 mm or more because stress due to its own weight is large. The formed dislocation clusters serve as starting points for slip dislocations generated by the heat treatment.

  FIG. 3 is a flowchart for explaining a heat treatment method using the RTA apparatus 10.

  First, the silicon wafer 13 is placed in the chamber 12, and the back surface 13a is held by the three support pins 16 (step S1). Next, in order to heat-treat the silicon wafer 13 in a constant gas atmosphere, a predetermined inert gas G is continuously introduced into the chamber 12 from the gas inlet 17 and continuously exhausted from the gas outlet 18 (step). S2). Thereby, the inside of the chamber 12 is maintained in an inert gas atmosphere. As the inert gas G, nitrogen gas or the like can be used. In this state, the infrared lamp 14 is turned on to heat the silicon wafer 13 (step S3).

  FIG. 4 is a graph showing an example of a temperature change of the silicon wafer 13 in the heat treatment process. In FIG. 4, the horizontal axis represents time, and the vertical axis represents temperature. The same applies to the graphs described below.

  As shown in FIG. 4, in this embodiment, the temperature of the silicon wafer 13 is raised and lowered in a V shape. Specifically, the temperature rise and fall consists of a temperature raising section H where the temperature of the silicon wafer 13 is raised from the temperature T1 to the temperature T2 (> T1) by the infrared lamp 14, and a temperature lowering section C where the temperature of the silicon wafer 13 is lowered from the temperature T2 to the temperature T1. The warm process P is repeated several times. Therefore, the temperature T1 is the starting point of the temperature rising section H and the end point of the temperature decreasing section C, and the temperature T2 is the starting point of the temperature decreasing section C and the end point of the temperature rising section H. Such temperature increase / decrease control is performed by controlling the output of the infrared lamp 14.

  Although the values of the temperatures T1 and T2 depend on the purpose of the heat treatment, the temperature T1 is preferably about 800 ° C. and the temperature T2 is about 1200 ° C. in the case of atomic vacancy injection for forming BMD. preferable. This is because slip dislocations are likely to extend in a temperature range exceeding 800 ° C., and high-density atomic vacancies are not injected unless heated to about 1200 ° C.

  Here, as shown in FIG. 4, in the temperature region exceeding 800 ° C., the silicon wafer is kept at a constant temperature, and the temperature is constantly raised and lowered. The temperature range exceeding 800 ° C. is a temperature at which slip dislocations are easily extended. When the temperature is kept at a constant temperature in this temperature range, the extension of slip dislocations becomes significant. That is, since the ductility and brittle transition temperature of silicon exists in the vicinity of 600 ° C., the dislocation hardly extends at a temperature of about 600 ° C. As the temperature rises, the dislocation extension rate increases. When the temperature exceeds 800 ° C., the extension rate increases to such an extent that it can be evaluated by various methods. Although not particularly limited, in the present embodiment, the temperature T1 is set to 800 ° C.

  In this way, since the silicon wafer is constantly raised and lowered in a temperature range exceeding 800 ° C. at which slip dislocations easily extend, the extension of slip dislocations starting from the dislocation clusters generated at the contact portions with the support pins 16. Is suppressed.

  In addition, since the temperature increasing / decreasing process P is not performed only once, but is repeated a plurality of times, it is possible to sufficiently secure the accumulated time for passing through the temperature region necessary for the injection of atomic vacancies. Thereby, it becomes possible to give a sufficient high-temperature heat history to the silicon wafer 13.

  Moreover, although not specifically limited, it is preferable that the temperature rising rate in the temperature rising zone H and the temperature falling rate in the temperature falling zone C are both 10 ° C./s or more and less than 200 ° C. /. This is because the extension of slip dislocation becomes more noticeable as the rate of temperature rise and the rate of temperature fall is slower, so that the extension of slip dislocation can be effectively suppressed by setting it to 10 ° C./s or more. In addition, if it is 200 ° C./s or more, it is necessary to repeat the temperature raising / lowering process P many times in order to secure a sufficient integration time, and the control becomes complicated. In addition, when the temperature rising rate or the temperature falling rate is 200 ° C./s or more, the silicon wafer 13 moves in the chamber 12, and as a result, the silicon wafer 13 may be broken by collision with the support pins 16. Because.

Further, when the rate of temperature rise is R _H and the rate of temperature drop is R _C , it is preferable to set R _H < _RC . This is because the extension of slip dislocation is more likely to occur when the temperature is lowered than when the temperature is increased, and thus the extension of the slip dislocation can be suppressed by setting the temperature decrease rate _RC relatively large. In addition, by setting the temperature increase rate _RH relatively small, it is easy to secure the accumulated time for passing through the temperature region necessary for the injection of atomic vacancies.

  Returning to FIG. 3, after performing the V-shaped lifting, heating by the infrared lamp 14 is stopped and rapid cooling is performed (step S <b> 4). As a result, atomic vacancies existing in the surface layer of the silicon wafer 13 diffuse to the outside and disappear, and a large amount of atomic vacancies are frozen only inside. The atomic vacancies frozen in the silicon wafer 13 form BMD by a subsequent heat treatment, thereby providing a gettering effect.

  Finally, if the silicon wafer 13 is taken out from the chamber 12 (step S5), a series of heat treatment processes is completed.

  As described above, according to the present embodiment, since the temperature increasing / decreasing process P is repeated a plurality of times in a temperature region exceeding 800 ° C., sufficient integration time for passing through the temperature region necessary for the injection of atomic vacancies is sufficiently ensured. However, it is possible to effectively suppress the extension of slip dislocation starting from the dislocation cluster generated at the contact portion with the support pin 16.

  The preferred embodiments of the present invention have been described above. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, these are also included in the present invention.

  For example, in the above embodiment, the temperature T1 is set to 800 ° C. and the temperature T2 is set to 1200 ° C. However, as long as the temperature is constantly raised and lowered in the temperature region exceeding 800 ° C., the starting point of the temperature rising zone H and the end point of the temperature falling zone C are set. There is no limitation on the temperature T1 and the value of the temperature T2 that is the starting point of the temperature lowering section C and the end point of the temperature rising section H. Therefore, the temperature T1 may be a temperature exceeding 800 ° C. as shown in FIG. 5A, or the temperature T1 may be less than 800 ° C. as shown in FIG. 5B.

  Furthermore, it is not essential that the temperature T1 is a constant temperature, and the temperature T1 may be changed for each temperature raising / lowering process P as shown in FIG. FIG. 6A shows an example in which the temperature T1 is increased as the temperature raising / lowering process P proceeds. Similarly, it is not essential for the temperature T2 to be a constant temperature, and it may be changed for each temperature raising / lowering process P as shown in FIG. FIG. 6B shows an example in which the temperature T2 is increased as the temperature raising / lowering process P proceeds.

Furthermore, in the above embodiment, the temperature increase rate _RH and the temperature decrease rate _RC are constant. However, as shown in FIG. 7, the temperature change before and after switching from the temperature increase interval H to the temperature decrease interval C may be moderate. . In other words, it may be controlled so that at least one of the temperature increase rate _RH and the temperature decrease rate _RC becomes smaller as the temperature of the silicon wafer 13 is higher. According to this, since the integration time passing through the temperature region necessary for the injection of atomic vacancies becomes longer, it is possible to provide a sufficient high temperature thermal history in a shorter period. Moreover, a rapid temperature change in the high temperature region increases the risk of cracking the silicon wafer 13, but such a risk can also be suppressed by performing the temperature control shown in FIG.

  In the above embodiment, the heat treatment for injecting atomic vacancies into the silicon wafer 13 has been described as an example. However, the heat treatment that is the subject of the present invention is not limited to this, and other heat treatments, for example, It is also possible to apply to heat treatment for forming an epitaxial layer on the surface of the silicon wafer 13. When applied to a heat treatment for forming an epitaxial layer on the surface of the silicon wafer 13, the temperature T1 is preferably about 800 ° C., and the temperature T2 is preferably about 1100 ° C. Further, the temperature increase rate may be about 15 ° C./s, and the temperature decrease rate may be about 10 ° C./s. Furthermore, the present invention can also be applied to heat treatment included in the IC device manufacturing process. In other words, since the device process temperature is often near 800 ° C., the application of the heat treatment method according to the present invention suppresses the extension of slip, and as a result, the yield of IC devices can be increased.

As a silicon wafer for evaluation, a plurality of silicon wafers having a diameter of 200 mm and an oxygen concentration of In [Oi] = 11.0 × 10 ¹⁷ atoms / cm ³ (Old ASTM) were prepared, and the same as the RTA apparatus 10 shown in FIG. Were put into an RTA apparatus having the structure of FIG. The inert gas introduced during the heat treatment was nitrogen gas.

  Among the silicon wafers for evaluation, the samples of Examples 1 to 3 wait for a while while being heated from room temperature to 800 ° C., and as shown in FIG. 4, the temperature T1 is 800 ° C. and the temperature T2 is 1200 ° C. The temperature raising / lowering process was repeated several times. The number of repetitions of the temperature raising / lowering process was set to 2 times, 3 times, and 5 times for the samples of Examples 1 to 3, respectively. In any of the samples, the temperature was constantly raised or lowered without being kept at a constant temperature in the temperature range of 800 ° C to 1200 ° C.

  On the other hand, as Comparative Examples 1 to 3, as shown in FIG. 8, the temperature raising / lowering process is repeated only once, and a high temperature heat history equal to each of Examples 1 to 3 is given to 1200 ° C. for a predetermined time t. And heat treatment was performed. Specifically, the samples of Comparative Examples 1 to 3 were held at 1200 ° C. for 4 seconds, 6 seconds, and 10 seconds, respectively, with respect to Examples 1 to 3 in which the temperature increasing / decreasing process was repeated twice, three times, and five times. did. The temperature increase rate and the temperature decrease rate were set to 50 ° C./s and 75 ° C./s, respectively, as in Examples 1-3.

  After the heat treatment was completed, the silicon wafer was taken out of the RTA apparatus, and the length of the slip dislocation extended from the contact portion with the support pin was measured. The measurement was performed by immersing the silicon wafer after heat treatment in a mixed solution of potassium dichromate, water and hydrofluoric acid for 50 minutes, etching the front and back surfaces, and then observing the pit length on the surface of the silicon wafer with an optical microscope. . The results are shown in FIG.

  As shown in FIG. 9, when silicon wafers having equivalently given the same thermal history are compared, a sample (Example) in which the temperature increasing / decreasing process is repeated a plurality of times, rather than a sample (Comparative Example) maintained at 1200 ° C. for a certain time ) Was confirmed to have a shorter slip length.

Each sample was then subjected to precipitation heat treatment at 800 ° C. for 4 hours and 1000 ° C. for 16 hours. As a result, each of Example 1 and Comparative Example 1 was 1.6 × 10 ⁶ pieces / cm ³ , and both of Example 2 and Comparative Example 2 were 1.9 × 10 ⁶ pieces / cm ³ , Example 3 and Comparative Example In all of Examples 3, BMDs of 2.4 × 10 ⁶ pieces / cm ³ were formed, and it was confirmed that there was no difference in BMD density between the corresponding Examples and Comparative Examples. The BMD density was measured by performing selective etching of 2 μm with an etching solution and then counting BMD erosion images with an optical microscope.

Next, as another silicon wafer for evaluation, a plurality of silicon wafers having a diameter of 200 mm and an oxygen concentration of In [Oi] = 15.0 × 10 ¹⁷ atoms / cm ³ (Old ASTM) were prepared and shown in FIG. A rapid heating / cooling heat treatment was performed using an RTA apparatus having the same structure as the RTA apparatus 10. The inert gas introduced during the heat treatment was nitrogen gas. The heat treatment was performed by holding at 1200 ° C. for 10 seconds as in Comparative Example 3 (see FIG. 8). About the temperature increase rate and the temperature decrease rate, as shown in Table 1 below, different rates were set for each of the samples 1 to 9.

  After the heat treatment, it was immersed in a Seco etchant and stirred for 3 minutes, and the length of the slip that appeared on the surface was measured with an optical microscope. The results are shown in FIG.

  As shown in FIG. 10, very long slips were formed in Samples 1 and 6 having a temperature rising rate or a temperature decreasing rate of 8 ° C./s, but the temperature increasing rate and the temperature decreasing rate were 10 ° C./s or more. In some other samples, the slip length drastically decreased to about 1/2 to 1/3 of samples 1 and 6. As a result, by making the temperature rising rate in the temperature increasing section and the temperature decreasing rate in the temperature decreasing section both 10 ° C./s or more, compared with the case where the temperature increasing rate or temperature decreasing rate is less than 10 ° C./s, It was confirmed that extension was effectively suppressed.

It is a schematic diagram which shows the structure of the RTA apparatus 10 for performing heat processing. It is a schematic diagram for demonstrating the contact position of the silicon wafer 13 and the support pin 16. FIG. 4 is a flowchart for explaining a heat treatment method using the RTA apparatus 10. It is a graph which shows an example of the temperature change of the silicon wafer 13 in a heat treatment process. It is a graph which shows the other example of the temperature change of the silicon wafer 13 in a heat treatment process. It is a graph which shows the further another example of the temperature change of the silicon wafer 13 in a heat treatment process. It is a graph which shows the further another example of the temperature change of the silicon wafer 13 in a heat treatment process. It is a graph which shows the temperature change of the silicon wafer by a comparative example. It is a graph which shows the length measurement result of slip dislocation. It is a graph which shows the relationship between temperature rising rate and temperature falling rate, and slip length.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 RTA apparatus 11 Quartz plate 12 Chamber 13 Silicon wafer 13a Silicon wafer back surface 13b Silicon wafer main surface 14 Infrared lamp 15 Quartz table 16 Support pin 17 Gas introduction port 18 Gas exhaust port

Claims (8)

  The temperature increasing / decreasing process consisting of a temperature increasing period for increasing the temperature of the silicon wafer and a temperature decreasing period for decreasing the temperature of the silicon wafer is repeated a plurality of times without maintaining the silicon wafer at a constant temperature in a temperature region exceeding 800 ° C. To heat-treat silicon wafers.   2. The method for heat-treating a silicon wafer according to claim 1, wherein a temperature rising rate in the temperature increasing section and a temperature decreasing rate in the temperature decreasing section are both 10 ° C./s or more.   3. The method for heat-treating a silicon wafer according to claim 1, wherein a temperature increase rate in the temperature increase interval and a temperature decrease rate in the temperature decrease interval are both less than 200 ° C./s.   4. The silicon wafer according to claim 1, wherein, in at least one of the temperature increase period and the temperature decrease period, a temperature increase rate or a temperature decrease rate is decreased in a region where the temperature of the silicon wafer is higher. Heat treatment method.   5. The method for heat-treating a silicon wafer according to claim 1, wherein atomic vacancies are injected into the silicon wafer by the temperature raising / lowering process. 6.   5. The method for heat-treating a silicon wafer according to claim 1, wherein an epitaxial layer is formed on the surface of the silicon wafer by the temperature raising / lowering process. 6.   6. The silicon wafer according to claim 5, wherein the atomic vacancies are injected therein by the heat treatment method for a silicon wafer according to claim 5.   A silicon wafer, wherein the epitaxial layer is formed on a surface by the method for heat-treating a silicon wafer according to claim 6.

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