JP2009164155A - Method of manufacturing silicon wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon wafer in which slip dislocation and curving in a device manufacturing process can be both prevented. <P>SOLUTION: Before a silicon single-crystal substrate is subjected to a usual annealing process (high-temperature heat treatment step D), heat treatments (A, B and C) are carried out at temperatures lower than usual to adjust a change amount ΔCs (atoms/cm<SP>3</SP>) of a substitution type carbon concentration (atoms/cm<SP>3</SP>) before the after the heat treatments in the range of ≥1.0×10<SP>15</SP>atoms/cm<SP>3</SP>and ≤1.0×10<SP>17</SP>atoms/cm<SP>3</SP>. Also, a change amount ΔOi (atoms/cm<SP>3</SP>) of an interstitial oxygen concentration (atoms/cm<SP>3</SP>) is adjusted in the range of ≥1.0×10<SP>17</SP>atoms/cm<SP>3</SP>and ≤6.0×10<SP>17</SP>atoms/cm<SP>3</SP>. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor wafer manufacturing technology field, and more particularly to a silicon wafer that can suppress both occurrence of slip dislocation and warpage in a device manufacturing process, and a manufacturing technology thereof.

  A silicon wafer used as a substrate of a semiconductor device or the like is manufactured by slicing a silicon single crystal ingot and performing heat treatment, mirror processing, or the like. Examples of a method for producing such a silicon single crystal ingot include the Czochralski method (hereinafter referred to as “CZ method”). The CZ method occupies most of the production of a silicon single crystal ingot because it is easy to obtain a large-diameter single crystal ingot and the defect control is relatively easy.

  A silicon single crystal pulled by the CZ method (hereinafter referred to as “CZ-Si”) has a crystal defect called a grown-in defect. CZ-Si incorporates oxygen into the supersaturation between lattices. Such supersaturated oxygen is a micro defect called “Bulk Micro Defect” (hereinafter referred to as “BMD”) in the subsequent heat treatment (annealing). Causes (oxygen precipitation nuclei).

  In order to form a semiconductor device on a silicon wafer, it is required that the semiconductor device formation region has no crystal defects. This is because if a crystal defect exists on the surface on which the circuit is formed, the defective portion causes a circuit breakdown or the like. On the other hand, appropriate BMD is required to be present inside the silicon wafer. This is because such a BMD has an action of gettering a metal impurity or the like that causes a semiconductor device malfunction.

  In order to satisfy the above requirements, the silicon wafer is annealed at a high temperature to induce BMD inside the silicon wafer to form an intrinsic gettering layer (hereinafter referred to as “IG layer”) and to exist on the surface of the silicon wafer. A technique is used in which grown-in defects to be eliminated are eliminated and a denuded zone (hereinafter referred to as “DZ layer”) layer having as few crystal defects as possible is formed.

  As a specific example, there has been proposed a method (Patent Document 1) in which a nitrogen-added substrate is annealed at a high temperature to reduce the surface grown-in defects and to form a BMD having nitrogen as a nucleus inside.

  However, the oxygen concentration of the DZ layer formed on the front and back surfaces of the silicon wafer by the high temperature annealing process is extremely reduced due to the outward diffusion of oxygen during the heat treatment. As a result, the ability to suppress dislocation defect extension on the front and back surfaces of the wafer is remarkably reduced, so that dislocation defects (hereinafter referred to as “slip”) extend into the bulk from the minute scratches on the front and back surfaces introduced in the annealing process. There is a problem that the strength of the silicon wafer is lowered due to the extension of the slip dislocation. For example, when annealing is performed in a state where it is supported by a heat treatment pobot or the like, slip dislocations often extend from a supported portion around the back surface of the wafer. Also, slip dislocations may extend from the silicon wafer edge.

  When the strength of the silicon wafer decreases, there is a concern that the wafer may be damaged or destroyed during the manufacturing process. However, the DZ layer is indispensable for semiconductor device formation, and a silicon wafer having a DZ layer and having excellent strength characteristics has been demanded.

In the prior art described in Patent Document 1 below, no consideration is given to the strength reduction of the silicon wafer, and the silicon wafer made by such a method cannot avoid the extension of slip dislocation.
On the other hand, in order to prevent the occurrence of such slip dislocation, a method of generating BMD at a high density has also been proposed.

Specifically, a substrate cut out from a silicon single crystal ingot is heated at a temperature of 500 to 1200 ° C. for 1 to 600 minutes in an atmosphere of nitrogen gas, an inert gas, or a mixed gas of ammonia gas and inert gas. There has been proposed a silicon wafer manufacturing method in which a BMD having a size of 20 nm or less is formed at 1 × 10 ¹⁰ atoms / cm ³ or more by performing rapid heating / cooling heat treatment within the range (Patent Document 2). Further, a silicon wafer having an oxygen concentration of 1.2 × 10 ^{18 to} 1.4 × 10 ¹⁸ atoms / cm ³ and a carbon concentration of 0.5 × 10 ¹⁶ to 2 × 10 ¹⁷ atoms / cm ³ is formed in a non-oxidizing atmosphere. Among them, BMD having a size of 150 nm or less is reduced to 5 by heat treatment under conditions of a temperature rise rate of 0.1 to 1 ° C./min in a temperature range of 1100 to 1250 ° C., a time of 1 to 5 hours, and a temperature range of 1100 to 1250 ° C. A silicon wafer manufacturing method in which × 10 ⁹ atoms / cm ³ or more is formed has also been proposed (Patent Document 3). In addition, a silicon wafer in which BMD having a high concentration (1 × 10 ¹⁰ atoms / cm ³ to 1 × 10 ¹² atoms / cm ³ ) is generated by repeating several heat treatments has been proposed (Patent Document 4).
JP-A-10-98047 JP 2006-40980 A JP 2006-269896 A Japanese Patent Laid-Open No. 08-213403

  However, in recent years, as silicon wafers have increased in diameter and the degree of integration of semiconductor device patterns has increased, warpage generated in the wafer has become a problem in addition to the occurrence of slip dislocations.

  A schematic diagram of a typical example of slip and warpage introduced by heat treatment is shown in FIG. There are roughly two types of heat treatment furnaces: a batch heat treatment furnace and an RTA (Rapid Thermal Annealer). As shown in FIG. 1, the slip is introduced from the contact point between the back surface of the silicon wafer and the silicon wafer holding portion or the silicon wafer edge portion. The introduced slip extends in the 110 direction, and in some cases, causes damage or destruction of the silicon wafer. Warpage is a phenomenon in which a silicon wafer is deformed by thermal distortion during heat treatment. When the warped silicon wafer is viewed from above, for example, as shown in FIG. 1, the center portion of the wafer is recessed in a valley shape and becomes lower than the edge portion. Usually, warpage of a silicon wafer before heat treatment for imparting desired characteristics is suppressed to 10 μm or less. However, when heat treatment is applied, the difference in height between the peaks and valleys of the silicon wafer may reach several tens of μm. When the warpage becomes large, the semiconductor device pattern cannot be accurately exposed on the wafer surface, which causes a decrease in the yield of semiconductor devices. Since the method of applying thermal strain differs between the batch type heat treatment furnace and the RTA, the method of generating warpage and slip is different. In general, RTA tends to cause slip, and batch type heat treatment furnace tends to warp.

  The problem of warpage is remarkable when the wafer diameter is 200 mm or more, and cannot be avoided by simply defining the BMD concentration at a high concentration as described above.

  Therefore, the problem to be solved by the present invention is to provide a silicon wafer manufacturing method that has a DZ layer of an appropriate width and can suppress both occurrence of slip dislocation and warpage in the device manufacturing process. is there.

The inventions according to the present application include the following inventions (1) to (5).
(1) including a step of performing heat treatment on a silicon single crystal substrate (hereinafter simply referred to as “substrate”),
The change amount ΔCs (atoms / cm ³ ) of the substitutional carbon concentration (atoms / cm ³ ) before and after the heat treatment is 1.0 × 10 ¹⁵ atoms / cm ³ or more and 1.0 × 10 ¹⁷ atoms / cm ³ or less. was adjusted in the range, and the interstitial oxygen concentration (atoms / cm ³⁾ of the variation ΔOi (atoms / cm ³⁾ to 1.0 × ¹⁰ 17 atoms / cm ³ or more 6.0 × ¹⁰ 17 atoms / cm ³ or less of A silicon wafer manufacturing method that adjusts in a range,
The interstitial oxygen concentration Oi is 7.5 × 10 ¹⁷ atoms / cm ³ or more and 9.5 × 10 ¹⁷ atoms / cm ³ or less, and the substitutional carbon concentration Cs is 2.0 × 10 ¹⁵ atoms / cm ³ or more and 2.0 ×. Using a substrate of 10 ¹⁷ atoms / cm ³ or less,
The step of performing the heat treatment includes
A: a low-temperature heat treatment step for heat treatment with a holding temperature T1 of 650 ° C. to 800 ° C. and a holding time H of 10 minutes to 4 hours,
B: Following the low temperature heat treatment step (A), the maximum temperature T2 is set to T1 + 50 ° C. to 1000 ° C., and the temperature rising rate R up to the maximum temperature T2 is set to 0.1 ° C./min to 2 ° C./min. A temperature raising step,
C: After the temperature raising step (B), the take-out temperature T3 when taking out the substrate is set to 600 ° C. or more and 800 ° C. or less, and when T3 is lower than T2, the temperature is 1 ° C./min or more and 10 ° C./min or less. Lowering the temperature of the furnace at the temperature lowering rate, taking out the substrate from the furnace at the take-off temperature T3 and cooling it to room temperature, and D: After the temperature lowering / outtake process (C), the furnace temperature is 600 ° C or higher The wafer is inserted into the furnace at a temperature of 800 ° C. or lower, the temperature range from the temperature at the time of wafer insertion to less than 1100 ° C. is raised at a temperature increase rate of 5 ° C./min to 10 ° C./min, and The temperature range from 1100 ° C. to 1250 ° C. is to raise the temperature of the furnace at a rate of temperature rise of 1 ° C./min to 2 ° C./min, and to maintain the furnace temperature at a constant temperature of 1000 ° C. to 1250 ° C. Including high temperature heat treatment process A method for producing a silicon wafer.

(2) A silicon wafer manufacturing method including a step of heat-treating a substrate,
The range of variation ΔOi variation ΔCs (atoms / cm ³⁾ interstitial oxygen concentration of substitutional carbon concentration after heat treatment before heat treatment ^{(atoms / cm 3) (atoms} / cm 3) (atoms / cm 3) ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁵ atoms / cm ³ or more,
And ΔOi (atoms / cm ³ ) is 1.0 × 10 ¹⁷ atoms / cm ³ or more,
And the manufacturing method of the silicon wafer characterized by satisfy | filling the relationship of (DELTA) Cs> = 2.0 * 10 < ¹³ > * exp ((DELTA) Oi * 1.5 * 10 < ^-17 >).

(3) Interstitial oxygen concentration Oi is 7.5 × 10 ¹⁷ atoms / cm ³ or more and 9.5 × 10 ¹⁷ atoms / cm ³ or less and substitutional carbon concentration Cs is 2.0 × 10 ¹⁵ atoms / cm ³ or more 2 Using a substrate of less than 0.0 × 10 ¹⁶ atoms / cm ³ ,
The step of performing the heat treatment includes
A: a low temperature heat treatment step in which heat treatment is performed at a holding temperature T1 of 650 ° C. to 750 ° C. and a holding time H of 10 minutes to 4 hours,
B: Following the low-temperature heat treatment step (A), the maximum temperature T2 is set to T1 + 50 ° C. or more and 850 ° C. or less, and the temperature increase rate R to the maximum temperature T2 is set to 0.5 ° C./min or more and 2 ° C./min or less. A temperature raising step,
C: After the temperature raising step (B), the take-out temperature T3 when taking out the substrate is set to 600 ° C. or more and 800 ° C. or less, and when T3 is lower than T2, it is 1 ° C./min or more and 10 ° C./min or less. Lowering the temperature of the furnace at the temperature lowering rate, taking out the substrate from the furnace at the take-off temperature T3 and cooling it to room temperature, and D: After the temperature lowering / outtake process (C), the furnace temperature is 600 ° C or higher The wafer is inserted into the furnace at a temperature of 800 ° C. or less, and the temperature range from the temperature at the time of wafer insertion to less than 1100 ° C. is raised at a temperature increase rate of 5 ° C./min or more and 10 ° C./min or less, and The temperature range from 1100 ° C. to 1250 ° C. is to raise the temperature of the furnace at a rate of temperature rise of 1 ° C./min to 2 ° C./min, and to maintain the furnace temperature at a constant temperature of 1000 ° C. to 1250 ° C. Including high temperature heat treatment process The manufacturing method of (2) characterized by the above-mentioned.

(4) A method for producing a silicon wafer, including a step of heat-treating a substrate,
The range of variation ΔOi variation ΔCs (atoms / cm ³⁾ interstitial oxygen concentration of substitutional carbon concentration after heat treatment before heat treatment ^{(atoms / cm 3) (atoms} / cm 3) (atoms / cm 3) ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁶ atoms / cm ³ or more,
And ΔOi (atoms / cm ³⁾ is 1.0 × ¹⁰ 17 atoms / cm ³ or more,
And the manufacturing method of the silicon wafer characterized by satisfy | filling the relationship of (DELTA) Cs> = 2.0 * 10 < ¹³ > * exp ((DELTA) Oi * 1.5 * 10 < ^-17 >).

(5) Interstitial oxygen concentration Oi is 7.5 × 10 ¹⁷ atoms / cm ³ or more and 9.5 × 10 ¹⁷ atoms / cm ³ or less, and substitutional carbon concentration Cs is 2.0 × 10 ¹⁶ atoms / cm ³ or more 2 Using a substrate of 0.0 × 10 ¹⁷ atoms / cm ³ or less,
The step of performing the heat treatment includes
A: a low temperature heat treatment step in which heat treatment is performed with a holding temperature T1 of 700 ° C. to 800 ° C. and a holding time H of 10 minutes to 4 hours,
B: Following the low temperature heat treatment step (A), the maximum temperature T2 is increased from T1 + 50 ° C. to 900 ° C., and the temperature increase rate R up to the maximum temperature T2 is increased from 0.5 ° C./min to 2 ° C./min. A temperature raising step,
C: After the temperature raising step (B), the take-out temperature T3 when taking out the substrate is set to 600 ° C. or more and 800 ° C. or less, and when T3 is lower than T2, it is 1 ° C./min or more and 10 ° C./min or less. Lowering the temperature of the furnace at the temperature lowering rate, taking out the substrate from the furnace at the take-off temperature T3 and cooling it to room temperature, and D: After the temperature lowering / outtake process (C), the furnace temperature is 600 ° C or higher The wafer is inserted into the furnace at a temperature of 800 ° C. or less, and the temperature range from the temperature at the time of wafer insertion to less than 1100 ° C. is raised at a temperature increase rate of 5 ° C./min or more and 10 ° C./min or less, and The temperature range from 1100 ° C. to 1250 ° C. is to raise the temperature of the furnace at a rate of temperature rise of 1 ° C./min to 2 ° C./min, and to maintain the furnace temperature at a constant temperature of 1000 ° C. to 1250 ° C. Including high temperature heat treatment process The manufacturing method of (4) characterized by the above-mentioned.

  According to the manufacturing method of the present invention, by controlling the interstitial oxygen concentration of the substrate, the substitutional carbon concentration, and the heat treatment conditions, it is possible to suppress both generation of slip dislocation and warpage in the device manufacturing process. Wafers can be manufactured.

Hereinafter, the present invention will be described in detail according to embodiments.
[First embodiment]
FIG. 2 is a flowchart showing a series of heat treatment steps in the production method of the present invention. FIG. 3 is a diagram showing a curve (time-temperature curve) of how the heat treatment temperature changes with time in the production method of the present invention.
In the first embodiment, before the normal annealing treatment (high-temperature heat treatment step (D)) is performed on the substrate, the heat treatment ((A) to (C)) is performed at a temperature lower than usual, thereby performing the heat treatment and the heat treatment. The amount of change ΔCs (atoms / cm ³ ) in the subsequent substitutional carbon concentration (atoms / cm ³ ) is adjusted in the range of 1.0 × 10 ¹⁵ atoms / cm ^{3 to} 1.0 × 10 ¹⁷ atoms / cm ^3. And the change amount ΔOi (atoms / cm ³ ) of the interstitial oxygen concentration (atoms / cm ³ ) is adjusted in the range of 1.0 × 10 ¹⁷ atoms / cm ³ or more and 6.0 × 10 ¹⁷ atoms / cm ³ or less. It is characterized by that.

This is based on the knowledge described below by the present inventors. That is, when ΔOi is set to 1.0 × 10 ¹⁷ atoms / cm ³ or more, the occurrence of slip can be extremely suppressed (typically 15 mm or less) in a general device manufacturing process. This also prevents the silicon wafer surface from penetrating even if a slip occurs from the wafer support part in the device manufacturing process. Even if a slip occurs on the wafer edge part, the slip reaches the semiconductor device creation region. It was possible to prevent the adverse effects on the device. This is because BMD having a high density and a sufficient size is formed inside the annealed wafer whose ΔOi is 1.0 × 10 ¹⁷ atoms / cm ³ or more, which prevents the progress of slip. I think that the.

Further, by setting ΔCs to 1.0 × 10 ¹⁵ atoms / cm ³ or more, a warp increase amount in a general device manufacturing process = (warp amount after process−warp amount before process) is reduced (typically Is 50 μm or less). This is presumably because carbon was taken into the BMD inside the annealed wafer, and as a result, generation of dislocations from the BMD was suppressed.

In order to set ΔOi to 1.0 × 10 ¹⁷ atoms / cm ³ or more and ΔCs to 1.0 × 10 ¹⁵ atoms / cm ³ or more, it is preferable that the number of BMDs is large, typically 5 × 10. It is desirable that there are ¹¹ / cm ³ or more. When BMD is less than 5 × 10 ¹¹ / cm ³ , ΔOi is less than 1.0 × 10 ¹⁷ atoms / cm ³ or ΔCs is less than 1.0 × 10 ¹⁵ atoms / cm ^{3 even} under the heat treatment conditions described later. In some cases, ΔOi and ΔCs cannot be easily controlled.
Note that the upper limit of ΔOi and the upper limit of ΔCs are defined by the upper limit of the interstitial oxygen concentration of the substrate or the substitutional carbon concentration, as will be described later.

The substrate has an interstitial oxygen concentration Oi of 7.5 × 10 ¹⁷ atoms / cm ³ or more and 9.5 × 10 ¹⁷ atoms / cm ³ or less, and a substitutional carbon concentration Cs of 2.0 × 10 ¹⁵ atoms. / Cm ³ or more and 2.0 × 10 ¹⁷ atoms / cm ³ or less are used.

Here, when the interstitial oxygen concentration is less than 7.5 × 10 ¹⁷ atoms / cm ³ , ΔOi cannot be 1.0 × 10 ¹⁷ atoms / cm ³ or more, and the substitutional carbon concentration is 2. When it is less than 0 × 10 ¹⁵ atoms / cm ³ , ΔCs cannot be 1.0 × 10 ¹⁵ atoms / cm ³ or more. It is difficult to stably produce crystals having an interstitial oxygen concentration exceeding 9.5 × 10 ¹⁷ atoms / cm ³ , and the substitutional carbon concentration is exceeding 2.0 × 10 ¹⁷ atoms / cm ^3. In this case, polycrystallization tends to occur, which is not preferable. When the interstitial oxygen concentration of the substrate is 9.5 × 10 ¹⁷ atoms / cm ³ or less, ΔOi does not exceed 6.0 × 10 ¹⁷ atoms / cm ^3, and the substitutional carbon concentration of the substrate is , 2.0 × 10 ¹⁷ atoms / cm ³ or less, ΔCs does not exceed 1.0 × 10 ¹⁷ atoms / cm ³ .

  A series of heat treatments including a low temperature heat treatment step (A), a temperature rise step (B), a temperature drop / removal step (C), and a high temperature heat treatment step (D) are performed on the substrate. This will be described in order below.

Low-temperature heat treatment step (A): Heat treatment is performed on the unheated substrate at a holding temperature T1 of 650 ° C. to 800 ° C. and a holding time H of 10 minutes to 4 hours. By this low-temperature heat treatment step (A), high-density BMD (typically 5 × 10 ¹¹ / cm ³ or more) is formed inside the annealed wafer, ΔOi is 1.0 × 10 ¹⁷ atoms / cm ³ or more, and ΔCs can be set to 1.0 × 10 ¹⁵ atoms / cm ³ or more. Here, when the holding temperature T1 is less than 650 ° C. or more than 800 ° C., or when the holding time H is less than 10 minutes, the BMD density is less than 5 × 10 ¹¹ / cm ³ , so ΔOi is 1.0. × 10 ¹⁷ atoms / cm ³ or more and ΔCs cannot be made 1.0 × 10 ¹⁵ atoms / cm ³ or more. There is no particular upper limit on the holding time H1, but if it exceeds 4 hours, the production process becomes longer and the productivity is lowered, which is not preferable.

Temperature rising step (B): After the low temperature heat treatment (A), the maximum temperature T2 is set to T1 + 50 ° C. or more and 1000 ° C. or less, and the temperature rising rate R to the maximum temperature T2 is 0.1 ° C./min or more and 2 ° C./min or less. And raise the temperature. By this temperature raising step (B), the BMD generated by the low temperature heat treatment is enlarged so that it does not disappear even in the high temperature heat treatment step (D). At the same time, ΔOi and ΔCs after annealing are adjusted in this step. When the maximum temperature T2 is less than T1 + 50 ° C. and when the temperature rising rate R is more than 2 ° C./min, the BMD does not grow sufficiently, so the BMD disappears in the high temperature heat treatment step (D). As a result, the BMD density is less than 5 × 10 ¹¹ / cm ³ . As the maximum temperature T2 increases, ΔOi and ΔCs increase, but when the maximum temperature T2 exceeds 1000 ° C., ΔOi and ΔCs no longer increase. As the heating rate R decreases, ΔOi and ΔCs increase. However, if the heating rate is less than 0.1 ° C./min, a stable temperature rising rate cannot be secured, which is not preferable.

  Temperature drop / takeout step (C): After the temperature rise step (B), the takeout temperature T3 when taking out the substrate is set to 600 ° C. or higher and 800 ° C. or lower. The temperature of the furnace is lowered at a temperature lowering rate of 10 ° C./min or less, and the substrate is taken out from the furnace at the take-out temperature T3 and cooled to room temperature. When the temperature of the furnace when the substrate is taken out from the furnace is less than 600 ° C., it is not preferable because the life of the heater of the furnace is shortened, and when it exceeds 800 ° C., the members of the furnace are deteriorated. The temperature lowering rate is preferably 1 ° C./min or more and 10 ° C./min or less which can be realized in a general furnace.

By performing the heat treatment steps (A) to (C), it is possible to form a BMD of 5 × 10 ¹¹ / cm ³ or more in the substrate and keep ΔOi and ΔCs within a predetermined range. It becomes.

  High-temperature heat treatment step (D): After the temperature lowering / removal step (C), the temperature of the furnace is set to 600 ° C. or higher and 800 ° C. or lower, and the wafer is inserted into the furnace. The temperature of the furnace is increased at a temperature increase rate of 5 ° C./min to 10 ° C./min, and the temperature range of 1100 ° C. to 1250 ° C. is 1 ° C./min to 2 ° C./min. The temperature of the furnace is raised and the temperature of the furnace is kept at a constant temperature at a temperature of 1000 ° C. or higher and 1250 ° C. or lower. The time for holding in this temperature range is not particularly limited, but may be in the range of the time required for normal annealing (for example, 10 minutes to 2 hours).

By this high-temperature heat treatment step (D), interstitial oxygen is diffused outward to form a DZ layer (typically 5 μm or more) having an appropriate width on the silicon wafer surface. In this step, the furnace temperature when the wafer is inserted is not preferably less than 600 ° C. or more than 800 ° C. for the same reason as (C). The heating rate up to less than 1100 ° C. is preferably 5 ° C./min or more and 10 ° C./min or less which can be realized in a general furnace, and the heating rate of 1100 ° C. or more is preferably 1 ° C./min or more and 2 ° C./min. If the holding temperature is less than 1000 ° C., it will take a long time for the outward diffusion of interstitial oxygen, which is not preferable from the viewpoint of productivity reduction. If the holding temperature exceeds 1250 ° C., the deterioration of the member of the annealing furnace becomes severe. Absent. There are no particular restrictions on the temperature drop rate and the extraction temperature after the high temperature heat treatment.
According to the silicon wafer manufactured in this manner, both slip dislocation and warpage in the device manufacturing process can be suppressed.

[Second embodiment]
In the second embodiment of the manufacturing method of the present invention, the change amount ΔCs (atoms / cm ³ ) of the substitutional carbon concentration (atoms / cm ³ ) before and after the heat treatment and the interstitial oxygen concentration (atoms) with respect to the substrate. / Cm ³ ) of change ΔOi (atoms / cm ³ ) is ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁵ atoms / cm ³ or more,
And ΔOi (atoms / cm ³ ) is 1.0 × 10 ¹⁷ atoms / cm ³ or more,
In addition, heat treatment is performed so as to satisfy the relationship of ΔCs ≧ 2.0 × 10 ¹³ × exp (ΔOi × 1.5 × 10 ⁻¹⁷ ).

This is based on the knowledge described below by the present inventors. That is, ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁵ atoms / cm ³ or more, and ΔCs ≧ 2.0 × 10 ¹³ × exp (ΔOi × 1.5 × 10 ⁻¹⁷ ) is satisfied. By doing so, the amount of warpage increase in a general device manufacturing process = (the amount of warpage after the process−the amount of warpage before the process) can be further reduced (typically 10 μm or less). This is considered to be because the dislocation suppression effect by the carbon incorporated into the BMD inside the annealed wafer becomes larger by satisfying the above relationship.

As a specific heat treatment method, the same method as the heat treatment of the first embodiment (see FIGS. 2 and 3) can be exemplified. However, a substrate having a substitutional carbon concentration Cs of 2.0 × 10 ¹⁵ atoms / cm ³ or more and less than 2.0 × 10 ¹⁶ atoms / cm ³ is used, and the holding temperature in the low-temperature heat treatment step (A) is used. T1 is 650 ° C. or more and 750 ° C. or less, and the maximum temperature T2 in the temperature raising step (B) is T1 + 50 ° C. or more and 850 ° C. or less, and the temperature raising rate R is 0.5 ° C./min or more and 2 ° C./min. The following.

Here, for the substitutional carbon concentration Cs of the substrate 2.0 × ¹⁰ 16 atoms / cm less than ^3, the Cs becomes 2.0 × ¹⁰ 16 atoms / cm ³ or more, since the behavior of precipitation changes , ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁵ atoms / cm ³ or more, and ΔCs ≧ 2.0 × 10 ¹³ × exp (ΔOi × 1.5 × 10 ⁻¹⁷ ) This is because the conditions are different. Further, to the holding temperature T1 below 750 ° C. 650 ° C. or higher, using the substrate of the substitutional carbon concentration range is to the BMD density 5 × ¹⁰ 11 / cm ³ or more. The maximum temperature T2 is set to 850 ° C. or lower and the temperature rising rate R is set to 0.5 ° C./min or higher by using a substrate having the above substitutional carbon concentration range, ΔCs ≧ 2.0 × 10 ¹³ × This is to satisfy the relationship exp (ΔOi × 1.5 × 10 ⁻¹⁷ ).
By this heat treatment, it is possible to manufacture a wafer in which ΔCs and ΔOi are within the above values and satisfy the above relationship.
According to the silicon wafer manufactured in this manner, both slip dislocation and warpage in the device manufacturing process can be suppressed.

[Third embodiment]
In the third embodiment of the manufacturing method of the present invention, the change amount ΔCs (atoms / cm ³ ) and the interstitial oxygen concentration (atoms) of the substitutional carbon concentration (atoms / cm ³ ) before and after the heat treatment are applied to the substrate. / Cm ³ ) of change ΔOi (atoms / cm ³ ) is ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁶ atoms / cm ³ or more,
And ΔOi (atoms / cm ³ ) is 1.0 × 10 ¹⁷ atoms / cm ³ or more,
And ΔCs ≧ 2.0 × 10 ¹³ × exp (ΔOi × 1.5 × 10 ⁻¹⁷ )
Heat treatment is performed so as to satisfy this relationship.

This is based on the knowledge described below by the present inventors. That is, ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁶ atoms / cm ³ or more, and ΔCs ≧ 2.0 × 10 ¹³ × exp (ΔOi × 1.5 × 10 ⁻¹⁷ ) is satisfied. Thus, the amount of warpage increase in a general device manufacturing process = (the amount of warpage after the process−the amount of warpage before the process) can be suppressed to be extremely small (typically 5 μm or less). This is considered to be because the effect of suppressing dislocation due to the carbon incorporated in the BMD inside the annealed wafer becomes extremely large by satisfying the above relationship.

As a specific heat treatment method, the same method as the heat treatment of the first embodiment (see FIGS. 2 and 3) can be exemplified. However, the substrate has a substitutional carbon concentration Cs of 2.0 × 10 ¹⁶ atoms / cm ³ or more and 2.0 × 10 ¹⁷ atoms / cm ³ or less, and the holding temperature in the low-temperature heat treatment step (A). T1 is 700 ° C. or more and 800 ° C. or less, and the maximum temperature T2 in the temperature raising step (B) is T1 + 50 ° C. or more and 900 ° C. or less, and the temperature raising rate R is 0.5 ° C./min or more and 2 ° C./min. The following.

Here, the reason why the substitutional carbon concentration Cs of the substrate is set to 2.0 × 10 ¹⁶ atoms / cm ³ or more is to set ΔCs to 1.0 × 10 ¹⁶ atoms / cm ³ or more. The reason why the holding temperature T1 is set to 700 ° C. or more and 800 ° C. or less is to use the substrate having the above substitutional carbon concentration range so that the BMD density is 5 × 10 ¹¹ / cm ³ or more. The maximum temperature T2 is set to 900 ° C. or less and the temperature rising rate R is set to 0.5 ° C./min or more by using a substrate having the above substitutional carbon concentration range, and ΔCs ≧ 2.0 × 10 ¹³ × This is to satisfy the relationship exp (ΔOi × 1.5 × 10 ⁻¹⁷ ).

By this heat treatment, it is possible to manufacture a wafer in which ΔCs and ΔOi are within the above values and satisfy the above relationship.
According to the silicon wafer manufactured in this manner, both slip dislocation and warpage in the device manufacturing process can be suppressed.

  There are no particular restrictions on the size (diameter, thickness) of the silicon wafer produced according to the present invention and the presence or absence of doping of various elements, and these features are appropriately selected according to the type of semiconductor silicon wafer required. be able to.

  Moreover, there is no restriction | limiting regarding the semiconductor device manufactured using the obtained silicon wafer, It can apply to various semiconductor device manufacture. Specifically, the silicon wafer of the present invention is an epitaxial wafer having an epitaxial layer formed on the surface, a bonded SOI wafer, a SIMOX wafer subjected to SIMOX (Separation By Implanted Oxygen) treatment, or a SiGe wafer having a SiGe layer formed on the surface. It can be widely applied to the manufacture of

Examples will be described below.
[Production method of substrate and annealed wafer]
Single crystal ingots are manufactured under various conditions (wafer diameter, conductivity type, interstitial oxygen concentration, carbon concentration), and the same part of the straight body of each single crystal ingot is cut out using a wire saw and mirror processed. The produced substrate having a thickness of 725 to 750 μm was used as a substrate. Interstitial oxygen concentration Oi of the substrate (atoms / ^cm 3), the carbon concentration Cs (atoms / cm ³⁾ was measured by an infrared absorption method, was used a value of JEITA (Japan Electronics and Information Technology Industries Association) as a conversion factor. That is, the conversion factor of interstitial oxygen concentration is 3.03 × 10 ¹⁷ / cm ² , and the conversion factor of carbon concentration is 8.1 × 10 ¹⁶ / cm ² .

  The obtained substrate was put into a batch type vertical heat treatment furnace and heat-treated in an argon atmosphere. The conditions of the substrate and the heat treatment are shown in Table 1 including examples and comparative examples.

[Measurement and evaluation of annealed wafers]
Measurement and evaluation on the following (1), (2), and (3) were performed for each annealed wafer obtained under the above-described production conditions.

(1) ΔOi and ΔCs of annealed wafer
The interstitial oxygen concentration and carbon concentration of the annealed wafer were measured by an infrared absorption method, and ΔOi and ΔCs were determined by the following methods.
ΔOi = interstitial oxygen concentration of substrate−interstitial oxygen concentration of annealed wafer ΔCs = carbon concentration of substrate−carbon concentration of annealed wafer

(2) Slip length of annealed wafer The annealed wafer was subjected to the following heat treatment.
Heat treatment using RTA (RTA test)
Insert Room temperature Temperature rise 50 ° C./min Hold 1100 ° C. 1 minute Temperature drop 30 ° C./min Draw Room temperature Atmosphere Argon The above heat treatment is repeated 10 times and the annealed wafer after heat treatment is observed with X-ray topograph and the length of the observed slip The maximum length was taken as the slip length.

(3) Increase in warpage of annealed wafer The annealed wafer was subjected to the following heat treatment.
Heat treatment using a batch heat treatment furnace (batch furnace test)
Insert the wafer while maintaining the furnace temperature at 900 ° C. Wafer insertion speed: 50 mm / min Hold the wafer at 900 ° C. for 30 minutes in an oxygen atmosphere and then pull out the wafer at 900 ° C. Wafer extraction speed: 50 mm / min The warpage of the annealed wafer after the heat treatment was measured with FT-90A manufactured by NIDEK, and the amount of warpage increase = (the warp after the heat treatment−the warp before the heat treatment) was determined.

[Each annealing wafer measurement result and evaluation result]
Table 2 shows the measurement results of ΔOi and ΔCs of various annealed wafers.

Table 3 shows the results of the slip length and the amount of warpage increase of various annealed wafers.

FIG. 4 is a diagram in which the above results are plotted on the coordinates with ΔCs on the vertical axis and ΔOi on the horizontal axis.
From the above results, the range of the change amount ΔOi (atoms / cm ³ ) of the interstitial oxygen concentration (atoms / cm ³ ) before and after the heat treatment is 1.0 × 10 ¹⁷ atoms / cm ³ with respect to the substrate. It can be seen that a good silicon wafer having a slip length of 15 mm or less can be obtained by performing the heat treatment as described above.
Further, the range of the change amount ΔCs (atoms / cm ³ ) of the substitutional carbon concentration (atoms / cm ³ ) before and after the heat treatment is such that ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁵ atoms / cm ^3. It can be seen that by performing the heat treatment as described above, a good silicon wafer having an increase in warpage of 50 μm or less can be obtained.
The range of ΔCs is such that ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁵ atoms / cm ³ or more and ΔCs ≧ 2.0 × 10 ¹³ × exp (ΔOi × 1.5 × 10 ⁻¹⁷ ). It can be seen that by performing heat treatment so as to satisfy the relationship, a good silicon wafer having an increase in warpage of 10 μm or less can be obtained.
The range of ΔCs is such that ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁶ atoms / cm ³ or more and ΔCs ≧ 2.0 × 10 ¹³ × exp (ΔOi × 1.5 × 10 ⁻¹⁷ ). It can be seen that by performing heat treatment so as to satisfy the relationship, a good silicon wafer having an increase in warpage of 5 μm or less can be obtained.

Diagram explaining slip and warpage introduced by heat treatment Flow chart showing a series of heat treatment steps in the production method of the present invention The figure which showed the way of the time-dependent change of the heat processing temperature in the manufacturing method of this invention with the curve A plot of measurement results on coordinates with the vertical axis being ΔCs and the horizontal axis being ΔOi.

Claims (5)

Including a step of heat-treating the silicon single crystal substrate,
The change amount ΔCs (atoms / cm ³ ) of the substitutional carbon concentration (atoms / cm ³ ) before and after the heat treatment is 1.0 × 10 ¹⁵ atoms / cm ³ or more and 1.0 × 10 ¹⁷ atoms / cm ³ or less. was adjusted in the range, and the interstitial oxygen concentration (atoms / cm ³⁾ of the variation ΔOi (atoms / cm ³⁾ to 1.0 × ¹⁰ 17 atoms / cm ³ or more 6.0 × ¹⁰ 17 atoms / cm ³ or less of A silicon wafer manufacturing method that adjusts in a range,
The interstitial oxygen concentration Oi is 7.5 × 10 ¹⁷ atoms / cm ³ or more and 9.5 × 10 ¹⁷ atoms / cm ³ or less, and the substitutional carbon concentration Cs is 2.0 × 10 ¹⁵ atoms / cm ³ or more and 2.0 ×. Using a substrate of 10 ¹⁷ atoms / cm ³ or less,
The step of performing the heat treatment includes
A: a low-temperature heat treatment step for heat treatment with a holding temperature T1 of 650 ° C. to 800 ° C. and a holding time H of 10 minutes to 4 hours,
B: Temperature raising step in which the maximum temperature T2 is set to T1 + 50 ° C. or more and 1000 ° C. or less after the low-temperature heat treatment, and the temperature rising rate R to the maximum temperature T2 is set to 0.1 ° C./min or more and 2 ° C./min or less. ,
C: After the temperature raising step, the take-out temperature T3 when taking out the substrate is set to 600 ° C. or higher and 800 ° C. or lower, and when T3 is lower than T2, the temperature lowering rate is 1 ° C./min or higher and 10 ° C./min or lower. A temperature lowering / removing step in which the temperature of the furnace is lowered and the substrate is taken out from the furnace at the take-off temperature T3 and cooled to room temperature. Is inserted into the furnace, and the temperature range from the temperature at the time of wafer insertion to less than 1100 ° C. is to raise the temperature of the furnace at a temperature increase rate of 5 ° C./min to 10 ° C./min and 1100 ° C. to 1250 ° C. Is a high temperature heat treatment process in which the temperature of the furnace is raised at a rate of temperature rise of 1 ° C./min to 2 ° C./min and the furnace temperature is kept at a constant temperature of 1000 ° C. to 1250 ° C. Including, Silicon wafer manufacturing method. A method for producing a silicon wafer comprising a step of heat-treating a silicon single crystal substrate,
The range of variation ΔOi variation ΔCs (atoms / cm ³⁾ interstitial oxygen concentration of substitutional carbon concentration after heat treatment before heat treatment ^{(atoms / cm 3) (atoms} / cm 3) (atoms / cm 3) ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁵ atoms / cm ³ or more,
And ΔOi (atoms / cm ³ ) is 1.0 × 10 ¹⁷ atoms / cm ³ or more,
And the manufacturing method of the silicon wafer characterized by satisfy | filling the relationship of (DELTA) Cs> = 2.0 * 10 < ¹³ > * exp ((DELTA) Oi * 1.5 * 10 < ^-17 >). In the manufacturing method of Claim 2,
The interstitial oxygen concentration Oi is 7.5 × 10 ¹⁷ atoms / cm ³ or more and 9.5 × 10 ¹⁷ atoms / cm ³ or less, and the substitutional carbon concentration Cs is 2.0 × 10 ¹⁵ atoms / cm ³ or more and 2.0 ×. Using a substrate of less than 10 ¹⁶ atoms / cm ³
The step of performing the heat treatment includes
A: a low temperature heat treatment step in which heat treatment is performed at a holding temperature T1 of 650 ° C. to 750 ° C. and a holding time H of 10 minutes to 4 hours,
B: Temperature raising step in which the maximum temperature T2 is set to T1 + 50 ° C. or more and 850 ° C. or less after the low-temperature heat treatment, and the temperature rising rate R to the maximum temperature T2 is set to 0.5 ° C./min or more and 2 ° C./min or less. ,
C: After the temperature raising step, the take-out temperature T3 when taking out the substrate is set to 600 ° C. or higher and 800 ° C. or lower, and when T3 is lower than T2, the temperature lowering rate is 1 ° C./min or higher and 10 ° C./min or lower. A temperature lowering / removing step in which the temperature of the furnace is lowered and the substrate is taken out from the furnace at the take-off temperature T3 and cooled to room temperature. Is inserted into the furnace, and the temperature range from the temperature at the time of wafer insertion to less than 1100 ° C. is to raise the temperature of the furnace at a temperature increase rate of 5 ° C./min to 10 ° C./min and 1100 ° C. to 1250 ° C. Is a high temperature heat treatment process in which the temperature of the furnace is raised at a rate of temperature rise of 1 ° C./min to 2 ° C./min and the furnace temperature is kept at a constant temperature of 1000 ° C. to 1250 ° C. Including, Silicon wafer manufacturing method. A method for producing a silicon wafer comprising a step of heat-treating a silicon single crystal substrate,
The range of variation ΔOi variation ΔCs (atoms / cm ³⁾ interstitial oxygen concentration of substitutional carbon concentration after heat treatment before heat treatment ^{(atoms / cm 3) (atoms} / cm 3) (atoms / cm 3) ΔCs (atoms / cm ³ ) is 1.0 × 10 ¹⁶ atoms / cm ³ or more,
And ΔOi (atoms / cm ³ ) is 1.0 × 10 ¹⁷ atoms / cm ³ or more,
And the manufacturing method of the silicon wafer characterized by satisfy | filling the relationship of (DELTA) Cs> = 2.0 * 10 < ¹³ > * exp ((DELTA) Oi * 1.5 * 10 < ^-17 >). In the manufacturing method of Claim 4,
Interstitial oxygen concentration Oi is 7.5 × 10 ¹⁷ atoms / cm ³ or more and 9.5 × 10 ¹⁷ atoms / cm ³ or less, and substitutional carbon concentration Cs is 2.0 × 10 ¹⁶ atoms / cm ³ or more and 2.0 ×. Using a substrate of 10 ¹⁷ atoms / cm ³ or less,
The step of performing the heat treatment includes
A: a low temperature heat treatment step in which heat treatment is performed with a holding temperature T1 of 700 ° C. to 800 ° C. and a holding time H of 10 minutes to 4 hours,
B: The temperature raising step of raising the temperature by setting the maximum temperature T2 to T1 + 50 ° C. or more and 900 ° C. or less after the low-temperature heat treatment, and the temperature rising rate R to the maximum temperature T2 to 0.5 ° C./min or more and 2 ° C./min or less. ,
C: After the temperature raising step, the take-out temperature T3 when taking out the substrate is set to 600 ° C. or higher and 800 ° C. or lower, and when T3 is lower than T2, the temperature lowering rate is 1 ° C./min or higher and 10 ° C./min or lower. A temperature lowering / removing step in which the temperature of the furnace is lowered and the substrate is taken out from the furnace at the take-off temperature T3 and cooled to room temperature. Is inserted into the furnace, and the temperature range from the temperature at the time of wafer insertion to less than 1100 ° C. is to raise the temperature of the furnace at a temperature increase rate of 5 ° C./min to 10 ° C./min and 1100 ° C. to 1250 ° C. Is a high temperature heat treatment process in which the temperature of the furnace is raised at a rate of temperature rise of 1 ° C./min to 2 ° C./min and the furnace temperature is kept at a constant temperature of 1000 ° C. to 1250 ° C. Including, Silicon wafer manufacturing method.