JP5976030B2 - Heat treatment method for silicon wafer - Google Patents

Description

  The present invention relates to a heat treatment method for a silicon wafer cut out from a silicon ingot grown by the Czochralski method, and the silicon wafer.

  In recent years, with the high integration of semiconductor devices, the crystal perfection in the device active region (depth region from the surface to about 7 μm) of the wafer surface layer relative to the silicon wafer (hereinafter referred to as wafer) used as the substrate. Quality requirements such as improvement of the wafer surface, ensuring sufficient mechanical strength in the wafer surface and inside the wafer (referred to as the bulk, hereinafter referred to as bulk), and quality uniformity over the entire wafer surface. It has become to.

  In order to improve crystal integrity, for example, as shown in Patent Document 1, heat treatment is performed in a batch heat treatment furnace maintained at a high temperature. This heat treatment is performed, for example, in an atmosphere containing hydrogen at a holding temperature lower than 1300 ° C. for 1 minute to 48 hours. When this heat treatment is performed, interstitial oxygen on the surface layer of the wafer is diffused outward to reduce the oxygen concentration. Then, in the vicinity of the wafer surface layer (depth region from the surface to about 10 μm), an inner wall oxide film of a cavity defect (Crystal Originated Particle, hereinafter referred to as COP) which is an agglomeration of vacancies introduced during crystal growth. In addition, the interstitial silicon atoms are injected into the COP to fill the cavities, and the COP can be eliminated, and oxygen precipitates (Bulk Micro Defect, which is a combination of interstitial oxygen and interstitial silicon atoms). Hereinafter, it is referred to as BMD). As a result, a defect-free region (Dedicated Zone, hereinafter referred to as a DZ layer) having no COP or BMD can be formed on the wafer surface layer.

  In the device manufacturing process, exposure is performed using a plurality of masks in sequence. However, there are problems such as overlay that shifts the exposure position and wafer warpage due to thermal stress during the manufacturing process. There is. These problems are known to be closely related to the behavior of dislocations introduced into the wafer. If a BMD having a density higher than a predetermined value is formed in the bulk by the heat treatment, when the dislocation such as slip moves in the bulk, the dislocation is caught by the BMD and the movement may be suppressed. . Thus, by suppressing the movement of dislocations, the strength of the wafer can be improved, and problems such as overlay during the device manufacturing process can be avoided.

  Further, the BMD formed in the bulk also acts as a gettering source for capturing heavy metals attached to the wafer surface during the device manufacturing process. In this way, by forming BMD as a gettering source in the bulk, it is possible to maintain the electrical characteristics such as the lifetime of the device in a good state and to reduce problems related to white scratches.

  In addition, if the BMD size becomes too large, as shown in Non-Patent Document 1, the BMD itself must be a predetermined density or more in order to become a dislocation generation source or to exert the suppression effect. In consideration of this point, the heat treatment conditions for forming the BMD are adjusted.

  A main factor causing non-uniformity in the wafer surface is that an oxidation-induced stacking fault (hereinafter referred to as OSF) region is included in the radial direction of the wafer. This OSF region appears in a ring shape around the crystal pulling axis in the vicinity of a region where the concentration of vacancies taken into the crystal from the silicon melt and the interstitial silicon atoms are just balanced during crystal growth (hereinafter referred to as OSF). It ’s called a ring.) In the vicinity of this OSF ring region, there are very few BMD nuclei introduced into the crystal during crystal growth. For this reason, even if heat treatment is performed on the wafer cut out from this crystal, almost no BMD is formed, and a difference in BMD density occurs between the vicinity of the OSF ring region and the other regions, and the wafer is uniform in the plane. The problem that cannot be secured.

  Therefore, a wafer having an OSF ring region is heat-treated at a temperature lower than 1300 ° C. as described above using a batch-type heat treatment furnace, thereby forming a high-quality DZ layer on the wafer surface layer and increasing the strength. In some cases, the BMD that is effective for improvement is formed in bulk, and the crystal growth history of the wafer in which the OSF ring region exists in the plane is reset to improve the in-plane uniformity of the wafer quality.

JP-A-6-295912

T.A. Ono, et al: ECS Trans. 2 (2006) No. 2 2,109

  In the heat treatment using the batch heat treatment shown in Patent Document 1, in-plane non-uniformity can be improved to some extent, and it is difficult to obtain complete in-plane uniformity. This is presumably because the heat treatment temperature is lower than 1300 ° C., so that undissolved BMD (or BMD nuclei) remains, which is insufficient to reset the crystal growth history. It is conceivable to extend the time of this heat treatment to prevent undissolved BMD, but as the heat treatment is prolonged, crystal defects such as slips occur frequently, the production throughput decreases, and the production cost decreases. It is not realistic because there is a problem of rising.

  In addition, there is a method in which in-plane uniformity is not obtained by heat treatment, but the crystal growth rate is reduced so that the OSF ring is not formed in the wafer surface. However, since a decrease in crystal growth rate directly leads to an increase in manufacturing cost, it is difficult to adopt in a situation where cost reduction demands are high.

  In addition, since heat treatment using a batch heat treatment furnace is generally performed for at least one hour, interstitial oxygen on the wafer surface layer escapes due to outward diffusion to the wafer surface during the heat treatment, and the wafer surface layer. A region having a low interstitial oxygen concentration is formed. This interstitial oxygen is known to have an effect of improving the crystal strength. When the wafer surface layer has a low oxygen concentration, defects are likely to be introduced into the surface layer, which may induce a device leakage failure. Rise.

  Accordingly, an object of the present invention is to improve the in-plane uniformity of crystal quality while ensuring the strength of the surface layer and bulk of a silicon wafer.

  In order to solve the above problems, in the present invention, a silicon wafer cut out from a silicon ingot grown by the Czochralski method is heat-treated in an oxidizing atmosphere at a holding temperature of 1300 ° C. or higher and 1400 ° C. or lower. A first step, a second step of cooling the silicon wafer heat-treated in the first step in an oxidizing atmosphere at a cooling rate of 10 ° C./second to 150 ° C./second, and the silicon cooled in the second step And a third step of heat-treating the wafer in an oxidizing atmosphere at a holding temperature of 800 ° C. to 1250 ° C. for 1 hour to 100 hours.

  In this way, by setting the heat treatment temperature of the wafer to a holding temperature of 1300 ° C. or higher and 1400 ° C. or lower, oxygen precipitates (BMD) introduced during crystal growth can be prevented from remaining undissolved and cavity defects (COP) can be quickly generated. It is possible to manufacture a wafer with high in-plane uniformity in which the crystal growth history is reset by disappearing. In addition, the heat treatment temperature is raised to an ultra-high temperature like the above holding temperature, so that the holding time can be shortened, crystal defects such as slips can be reduced, and the manufacturing throughput is improved to reduce the cost. Can be. Further, by performing this heat treatment in an oxidizing atmosphere, an oxide film (silicon oxide film) is formed on the surface of the wafer, and interstitial silicon atoms are injected into the wafer from this oxide film. By injecting interstitial silicon atoms, COP disappears more rapidly.

  Further, interstitial oxygen is injected from the oxide film into the wafer, and a low oxygen concentration region can be prevented from being formed on the wafer surface layer. For this reason, the strength reduction of the wafer surface layer can be prevented, and problems such as leakage failure can be prevented from occurring in the device. This high-temperature heat treatment at 1300 ° C. or higher can be realized by using a lamp annealing furnace instead of a batch-type heat treatment furnace generally used conventionally.

  In addition, by cooling the wafer that has been heat-treated in the first step within the range of the above cooling rate, it is possible to leave pores having an appropriate concentration in the bulk. By leaving the pores, a BMD having a sufficient size and density necessary for securing bulk strength can be formed in the subsequent heat treatment. If this cooling rate is less than 10 ° C./second, vacancies introduced at a high temperature are lost by pair annihilation or diffusion with interstitial silicon atoms during cooling, so cooling at least 10 ° C./second or more. Need to cool at speed. On the other hand, if the cooling rate is higher than 150 ° C./second, a large thermal stress acts on the wafer and crystal defects such as slips are easily introduced. Therefore, it is necessary to cool at a cooling rate of 150 ° C./second or less. .

  Further, the wafer cooled in the second step is heat-treated at the above holding temperature for the above time, whereby a BMD having a sufficient size and density can be formed in the bulk. At this time, by performing this heat treatment in an oxidizing atmosphere, an oxide film is formed on the wafer surface, and interstitial silicon atoms are implanted into the wafer from this oxide film. The interstitial silicon atoms exert an effect of eliminating the oxygen precipitation nuclei formed on the wafer surface layer in the second step. For this reason, it is possible to prevent the formation of oxygen precipitates on the wafer surface layer, and to ensure the integrity of the DZ layer on the wafer surface layer.

  As described above, each process from the first process to the third process is performed in an oxidizing atmosphere, and an oxide film is formed on the wafer surface, so that the dopant, carbon, metal in the heat treatment member (susceptor, etc.) or the atmospheric gas. Even if impurities such as these are included, the diffusion of these impurities into the wafer can be shielded by this oxide film.

  The configuration further includes a fourth step of heat-treating the silicon wafer heat-treated in the third step in a non-oxidizing atmosphere at a holding temperature of 800 ° C. to 1250 ° C. for 1 hour to 100 hours. Is preferred.

  As described above, the BMD is formed for the purpose of improving the strength of the wafer and imparting gettering ability, but when the heat treatment is completed in the third step performed in an oxidizing atmosphere, the size and density of the BMD are obtained. May be insufficient to exert the gettering ability. This is because, in an oxidizing atmosphere, interstitial silicon atoms are implanted from the wafer surface, and the interstitial silicon atoms exert an action of suppressing BMD nucleation and growth. Therefore, following the third step, a fourth step performed in a non-oxidizing atmosphere is provided, and by suppressing the implantation of interstitial silicon atoms in the fourth step, nucleation and growth of BMD can be promoted. it can. Thereby, sufficient gettering ability can be imparted to the wafer.

In each of the above configurations, the average size of the cavity defects existing in the silicon wafer in the stage before the first step is a diameter of 80 nm or less in a spherical equivalent value of the same volume, and the density of the cavity defects is 100. It is preferable that the number of particles / cm ³ or more.

The size and density of the COP introduced into the wafer (silicon ingot) during crystal growth are the crystal growth conditions (particularly the v / G value, where v is the crystal growth rate (mm / min), and G is near the melting point ( It is closely related to the axial temperature gradient (° C./mm) in the crystal of 1350 ° C. from the melting point) and the concentration of the additive to the silicon melt (particularly nitrogen). When this v / G is set to an appropriate value, the concentration of vacancies introduced from the silicon melt into the ingot and the concentration of interstitial silicon atoms are balanced, and a complete crystal having a very low COP density can be obtained. However, the value of v at this time is generally small, which is disadvantageous from the viewpoint of manufacturing throughput. On the other hand, the growth rate v of a crystal having a COP density of 100 / cm ³ is relatively larger than the growth rate of the complete crystal, and a high production throughput can be secured. For this reason, the manufacturing cost of the wafer can be reduced. Further, by setting the COP size to 80 nm or less, this COP can be surely eliminated by the first heat treatment, and a wafer surface layer with high crystal integrity can be secured.

  In each of the above configurations, the depth of the defect-free layer from the surface of the silicon wafer is changed by changing the cooling rate in the second step or by changing the holding time in the third step. Is preferred.

  In many cases, the depth of the defect-free layer from the wafer surface (the width of the DZ layer) is required to be changed in accordance with the type and application of the device manufactured using the wafer. As described above, wafers corresponding to various devices can be easily manufactured by changing the parameters related to the heat treatment of the wafer such as the cooling rate and the heat treatment time to change the width of the DZ layer. The defect-free layer here refers to a region where there are no defects such as oxygen precipitates and COPs. As a method for detecting the oxygen precipitates, for example, a laser scattering tomograph can be employed.

A silicon wafer that has been heat-treated by the heat treatment method for silicon wafers according to each of the above-described structures, and the average in-plane density of oxygen precipitates in the bulk is 1.0 × 10 ⁹ pieces / cm ³ or more and 1.0 × 10 ¹⁰ pieces / A silicon wafer can be formed, which is equal to or less than cm ³ and has an in-plane variation of the oxygen precipitate density at each depth position from the surface within one digit.

When the in-plane average density of oxygen precipitates (BMD) is lower than 1.0 × 10 ⁹ pieces / cm ^{3, the} gettering ability by this BMD is lowered, and the lifetime is increased when contamination of heavy metals or the like occurs on the wafer. There is a risk of problems such as degradation. In addition, when the in-plane average density of BMD exceeds 1.0 × 10 ¹⁰ atoms / cm ³ , many interstitial oxygen atoms are consumed in the wafer, and the problem of a decrease in wafer strength due to a low oxygen concentration becomes remarkable. There is a fear. Furthermore, by making the in-plane variation of the BMD density within one digit, in-plane uniformity of the wafer quality can be achieved, and crystal defects such as slips are caused by the presence of non-uniform BMD in the surface. It can prevent as much as possible.

In addition, by setting the in-plane average density of BMD within the range of 4.0 × 10 ⁹ pieces / cm ³ or more and 1.0 × 10 ¹⁰ pieces / cm ³ or less, the strength improvement effect and gettering ability by this BMD can be obtained. This can be further improved.

  In the silicon wafer, it is preferable that the size of 90% or more of the oxygen precipitates in the bulk is in a range of 35 to 75 nm.

  As described above, while BMD has advantages such as an effect of improving the strength of the wafer, if the size is too large, this BMD itself may cause a dislocation generation source. Therefore, by controlling the size range of oxygen precipitates (BMD) as described above, the BMD generates crystal defects such as dislocations from the BMD while ensuring the effect of improving the strength of the wafer and ensuring the gettering ability. It is possible to prevent the quality from deteriorating.

  In the present invention, the wafer is heat-treated at a holding temperature of 1300 ° C. or higher and 1400 ° C. or lower in an oxidizing atmosphere, and the wafer heat-treated in the first step is 10 ° C./second or higher and 150 ° C./second or lower. A second step of cooling at a cooling rate of, and a third step of heat-treating the wafer cooled in the second step in an oxidizing atmosphere at a holding temperature of 800 ° C. to 1250 ° C. for 1 hour to 100 hours. A wafer heat treatment method is provided. According to this configuration, by performing the first step at the above holding temperature, it is possible to reset the crystal growth history such as in-plane distribution of BMD and COP, and to improve the in-plane uniformity of crystal quality.

  Further, by performing the first step in an oxidizing atmosphere, it is possible to prevent the oxygen concentration of the wafer surface layer and to secure the strength of the surface layer. Furthermore, by performing the first to third steps in an oxidizing atmosphere, interstitial silicon atoms are implanted into the wafer, and a BMD having a sufficient size and density can be formed while forming a good DZ layer.

The figure which shows the sequence of the heat processing method of the silicon wafer which concerns on this invention The figure which shows the behavior of COP and BMD when the 1st heat treatment concerning this invention is performed Diagram showing the behavior of COP and BMD when heat treatment is performed in a general batch heat treatment furnace Diagram showing behavior of vacancies and interstitial silicon atoms in wafer It is a figure which shows the behavior of a void | hole and an interstitial silicon atom when heat-processing to a wafer, Comprising: (a) after holding | maintenance at the holding temperature of 1st heat processing, (b) after cooling of 1st heat processing, (C) after the completion of the second heat treatment (oxidizing atmosphere) It is a figure which shows the behavior of a void | hole and an interstitial silicon atom when heat-processing to a wafer, Comprising: (a) after holding | maintenance at the holding temperature of 1st heat processing, (b) after cooling of 1st heat processing, (C) after completion of the second heat treatment (non-oxidizing atmosphere) The figure which shows the wafer depth direction distribution of oxygen concentration when heat-treating a wafer The result of in-plane distribution evaluation of BMD when the heat treatment according to the present invention is performed is shown, (a) is the center of the wafer, (b) is 75 mm from the center, (c) is 100 mm from the center, (d) is from the center. 120mm, (e) is 140mm from the center, (f) is 147mm from the center The figure which shows the wafer depth direction distribution of BMD density when heat processing concerning this invention are performed The figure which shows the wafer depth direction distribution of BMD size when the heat processing which concerns on this invention is performed The figure which shows the width of BMD size, BMD density, and DZ layer when changing the cooling rate of the first heat treatment The results of evaluation of in-plane distribution of BMD when performing general heat treatment for growing BMD in a batch heat treatment furnace are shown. (A) is the center of the wafer, (b) is 75 mm from the center, and (c) is from the center. 100mm, (d) is 120mm from the center, (e) is 140mm from the center, (f) is 147mm from the center The figure which shows the wafer depth direction distribution of the BMD density at the time of performing the general heat treatment which grows BMD in a batch type heat treatment furnace The figure which shows the wafer depth direction distribution of BMD size at the time of performing the general heat treatment which grows BMD in a batch type heat treatment furnace The figure which shows the wafer depth direction distribution of a void | hole and an interstitial silicon atom when performing the 1st heat processing which concerns on Example 1. FIG. The figure which shows the wafer depth direction distribution of a void | hole and the interstitial silicon atom at the time of performing the 1st heat processing which concerns on the comparative example 1 The figure which shows the wafer depth direction distribution of a void | hole and an interstitial silicon atom when performing the 1st heat processing which concerns on the comparative example 2

(1) About the heat processing sequence which concerns on this invention An example of the sequence of the heat processing method of the silicon wafer (henceforth a wafer) which concerns on this invention is shown in FIG. This heat treatment method is configured by successively performing two heat treatments, a first heat treatment HT ₁ using a lamp annealing furnace and a second heat treatment HT ₂ using a batch heat treatment furnace.

Although not shown in the figure, following the first heat treatment HT _1, the step of peeling is provided an oxide film formed on the wafer surface. This peeling process may be omitted. Subsequent to the second heat treatment HT ₂ , double-side polishing (about 5 to 6 μm per side) of the front and back surfaces of the wafer and single-side polishing (about 1 μm) of the wafer surface are performed. By performing this polishing, the roughness of the wafer is improved, and COP and BMD (described later) remaining on the extreme surface layer (in the range of about 1 μm from the surface) of the wafer after the first heat treatment can be removed. The polishing process may be appropriately changed, such as omitting single-side polishing and performing only double-side polishing, or omitting double-side polishing and performing only single-side polishing. After the polishing process, it is shipped as a product through a wafer cleaning process and an inspection process.

Hereinafter, the influence of the first heat treatment HT ₁ and the second heat treatment HT _{2 on} the behavior of point defects in the wafer will be described in detail.

(A) First Heat Treatment As shown in FIG. 1, the first heat treatment HT ₁ is first carried into a lamp annealing furnace having the wafer in an oxidizing atmosphere and heated to a holding temperature T ₁ at a temperature rising rate R _1. To do. Next, for a predetermined period of time the wafer at a holding temperature T _1. After the wafer is held at the holding temperature T ₁ for the holding time D ₁ , it is cooled at the cooling rate R ₂ .

Holding the wafer at a high temperature holding temperature _{T 1,} as shown in FIG. 2, the interstitial oxygen concentration in the wafer (a typical ^{wafer, (1~20) × 10 17 atoms} / cm 3 (old ASTM)) Rather than the solubility of interstitial oxygen at that holding temperature (for example, 21 × 10 ¹⁷ atoms / cm ³ (old ASTM) at 1300 ° C.), and the interstitial oxygen in the wafer is in an unsaturated state. Become. Then, BMD which is an oxide of silicon gradually dissolves and finally disappears. Further, the inner wall oxide film of the COP is dissolved, and interstitial silicon atoms are injected into the wafer from the oxide film formed on the wafer surface, so that the cavity of the COP is gradually filled and finally disappears. This disappearance effect of BMD and COP occurs not only on the wafer surface layer but also in the entire thickness direction of the wafer, so that the crystal growth history is reset and a wafer with high in-plane uniformity can be obtained.

Since the first heat treatment HT ₁ is performed in an oxidizing atmosphere, an oxide film is formed on the wafer surface, and interstitial oxygen having a concentration higher than the solubility at the holding temperature T ₁ of the first heat treatment HT ₁ is generated from the oxide film. It is injected (see the rising portion of the oxygen concentration distribution on the surface layer in FIG. 2). As described above, the oxygen concentration in the surface layer becomes high, and as a result, the inner surface oxide film of the COP and the BMD remain undissolved in the extreme surface layer (in the range of about 1 μm from the surface) of the wafer. Even if COP or the like remains in this way, as described above, the surface layer of the wafer is removed by polishing, including the remaining layer of COP or the like, for the purpose of improving roughness. There is no problem at all.

  On the other hand, when the wafer is heat-treated using a conventional batch-type heat treatment furnace, interstitial oxygen diffuses outward from the wafer surface during the heat treatment, and the interstitial oxygen concentration on the wafer surface layer decreases, as shown in FIG. To do. For this reason, in the surface layer of the wafer, the effect of annihilation of BMD and COP is exhibited, but in the bulk, interstitial oxygen is in a supersaturated state as compared with the solubility, so that BMD and COP cannot be eliminated. . For this reason, the crystal growth history cannot be reset, and when there is non-uniformity in the wafer surface, the state remains as it is even after the heat treatment.

The behavior of point defects (interstitial silicon atoms I, vacancies V) in the first heat treatment HT ₁ will be described with reference to FIGS. Holding the wafer at a holding temperature T ₁ of, interstitial silicon atoms I and vacancies V thermal equilibrium concentration corresponding to the holding temperature T ₁ of the wafer surface is injected into the wafer. In addition, since the first heat treatment HT ₁ is performed in an oxidizing atmosphere, an oxide film (silicon oxide film) in which silicon and oxygen are combined is formed on the wafer surface. From the oxide film, interstitial oxygen and excessive interstitial interstices are formed. Silicon atoms I are implanted into the wafer (see FIGS. 4 and 5A).

In the cooling process from the holding temperature, the interstitial silicon atoms I and the vacancies V repeat the phenomenon that they disappear from each other or are newly generated as Frenkel pairs (see FIG. 4). Also, some of the vacancies V combine with interstitial oxygen injected from the silicon surface to form a complex (O ₂ V) near 1050 ° C. in the cooling step, and this complex serves as an oxygen precipitation nucleus. It works (see FIG. 5B).

The oxygen concentration in the oxidizing atmosphere of the first heat treatment HT ₁ may as long as an oxide film on the wafer surface is formed, for example, be in the range of 1% to 100%. By making the range of this oxygen concentration 25% or more and ensuring a sufficient injection amount of interstitial silicon atoms I from the oxide film, the COP disappearance effect can be further enhanced.

Heating rate R ₁ is usually set within the following range 1 ° C. / sec or more 0.99 ° C. / sec. If the temperature rising rate R ₁ is lower than 1 ° C./second, the production throughput is lowered. If the temperature rising rate R ₁ is higher than 150 ° C./second, there may be a problem that crystal defects such as slips occur during the temperature rising. It is.

Holding temperatures T ₁ may be a temperature necessary to extinguish the BMD and COP introduced during crystal growth, can be in the range of 1300 ° C. or higher 1400 ° C. or less. Or unable to extinguish BMD etc. If the holding temperature T ₁ is higher concentration of interstitial oxygen in silicon lower than 1300 ° C., and because sometimes it takes a long time to disappear, holding temperature This is because if T ₁ is higher than 1400 ° C., there may be a problem that crystal defects such as slip occur during heat treatment.

Retention time D ₁ may be any time required to extinguish the BMD and COP introduced during crystal growth, corresponding to the size of the BMD and COP, in the range of less than 600 seconds 1 second be able to. Retention time D ₁ can not be eliminated sufficiently short and BMD like than 1 second, the holding time D ₁ is longer than 600 seconds, the crystal defects of slippage may occur a problem that occurs during the hold It is.

Cooling rate _{R 2} is a 10 ° C. / sec or more 0.99 ° C. / sec or less. When the cooling rate R ₂ is less than 10 ° C./second, the vacancies V introduced at the holding temperature T ₁ are lost due to pair annihilation or diffusion with the interstitial silicon atoms I during cooling. This is because the BMD having a sufficient size and density cannot be formed by the second heat treatment HT ₂ , and if the cooling rate R ₂ is higher than 150 ° C./second, a large thermal stress acts on the wafer to cause crystal defects such as slips. This is because a problem may occur.

(B) Second Heat Treatment As shown in FIG. 1, the second heat treatment HT ₂ first holds the wafer in a batch heat treatment furnace that maintains the furnace temperature at a predetermined temperature (for example, 600 ° C.) and uses an oxidizing atmosphere. loading and, after its loading, to raise the temperature at a predetermined heating rate R ₃ from the predetermined temperature to the holding temperature T _2. Once the furnace temperature reached the holding temperature T _2, the holding at temperature T ₂ First holding time D ₂₁ held as it is. After the lapse of the first hold time D _21, switched to a non-oxidizing atmosphere the atmosphere in the furnace from the oxidizing atmosphere. Then, in the non-oxidizing atmosphere, holding still intact second hold time D _22. After the lapse of the second holding time D _22, Once this from the holding temperature T ₂ to a predetermined temperature (e.g. 600 ° C.) and cooled at a predetermined cooling rate R _4, reaches a predetermined temperature (e.g. 600 ° C.), the wafers from the furnace Take it out.

In the present view, it is shown the structure for switching the atmosphere of a batch type heat treatment furnace in a non-oxidizing atmosphere from the oxidation atmosphere, that throughout the second heat treatment HT _2, and configured to perform heat treatment in an oxidizing atmosphere Is also acceptable. This is because by performing heat treatment in an oxidizing atmosphere, the effect of enhancing the crystal integrity of the wafer surface layer by annihilating BMD nuclei on the wafer surface layer as described later is exhibited. Further, in this view, it is shown for the case where a same holding temperature T ₂ in the oxidizing atmosphere and a non-oxidizing atmosphere, it is also possible to perform the heat treatment in the atmosphere at different temperatures.

The behavior of point defects (vacancies V, interstitial silicon atoms I) in the second heat treatment HT ₂ will be described with reference to FIG. When the wafer subjected to the first heat treatment HT ₁ is subjected to heat treatment in an oxidizing atmosphere, oxygen precipitation nuclei (O ₂ V) formed on the wafer surface layer by the first heat treatment HT ₁ (see this figure (b)). Then, it disappears due to interstitial silicon atoms I implanted into the wafer from the oxide film (see FIG. 4C). This disappearance occurs remarkably in a depth region of about 13 μm from the wafer surface to the inside of the wafer. As described above, the surface of the wafer is polished for the purpose of improving the roughness, but the polishing depth is usually about several μm. If oxygen precipitation nuclei are present in the vicinity of the polishing depth, oxygen precipitates may remain on the wafer surface layer (device active region) even when surface polishing is performed, which may cause problems such as device leakage failure. Therefore, by performing heat treatment in an oxidizing atmosphere with the second heat treatment HT ₂ and eliminating the oxygen precipitation nuclei, it is possible to prevent oxygen precipitates from remaining on the wafer surface when performing surface polishing, and to produce a high-quality wafer. Can be provided.

When the second heat treatment HT ₂ is performed in a non-oxidizing atmosphere, as shown in FIG. 6, the oxygen precipitation nuclei take in the surrounding solid solution oxygen and vacancies and grow as they are as oxygen precipitates (this figure (c)). reference). For this reason, even if the surface polishing is performed, there is a high possibility that oxygen precipitates remain on the wafer surface layer and cause problems such as device leakage failure.

The oxygen concentration in the oxidizing atmosphere of the second heat treatment HT2 _only needs to be such that an oxide film is formed on the wafer surface, and can be, for example, in the range of 1 to 100%. By making this oxygen concentration 25% or more, the effect of eliminating the oxygen precipitation nuclei can be further enhanced. In a non-oxidizing atmosphere, for example, an inert gas such as argon (Ar) can be used.

Heating rate R ₃ is usually set in the range of 1 ° C. / min or higher 30 ° C. / min or less. If the rate of temperature increase is less than 1 ° C./min, the production throughput decreases. If the rate of temperature increase is greater than 30 ° C./min, crystal defects such as slips occur during the temperature increase or are introduced in the first heat treatment HT _1. This is because the problem that the BMD nuclei disappear during heating and a sufficient BMD density cannot be obtained may occur. The heating rate R ₃ is not necessary is constant from the predetermined temperature is carried temperature of the wafer (e.g., 600 ° C.) to the holding temperature T _2, for example, from the predetermined temperature to an intermediate temperature (e.g., 800 ° C.) the first heating rate, said from the intermediate temperature to the holding temperature T ₂ may be changed for each temperature region and so, different second heating rate from said first IchiNoboru rise rate.

Holding temperature T ₂ may be a temperature that can be grown wafer plane uniformly newly introduced BMD nuclei in the first heat treatment HT _1, it can be in the range of 800 ° C. or higher 1250 ° C. or less. This is because if the holding temperature T ₂ is lower than 800 ° C., it takes a long time to grow BMD and the production throughput is lowered. If the holding temperature T ₂ is higher than 1250 ° C., crystal defects such as slips are generated during the heat treatment. This is because a problem may occur.

The holding time D ₂ (D ₂₁ , D ₂₂ ) may be a time required to sufficiently grow BMD, and is 1 hour to 100 hours in an oxidizing atmosphere, and 1 hour to 100 hours in a non-oxidizing atmosphere. It can be as follows. In any atmosphere, if the holding times D ₂₁ and D ₂₂ are shorter than 1 hour, the BMD cannot be sufficiently grown. If the holding times D ₂₁ and D ₂₂ are longer than 100 hours, slipping or the like may occur during holding. This is because a crystal defect may occur and a problem that the manufacturing throughput may be reduced.

Cooling rate _{R 4} is a 0.5 ° C. / min or higher 10 ° C. / min or less. When the cooling rate R ₄ is less than 0.5 ° C./min, the manufacturing throughput is lowered, and when the cooling rate R ₄ is greater than 10 ° C./min, a large thermal stress acts on the wafer to generate crystal defects such as slips. This is because problems may arise.

(2) Experimental conditions In this embodiment, a wafer having a diameter of 300 mm including an OSF ring in a plane cut out from an ingot grown by the Czochralski method was used. The interstitial oxygen concentration of this wafer is 11 × 10 ¹⁷ atoms / cm ³ (old ASTM). Nitrogen is added to the melt used for this growth. This is because nitrogen has the effect of reducing the size of the COP introduced during crystal growth, and the COP can be extinguished in a shorter time in the first heat treatment HT ₁ by reducing the size of the COP. . The nitrogen becomes polarized due析係number is greater toward the top of the ingot in the tail density greatly changes, the top portion is ^{2 × 10 14 atoms / cm 3} , 10 × 10 14 atoms / cm 3 approximately at the tail . A wafer to which nitrogen is not added can also be used.

Table 1 shows processing conditions in the first heat treatment HT ₁ and the second heat treatment HT ₂ . The first heat treatment HT heating rate _{R 1} and the holding time _{D 1} in _1, the second heat treatment HT ₂ heating rate _{R 3} in, and the cooling rate _{R 4} is the same for all the examples and comparative examples. “O ₂ ” in the column of atmosphere means 100% O ₂ atmosphere, and “Ar” means 100% Ar atmosphere. Further, “O ₂ / Ar” described in the column of the atmosphere of the second heat treatment HT ₂ means that the first half is a 100% O ₂ atmosphere and the second half is a 100% Ar atmosphere. In this case, the first and second half holding times (D ₂₁ and D _{22 in} FIG. 1) are described in the column of the holding time D ₂ of the second heat treatment HT ₂ (the first half hatched area is an oxidizing atmosphere (in O ₂ )). the retention time _{D 21,} the second half diagonal lines show the retention times _{D 22} of a non-oxidizing atmosphere (in Ar).).

  The interstitial oxygen concentration in the wafer depth direction after the heat treatment was evaluated using a secondary ion mass spectrometer (Secondary Ion Mass Spectrometry (SIMS), IMS7f manufactured by CAMECA). Moreover, the wafer depth direction distribution of the defect was evaluated using a laser scattering tomograph (Laser Scattering Tomography, MO441 manufactured by Raytex). Furthermore, the defect of the wafer surface layer was evaluated using a surface inspection machine (SurfScan (SP2) manufactured by KLA Tencor). Moreover, the substance of the defect evaluated with the surface inspection machine was analyzed using a scanning electron microscope (Scanning Electron Microscope (SEM)) and an energy dispersive X-ray analyzer (Energy Dispersive X-ray Spectrometry (EDX)).

(3) Evaluation result after performing the first heat treatment HT ₁ and the second heat treatment HT _2, shows a wafer depth direction distribution of oxygen concentration measured by SIMS in FIG. This oxygen concentration is a conversion concentration according to the old ASTM standard. When the first heat treatment HT ₁ is performed in an oxidizing atmosphere (in O ₂ ), an oxide film is formed on the wafer surface, and interstitial oxygen is injected into the wafer from this oxide film. Thus, the interstitial oxygen concentration is particularly high distribution in a depth range of 1~3μm the wafer surface (see A ₁ in the figure). Thus, by performing the first heat treatment HT ₁ in an oxidizing atmosphere and increasing the interstitial oxygen concentration of the wafer surface layer, the strength of the wafer surface layer is improved, and defects are introduced into the wafer surface layer. Leak failure can be prevented from occurring.

After the second heat treatment HT ₂ is performed in a non-oxidizing atmosphere (in Ar) on the wafer having an increased interstitial oxygen concentration in the surface layer, a predetermined amount of the wafer surface layer is polished and removed, and the polished surface is evaluated using SP2. As a result, when the polishing amount was less than 13 μm, a minute defect (Light Point Defect (LPD)) that scattered the SP2 probe light was detected. This LPD was present at a high density in a depth region of 3 to 5 μm from the wafer surface (to the extent that the number of measurements by SP2 overflowed). The composition of the location where LPD was present was analyzed using EDX, and silicon and oxygen were detected. When the analysis result by EDX and the shape observation result by SEM are considered together, it can be said that the substance of LPD is an oxygen precipitate.

The distribution result of the LPD (oxygen precipitate) in the wafer depth direction is consistent with the result of high concentration oxygen detected in a depth region of 2 to 5 μm from the wafer surface in the distribution A ₂₁ shown in FIG. It is reasonable to consider that the origin of this high concentration of oxygen is oxygen precipitates. The reason why oxygen precipitates are formed in a depth region of about several μm to 13 μm (particularly a depth region of 2 to 5 μm) in the vicinity of the wafer surface as described above is that by the first heat treatment HT ₁ as will be described later. The concentration of vacancies V injected into the wafer from the wafer surface exceeds the threshold of 1 × 10 ¹³ / cm ³ required for the formation of oxygen precipitation nuclei (O ₂ V), and the first heat treatment HT ₁ This is considered to be because the newly formed oxygen precipitation nuclei take in the surrounding interstitial oxygen and vacancies V and grow into oxygen precipitates.

  Thus, when oxygen precipitates are formed on the wafer surface layer, oxygen precipitates remain on the wafer surface layer after surface polishing when the surface of the wafer surface is polished by about 5 to 6 μm to improve the roughness of the wafer after heat treatment. It was confirmed by evaluation using SP2. When a device is formed on a wafer in which oxygen precipitates remain on the surface layer in this manner, problems such as leakage defects may occur.

On the other hand, when the first half of the second heat treatment HT ₂ is performed in an oxidizing atmosphere (in O ₂ ) on a wafer having an increased interstitial oxygen concentration in the surface layer (see FIG. 1), an oxide film is formed on the wafer surface. , interstitial silicon atoms I is injected into the wafer during the interface between the oxide film and the silicon to the second heat treatment in HT _2. This interstitial silicon atom I exhibits the action of eliminating the oxygen precipitation nuclei formed on the wafer surface layer by the first heat treatment HT ₁ (see FIG. 5C). For this reason, the second heat treatment HT ₂ forms a region having high crystal integrity without oxygen precipitates on the wafer surface layer, and is sufficient in the bulk where the interstitial silicon atoms I implanted by the second heat treatment HT ₂ do not reach. BMD having a high density can be formed. Even after the heat treatment in the oxidizing atmosphere in the first half and the heat treatment in the non-oxidizing atmosphere in the latter half (see FIG. 1), the rise of the oxygen concentration on the wafer surface layer considered to be caused by oxygen precipitates could not be confirmed ( see _{a 22} in FIG. 7).

Incidentally, when the first heat treatment HT ₁ is performed in a non-oxidizing atmosphere (in Ar), interstitial oxygen diffuses outward from the wafer surface during the first heat treatment HT ₁ and the second heat treatment HT ₂ (B _{1 in} FIG. 7). (Refer to the first heat treatment HT ₁ ), B ₂ (after the second heat treatment HT ₂ ), and since a region having a low interstitial oxygen concentration is formed on the wafer surface layer, the second heat treatment HT ₂ is treated in a non-oxidizing atmosphere (Ar even performed in middle), swelling of the oxygen concentration due to oxygen precipitates was observed in the concentration distribution a ₂₁ was observed. However, since the oxide film is not formed on the wafer surface in the first heat treatment HT _1, not injected interstitial silicon atoms I, the COP of the wafer surface layer it is impossible to sufficiently eliminated.

FIG. 8 shows the evaluation results using the laser scattering tomograph device after the first heat treatment HT ₁ and the second heat treatment HT ₂ were performed on the wafer according to Example 1 (see Table 1). (A) is the wafer center, (b) is 75 mm from the center, (c) is 100 mm from the center, (d) is 120 mm from the center, (e) is 140 mm from the center, and (f) is 147 mm from the center. This is the result.

This wafer contains an OSF ring in the plane in the crystal growth stage, and the in-plane uniformity is not good at first, but the BMD size, BMD density, DZ width, etc. are very high in-plane uniformity. It was confirmed that it was obtained. This is because the BMD introduced at the time of crystal growth disappears in the high-temperature first heat treatment HT ₁ , and after the crystal growth history is reset, new BMD nuclei are uniformly introduced in the plane when the first heat treatment HT ₁ is cooled. It is to be done. Moreover, it was also confirmed by SP2 evaluation and SEM observation that oxygen precipitates were not formed on the wafer surface layer and high crystal integrity was ensured. This is because interstitial silicon atoms I are implanted into the wafer by performing the first half of the second heat treatment HT _{2 in} an oxidizing atmosphere, and the interstitial silicon atoms I are introduced into the wafer surface layer by the first heat treatment HT ₁ . This is because the oxygen precipitation nuclei disappeared (see FIG. 5C).

As shown in FIG. 9, a high-quality DZ layer having almost no oxygen precipitates is formed in a depth region from the wafer surface to about 60 μm, and the BMD density rises from a depth of about 80 μm. First, in the bulk having a depth of about 200 μm or more, the in-plane average density of BMD is 4.0 × 10 ⁹ pieces / cm ³ or more and 1.0 × 10 ¹⁰ pieces / cm ³ or less, and the in-plane variation of the BMD density Was within one digit (within the range of the length of the arrow shown in the figure). By forming a BMD having a high density in this way, it is possible to ensure a high bulk strength and a sufficient gettering ability.

The width of the DZ layer is often required to be changed so as to correspond to the type and application of a device manufactured using this wafer. However, the cooling rate R ₂ in the first heat treatment HT ₁ and the second heat treatment HT _{2 are used.} by changing the holding time D ₂ in, it is possible to change the width freely.

  Moreover, as shown in FIG. 10, it was confirmed that the average size of BMD in the bulk was about 50 nm, and the size of BMD of 90% or more was within the range of 35 to 75 nm. When the size of the BMD is large (for example, 100 nm or more), the BMD itself becomes a dislocation source and the strength of the wafer is lowered, which may cause problems such as overlay in the device manufacturing process. Therefore, by controlling the BMD within the above size range, it is possible to prevent a problem related to a decrease in wafer strength.

First heat treatment HT ₁ (oxidizing atmosphere, holding temperature T ₁ is 1350 ° C., cooling rate R ₂ is 5 to 120 ° C./second) and second heat treatment HT ₂ (oxidizing / non-oxidizing atmosphere, holding temperature T ₂ is 1000 ° C.) The evaluation results of the BMD density, the BMD average size, and the DZ layer width after (Examples 1 to 4, Comparative Example 1) are shown in FIG. As the cooling rate R ₂ decreases, the BMD density decreases. When the cooling rate R ₂ is 5 ° C./second (Comparative Example 1), BMD was hardly confirmed. The width enough DZ layer cooling rate R ₂ becomes small expanded. On the other hand, BMD average size, be varied cooling rate _{R 2} hardly changes were within 45～60Nm.

  As described above, since the crystal growth history can be reset, a low-cost wafer having a relatively high crystal pulling speed and a high manufacturing throughput can be adopted, such as a wafer including an OSF ring. Even if a single-wafer lamp annealing furnace is used instead of a batch-type heat treatment furnace that performs heat treatment at a time, it can stand out in terms of manufacturing cost.

If the holding temperature _{T 1} of the first heat treatment HT ₁ and 1300 ° C. (Examples 5-8) also the holding temperature _{T 1} of similarly to the case of the 1350 ° C., high-quality DZ layer is formed on the wafer surface layer In addition, it was confirmed that BMD having sufficient size and density that can contribute to securing high strength and gettering ability was formed in the bulk. Depending on the size of the COP introduced after crystal growth, the retention time D ₁ in the first heat treatment HT ₁ slightly with longer (e.g., 45 seconds), even if the COP is it is preferable that conditions changed to disappear reliably is there.

When the first heat treatment HT ₁ is performed in the same manner as in Example 1 and the second heat treatment HT ₂ is performed only in an oxidizing atmosphere (Example 9), it can be confirmed that a high-quality DZ layer is formed on the wafer surface layer. It was. When the second heat treatment HT ₂ is performed in an oxidizing atmosphere, the size of the BMD may be smaller even when the holding time D ₂ is the same as that in a non-oxidizing atmosphere. there second heat treatment HT appropriate ₂ of the holding time D ₂ extending (e.g. 6 hours) when it is preferable that the conditions changed to be.

When the atmosphere in the first heat treatment HT ₁ was a non-oxidizing atmosphere (Comparative Example 3), it was confirmed that after this first heat treatment HT ₁ , COP remained on the wafer surface layer by SP2 evaluation and SEM observation. This is presumably because an oxide film was not formed on the wafer surface due to the non-oxidizing atmosphere, and a sufficient amount of interstitial silicon atoms I for annihilating COP was not injected into the wafer.

When the first heat treatment HT ₁ is performed in the same manner as in Example 1 and the second heat treatment HT ₂ is performed only in a non-oxidizing atmosphere (Comparative Example 4), the wafer surface layer (depth region from the wafer surface to about 13 μm) is low. The presence of density oxygen precipitates was confirmed by SP2 evaluation and SEM observation. This is because the oxygen precipitation nuclei (O ₂ V) on the wafer surface layer formed by the first heat treatment HT ₁ remain as they are without disappearing because the interstitial silicon atoms I are not implanted in the second heat treatment HT ₂ . It is thought that it was because.

In addition, instead of performing the first heat treatment HT ₁ and the second heat treatment HT ₂ on the same wafer as the wafer according to the first embodiment, a BMD is grown in a non-oxidizing atmosphere (in Ar) using a batch heat treatment furnace. Heat treatment (1100 ° C. for 4 hours) was performed. FIG. 12 shows the evaluation results using the laser scattering tomograph after the heat treatment, FIG. 13 shows the depth direction distribution of the BMD density, and FIG. 14 shows the depth direction distribution of the BMD size.

From the result of FIG. 12, it was confirmed that the formation state of BMD greatly differs depending on the in-plane position of the wafer. That is, in the region where the OSF ring was formed during crystal growth (region of 100 to 120 mm from the center of the wafer; see FIGS. 3C and 3D), the BMD density was lower than that inside and outside. In the present invention, the crystal growth history is reset by performing heat treatment at 1300 ° C. or higher in the first heat treatment HT ₁ , whereas BMD nucleation is newly performed during cooling, whereas batch-type heat treatment is performed. In the heat treatment by the furnace, it is considered that the crystal growth history remains as it is because the heat treatment temperature is relatively low, and this is because new BMD nucleation is not performed in the OSF ring region.

  Further, as shown in FIG. 13, it was confirmed that the BMD density had a large in-plane variation of one digit or more. Thus, when there is a large in-plane variation in the BMD density, stress concentrates on a specific portion of the wafer during device manufacture, and the wafer is deformed, or crystal defects such as dislocations are newly introduced by the stress. Problems can arise. In addition, the width of the DZ layer on the wafer surface layer was about 10 μm. Unlike the case of the present invention, the width of the DZ layer is difficult to change by adjusting the heat treatment conditions, and there is a problem that it cannot be easily handled for various devices of different types and uses.

  Moreover, as shown in FIG. 14, it has confirmed that the size of BMD in the bulk was biased to the large size side. In the evaluation using the laser scattering tomograph device, when the BMD size exceeds 95 nm, the measurement is saturated, and the size is evaluated to be 95 nm. Therefore, there are actually many BMDs having a size larger than 95 nm. Existing. When the BMD size is increased in this way, when an external stress such as a thermal stress acts on the wafer, the BMD itself becomes a dislocation source, and there is a high possibility that problems such as wafer deformation and overlay will occur.

(4) Wafer depth direction distribution of vacancies and interstitial silicon atoms after first heat treatment In the first heat treatment HT ₁ , the wafer depth direction distribution of vacancies V and interstitial silicon atoms I introduced into the wafer is shown. Simulated. In this simulation, the following equation 1 is used in consideration of diffusion and pair annihilation of vacancies V and interstitial silicon atoms I (K. Nakamura, Ph. D. Thesis, Tohoku University, Sendai. ( 2001)). The first term on the right side corresponds to the flux (diffusion) of vacancies V or interstitial silicon atoms I, and the second term on the right side corresponds to the pair annihilation of vacancies V and interstitial silicon atoms I.

In Equation 1, C is the concentration of vacancies V or interstitial silicon atoms I, t is time, J is the flux of vacancies V or interstitial silicon atoms I, K is the reaction constant of pair annihilation, and each subscript is V is a vacancy, I is an interstitial silicon atom, and eq is a thermal equilibrium concentration. JI _{and V} are expressed by Equation 2, and K is expressed by Equation 3, respectively.

Number 2, the D in equation 3 diffusion constant, a _c is the critical length of the annihilation reaction, the energy barrier of ΔG is annihilation reaction, k _b is the Boltzmann constant, T is the absolute temperature.

  Further, the supersaturation degree of interstitial silicon atoms at the silicon oxide interface can be obtained by the following mathematical formula (S. Dunham, J. Appl. Phys., 71, 685 (1992)).

  A1 and A2 in Equation 4 are parameters determined from the physical property values of oxidation.

  DX / dt in Equation 4 is the oxidation rate of the silicon surface and can be expressed by Equation 5 (BE Deal, AS Grove, J. Appl. Phys., 36, 3770 (1965). )).

In Equation 5, X is the oxide film thickness, k _l is the linear rate constant, and k _p is the parabolic rate constant.

The wafer depth direction distribution of the vacancies V and the interstitial silicon atoms I when the first heat treatment HT ₁ was performed was simulated using the above mathematical formulas. FIG. 15 shows the results when the holding temperature T ₁ is 1350 ° C. and the cooling rate R ₂ is 120 ° C./second (Example 1), the holding temperature T ₁ is 1350 ° C., and the cooling rate R ₂ is 5 ° C./second ( FIG. 16 shows the results when Comparative Example 1) is shown, and FIG. 17 shows the results when the holding temperature T ₁ is 1250 ° C. and the cooling rate R ₂ is 120 ° C./second (Comparative Example 2). Any of the heat treatment is performed in an oxidizing atmosphere, the retention time D ₁ is 30 seconds.

In each figure, the sequence of the first heat treatment HT ₁ is shown at the center, and further, during the temperature rise of the heat treatment, during the holding at the holding temperature T ₁ , and in each stage (A to E or A to D) after cooling. The wafer depth direction distribution of holes V (broken lines) and interstitial silicon atoms I (solid lines) is shown in a graph.

As shown in FIG. 15, in the temperature rising process, vacancies V and interstitial silicon atoms I are injected into the wafer from the wafer surface, and the concentrations of both gradually increase (see AC in this figure). When held at the holding temperature T ₁ (1350 ° C.) for 30 seconds, the vacancies V and interstitial silicon atoms I almost reach the thermal equilibrium concentration at the holding temperature T ₁ over the entire thickness direction of the wafer. The thermal equilibrium concentration at the holding temperature T ₁ is slightly higher in the concentration of the vacancies V than in the interstitial silicon atoms I. The holding temperature T ₁ of the cooling wafers from (120 ° C. / sec), the vacancy V, interstitial silicon atoms I together, although the concentration by diffusion and annihilation decreases, the degree of decrease of the interstitial silicon atoms I Is more prominent. For this reason, after cooling of the wafer, vacancies V predominately remain in the wafer.

It has been found that when the concentration of vacancies V after the first heat treatment HT ₁ is 1 × 10 ¹³ / cm ³ or more, formation of BMD is promoted when the second heat treatment HT ₂ is performed. Under the conditions of the first heat treatment HT ₁ shown in FIG. 15, it is expected that BMD is formed in a depth region of 40 μm or more from the wafer surface where the vacancy concentration is 1 × 10 ¹³ / cm ³ or more. This expectation is substantially consistent with the width of the DZ layer confirmed in FIG.

On the other hand, as shown in FIG. 16, when the cooling rate R ₂ from the holding temperature T ₁ (1350 ° C.) is reduced (5 ° C./second), the holes V up to the end of holding at the holding temperature T ₁ and although the depth direction distribution of the interstitial silicon atoms I is the same as that shown in FIG. 15, due to the cooling rate R ₂ is small, diffusion and annihilation of vacancies V and interstitial silicon atoms I Accordingly, these concentrations further reduced compared to when the cooling rate R ₂ is large. In particular, when attention is paid to the pores V, the concentration is significantly lower than 1 × 10 ¹³ / cm ³ which is a standard of BMD formation, and it is expected that BMD is not formed. This expectation is consistent with the measurement result of the BMD density shown in FIG. 11 (see Comparative Example 1 in this figure).

As shown in FIG. 17, when the holding temperature T ₁ is lowered to 1250 ° C., the concentrations of the vacancies V and the interstitial silicon atoms I after holding at the holding temperature T ₁ for 30 seconds are as shown in FIG. Compared to the case of FIG. 15, both are slightly lower and the concentration of interstitial silicon atoms I is slightly higher than the holes V, unlike the case of FIG. The holding temperature T ₁ of the cooling wafers from (120 ° C. / sec) Then, as compared to the interstitial silicon atoms I is the concentration of vacancies V significantly reduced. The concentration is lower than 1 × 10 ¹³ / cm ³ which is a standard for BMD formation, and it is expected that BMD is not formed. This expectation is consistent with the result (not shown) in which BMD was not formed in the wafer according to Comparative Example 2.

(5) Summary As described above, in the oxidizing atmosphere, the wafer is held within the range of the holding temperature T ₁ of 1300 ° C. or higher and 1400 ° C. or lower, and further the cooling rate R _{2 of} 10 ° C./second or higher and 150 ° C./second or lower. The first heat treatment HT ₁ cooled in step ₁ and the second heat treatment HT ₂ for holding the wafer within the range of the holding temperature T ₂ of 800 ° C. or higher and 1250 ° C. or lower in an oxidizing atmosphere are continuously performed. A BMD for imparting sufficient strength and gettering ability to the bulk can be formed while ensuring the crystal integrity of the DZ layer.

Further, by performing the first heat treatment HT ₁ in an oxidizing atmosphere, interstitial oxygen from the wafer surface is injected into the wafer surface layer, it is possible to secure high strength of the wafer surface layer. Moreover, the first heat treatment HT ₁ by performing a high temperature oxidizing atmosphere, COP was introduced during crystal growth and BMD (BMD nuclei) was disappeared completely, it is possible to reset the crystal growth history. For this reason, wafers with high wafer manufacturing throughput but inferior in-plane uniformity, such as wafers that include an OSF ring in the wafer surface, can be used without problems, and the total including crystal growth and wafer heat treatment can be adopted. The manufacturing cost can be reduced.

Incidentally, the first heat treatment HT ₁ and the second heat treatment HT ₂ sequences described above is merely an example. As long as the problem of the present invention of improving the in-plane uniformity of the crystal quality can be solved while ensuring the strength of the surface layer and the bulk of the wafer, for example, the holding temperature T ₁ is 1300 ° C. or more and 1400 ° C. or less over time. gradually or varied in the range of, between the first heat treatment HT ₁ and the second heat treatment HT ₂ or before and after, it is acceptable or perform additional heat treatment. In addition, a step of peeling the oxide film formed in the oxidizing atmosphere in the middle of a series of steps can be provided.

Claims (3)

A first step of heat-treating a silicon wafer cut from a silicon ingot grown by the Czochralski method at a holding temperature of 1300 ° C. or higher and 1400 ° C. or lower in an oxidizing atmosphere;
A second step of cooling the silicon wafer heat-treated in the first step at a cooling rate of 10 ° C./second or more and 150 ° C./second or less in an oxidizing atmosphere;
A third step of heat-treating the silicon wafer cooled in the second step in an oxidizing atmosphere at a holding temperature of 800 ° C. to 1250 ° C. for 1 hour to 100 hours;
A fourth step of heat-treating the silicon wafer heat-treated in the third step at a holding temperature of 800 ° C. or higher and 1250 ° C. or lower for 1 hour or more and 100 hours or less in a non-oxidizing atmosphere ;
A method for heat treating a silicon wafer. The average size of the cavity defects existing in the silicon wafer in the stage before the first step is a diameter of 80 nm or less and the density of the cavity defects is 100 pieces / cm ³ or more in a spherical equivalent value of the same volume. The silicon wafer heat treatment method according to claim 1 . By varying the cooling rate in the second step, or by changing the retention time in the third step, the silicon according to claim 1 or 2 to change the depth of the denuded from the silicon wafer surface Wafer heat treatment method.