JP2010118471A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010118471A
JP2010118471A JP2008290215A JP2008290215A JP2010118471A JP 2010118471 A JP2010118471 A JP 2010118471A JP 2008290215 A JP2008290215 A JP 2008290215A JP 2008290215 A JP2008290215 A JP 2008290215A JP 2010118471 A JP2010118471 A JP 2010118471A
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inductor
inductor element
semiconductor substrate
semiconductor
semiconductor device
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Tomohiro Matsunaga
朋弘 松永
Yuichi Hirofuji
裕一 広藤
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Panasonic Corp
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Panasonic Corp
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Priority to PCT/JP2009/005557 priority patent/WO2010055614A1/en
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Abstract

<P>PROBLEM TO BE SOLVED: To solve problems of conventional semiconductor devices that it is difficult to control an eddy current induced in a semiconductor substrate because the semiconductor substrate is placed immediately under an inductor element, and it is also difficult to raise a maximum use operating frequency and a Q value because the self resonance frequency of the inductor element cannot be set to a higher value due parasitic capacitance between the semiconductor substrate and inductor wiring. <P>SOLUTION: In a semiconductor device 1, inductor elements 201, 202 are arranged at the external side of a semiconductor substrate 11. Since the semiconductor substrate 11 is not arranged immediately under the inductor elements 201, 202 as explained above, eddy current induction caused by a magnetic field generated in the inductor element can be controlled and parasitic capacitance between the inductor element and GND can be reduced. Therefore, an inductor element loss can be suppressed, the maximum use frequency can be raised, and the Q value can be improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、インダクタ素子を有する半導体装置に関するものである。   The present invention relates to a semiconductor device having an inductor element.

近年、携帯電話等の携帯通信機器の小型化が進められている。携帯通信機器の小型化のために、高周波回路をシリコン集積回路に１チップ化する要求が高まってきている。ところが、高周波回路には、トランジスタ、抵抗および容量に加えて、コイルやトランスといったインダクタ素子が必要であって、シリコン基板上にトランジスタや抵抗等を利用した集積回路と共に、インダクタ素子を形成する方法が開発されている。インダクタ素子は電圧制御型発振回路（VCO；voltage-controlled oscillator）等の発振回路に用いられ、安定な発振周波数および高い周波数の発振波形を得るためにはより高性能なインダクタ素子が求められる。   In recent years, downsizing of mobile communication devices such as mobile phones has been promoted. In order to reduce the size of portable communication devices, there is an increasing demand for a high-frequency circuit to be integrated into a silicon integrated circuit on a single chip. However, a high-frequency circuit requires an inductor element such as a coil and a transformer in addition to a transistor, a resistor, and a capacitor. A method of forming an inductor element together with an integrated circuit using a transistor or a resistor on a silicon substrate is known. Has been developed. The inductor element is used in an oscillation circuit such as a voltage-controlled oscillator (VCO), and a higher-performance inductor element is required to obtain a stable oscillation frequency and a high-frequency oscillation waveform.

インダクタ素子として、半導体基板の表面に形成した絶縁膜上に、アルミニウム等の導電膜を渦巻き状にあるいは巻き線状に形成する方法がある。しかしながら、このような構成では、インダクタ素子の近傍に半導体基板が存在し、インダクタ素子に電流を流した時に発生する磁界の変化を妨げる渦電流がその半導体基板中に発生して、インダクタ素子の特性が損失を伴うことが知られている。   As an inductor element, there is a method in which a conductive film such as aluminum is formed in a spiral shape or a winding shape on an insulating film formed on the surface of a semiconductor substrate. However, in such a configuration, a semiconductor substrate exists in the vicinity of the inductor element, and an eddy current that prevents a change in magnetic field generated when a current is passed through the inductor element is generated in the semiconductor substrate. Is known to be lossy.

即ち、巻き線状に形成された帯状導電層をトランスにおける一次コイルと考えると、不純物を含む半導体基板そのものは抵抗値が低いので高周波領域では短絡された二次コイルのように作用する。この二次コイルの存在によるインダクタ素子の損失は特に高周波領域において顕著に現れるので、半導体基板内の渦電流の発生を防止する為の提案がなされている。例えば、特開平07-183468号には、シリコン基板の表面に複数のＰＮ接合を形成し、その接合により形成される空乏層により、渦電流を抑制することが示されている。つまり、半導体基板の表面に形成される渦電流の経路を複数の空乏層により分断して、渦電流を抑制するという構成が開示されている。この公知例においても、半導体基板の表面に形成される空乏層により渦電流の発生が抑えられることが示されている。   That is, when the band-shaped conductive layer formed in a winding shape is considered as a primary coil in a transformer, the semiconductor substrate containing impurities itself has a low resistance value, and thus acts like a short-circuited secondary coil in a high-frequency region. Since the loss of the inductor element due to the presence of the secondary coil appears prominently in the high frequency region, proposals have been made to prevent the generation of eddy currents in the semiconductor substrate. For example, Japanese Patent Application Laid-Open No. 07-183468 shows that a plurality of PN junctions are formed on the surface of a silicon substrate, and eddy current is suppressed by a depletion layer formed by the junctions. That is, a configuration is disclosed in which the eddy current path formed on the surface of the semiconductor substrate is divided by a plurality of depletion layers to suppress the eddy current. This known example also shows that the generation of eddy currents can be suppressed by the depletion layer formed on the surface of the semiconductor substrate.

図５は、上記公知例のインダクタ素子の構造を示す図である。Ｐ型の半導体基板１１の表面にＮ型の不純物領域１４が形成され、半導体基板１１の表面に複数のＰＮ接合が形成される。そして、半導体基板１１の表面上に形成された絶縁膜１２上に、渦巻き状の導電膜１６が形成される。この導電膜１６の一端１６Ａは、図示しない配線に接続され、また、この導電膜１６の他端１６Ｂは、絶縁膜１２内に形成された下層の配線１８に接続される。導電膜１６の一端１６Ａから他端１６Ｂに向かって図中の矢印２２の方向に電流を流すと、それにより半導体基板１１の表面に垂直な磁界が渦巻き配線内に発生する。   FIG. 5 is a diagram showing the structure of the above-described known inductor element. An N-type impurity region 14 is formed on the surface of the P-type semiconductor substrate 11, and a plurality of PN junctions are formed on the surface of the semiconductor substrate 11. Then, a spiral conductive film 16 is formed on the insulating film 12 formed on the surface of the semiconductor substrate 11. One end 16 A of the conductive film 16 is connected to a wiring (not shown), and the other end 16 B of the conductive film 16 is connected to a lower wiring 18 formed in the insulating film 12. When a current is passed in the direction of the arrow 22 in the figure from one end 16A to the other end 16B of the conductive film 16, a magnetic field perpendicular to the surface of the semiconductor substrate 11 is thereby generated in the spiral wiring.

図５に示された構成では、複数のＰＮ接合により空乏層が形成されるので、半導体基板１１の表面側に空乏層が多く形成され、帯状の導電膜１６からなるインダクタ素子により発生した磁界に対して半導体基板１１内に発生する渦電流が流れる抵抗を高くすることができ、渦電流を抑制し上記の渦電流による損失とインダクタンスの低下を防止することができる。
特開平07-183468号公報 In the configuration shown in FIG. 5, a depletion layer is formed by a plurality of PN junctions. Therefore, a large number of depletion layers are formed on the surface side of the semiconductor substrate 11, and the magnetic field generated by the inductor element composed of the strip-like conductive film 16 is generated. On the other hand, resistance through which eddy current generated in the semiconductor substrate 11 flows can be increased, and eddy current can be suppressed and loss and inductance reduction due to the eddy current can be prevented.
Japanese Unexamined Patent Publication No. 07-183468

しかしながら、従来の半導体装置において、インダクタ素子の下部の半導体基板中に形成される空乏層の幅（厚さ）は1〜10μm程度であるため、インダクタ素子で発生した磁束は空乏層を透過して、空乏層下の半導体基板に到達して半導体基板中に渦電流を誘起させる。そのため、渦電流の発生を抑制することは難しい。また、半導体基板とインダクタ配線との間の寄生容量により、インダクタ素子の自己共振周波数を高くできないため、最大使用周波数を上げることは難しく、また、インダクタ素子の性能の指標となるQ値（Quality Factor）を上げることは難しい。更に、空乏層を半導体基板中に形成する必要があるため、インダクタ下部の半導体基板中に集積回路素子を形成できないという課題があった。これは、半導体基板内に回路を構成するためのレイアウト設計上の大きな制約となるとともに、一般にインダクタは大きな面積を要するため、チップサイズが大きくなるという問題を引き起こす。   However, in the conventional semiconductor device, since the width (thickness) of the depletion layer formed in the semiconductor substrate below the inductor element is about 1 to 10 μm, the magnetic flux generated in the inductor element passes through the depletion layer. And reaches the semiconductor substrate below the depletion layer to induce eddy currents in the semiconductor substrate. Therefore, it is difficult to suppress the generation of eddy current. In addition, since the self-resonance frequency of the inductor element cannot be increased due to the parasitic capacitance between the semiconductor substrate and the inductor wiring, it is difficult to increase the maximum operating frequency. ) Is difficult to raise. Furthermore, since it is necessary to form a depletion layer in the semiconductor substrate, there is a problem that an integrated circuit element cannot be formed in the semiconductor substrate under the inductor. This is a great restriction in layout design for configuring a circuit in a semiconductor substrate, and generally causes a problem that the chip size increases because an inductor requires a large area.

本発明はかかる問題点に鑑みてなされたものであって、インダクタ素子を有する半導体装置において最大使用周波数を高くするとともにQ値を向上させることを目的とする。   The present invention has been made in view of such problems, and an object thereof is to increase the maximum usable frequency and improve the Q value in a semiconductor device having an inductor element.

本発明の半導体装置は、半導体集積回路と半導体集積回路と電気的に接続されたインダクタ素子とを有しており、インダクタ素子は、半導体集積回路を構成する半導体基板よりも外側に配置されている。かかる構成により、インダクタ素子に発生する磁界による半導体基板内での渦電流の誘起が抑制され、インダクタ素子と半導体基板との間の寄生容量が低減されることから、インダクタ素子の損失が抑制され、最大使用周波数が高くなり、Q値が向上する。   A semiconductor device of the present invention includes a semiconductor integrated circuit and an inductor element electrically connected to the semiconductor integrated circuit, and the inductor element is disposed outside a semiconductor substrate constituting the semiconductor integrated circuit. . With this configuration, induction of eddy currents in the semiconductor substrate due to the magnetic field generated in the inductor element is suppressed, and parasitic capacitance between the inductor element and the semiconductor substrate is reduced, so that loss of the inductor element is suppressed, Maximum operating frequency increases and Q value improves.

本発明の半導体装置では、インダクタ素子の長手方向における各端に設けられた端子はどちらも、半導体基板に電気的に接続されていることが好ましい。この場合、半導体基板の表面に導体パッドを有し、インダクタ素子の端子がそれぞれ導体パッドを介して半導体基板に接続されていればよい。また、インダクタ素子は１ターン以上の巻き線からなり、インダクタ素子の端子はインダクタ素子の巻き中心に対して互いに同じ側に配置されていればよい。。   In the semiconductor device of the present invention, it is preferable that both terminals provided at each end in the longitudinal direction of the inductor element are electrically connected to the semiconductor substrate. In this case, a conductor pad may be provided on the surface of the semiconductor substrate, and the terminals of the inductor element may be connected to the semiconductor substrate via the conductor pad. Further, the inductor element is composed of a winding of one turn or more, and the terminals of the inductor element may be arranged on the same side with respect to the winding center of the inductor element. .

本発明の半導体装置では、インダクタ素子は、１ターン以上の巻き線からなることが好ましい。   In the semiconductor device of the present invention, the inductor element is preferably composed of a winding of one turn or more.

本発明の半導体装置では、複数のインダクタ素子を具備することが好ましく、複数のインダクタ素子は誘導結合しないように配置されていることが好ましい。   The semiconductor device of the present invention preferably includes a plurality of inductor elements, and the plurality of inductor elements are preferably arranged so as not to be inductively coupled.

本発明による半導体装置によれば、インダクタ素子の直下に半導体基板がないため、インダクタ素子の磁界により誘起される渦電流が抑制され、インダクタ素子と半導体基板との間の寄生容量が低減されるため、インダクタ素子の損失が抑制され、更に、最大使用周波数が高くなり、Q値が向上するという効果を得ることができる。   According to the semiconductor device of the present invention, since there is no semiconductor substrate directly under the inductor element, eddy currents induced by the magnetic field of the inductor element are suppressed, and parasitic capacitance between the inductor element and the semiconductor substrate is reduced. In addition, the loss of the inductor element can be suppressed, the maximum usable frequency can be increased, and the Q value can be improved.

以下、半導体装置等の実施形態について図面を参照して説明する。なお、実施の形態において同じ符号を付した構成要素は同様の動作を行うので、再度の説明を省略する場合がある。また、本発明は以下に示す構成に限定されない。   Hereinafter, embodiments of a semiconductor device and the like will be described with reference to the drawings. In addition, since the component which attached | subjected the same code | symbol in embodiment performs the same operation | movement, description may be abbreviate | omitted again. Further, the present invention is not limited to the configuration shown below.

（実施の形態１）
本発明の実施の形態１について説明する。 (Embodiment 1)
Embodiment 1 of the present invention will be described.

図１は、本実施の形態に係る半導体装置１の構造図であり、図１（ａ）、図１（ｂ）および図１（ｃ）はそれぞれ斜視図、断面図および上面図である。   FIG. 1 is a structural diagram of a semiconductor device 1 according to the present embodiment. FIGS. 1A, 1B, and 1C are a perspective view, a cross-sectional view, and a top view, respectively.

半導体チップ２０は、絶縁物の内部にインダクタ素子２０１、２０２、ビア２０３および配線２０４を有し、表面に導体パッド２０５を有している。導体パッドとは、金属配線等を形成する導体が露出した領域を示し、ワイヤボンディングを行う際の接続端子や他のチップとの接続端子となる。図２にインダクタ素子２０１、２０２の配置図の一例を示す。インダクタ素子２０１は、同一層の配線を渦巻き状に形成した通常のインダクタであり、インダクタ素子２０２は、２端子のどちらの端子からも渦巻き形状が対象になる差動タイプのインダクタである。インダクタ素子２０１、２０２では、それぞれ、端子（インダクタ素子の長手方向における端に設けられている）がインダクタ素子２０１、２０２の巻き中心に対して互いに同じ側に配置されている。ここでは、便宜上２つの異なる形状のインダクタ素子を並べて示しているが、これは種々の形状のインダクタ素子を対象としていることを示すためであって、実際には一つのインダクタ素子が配置されている場合や同じ形状のインダクタ素子が複数配置されている場合がある。   The semiconductor chip 20 has inductor elements 201 and 202, vias 203 and wirings 204 inside an insulator, and has a conductor pad 205 on the surface. The conductor pad indicates a region where a conductor forming a metal wiring or the like is exposed, and serves as a connection terminal for wire bonding or a connection terminal with another chip. FIG. 2 shows an example of an arrangement diagram of the inductor elements 201 and 202. The inductor element 201 is a normal inductor in which wiring of the same layer is formed in a spiral shape, and the inductor element 202 is a differential type inductor in which a spiral shape is an object from either of two terminals. In the inductor elements 201 and 202, terminals (provided at the ends in the longitudinal direction of the inductor elements) are arranged on the same side with respect to the winding centers of the inductor elements 201 and 202, respectively. Here, for the sake of convenience, two differently shaped inductor elements are shown side by side, but this is to show that the inductor elements are of various shapes, and in fact one inductor element is arranged. In some cases, a plurality of inductor elements having the same shape may be arranged.

インダクタ素子２０１、２０２は互いに誘導結合しないように配置されており、半導体基板１１の主表面に対して垂直方向に磁力線が発生するように配置されている。ここで、半導体基板１１には半導体チップ１０が形成されており、半導体チップ１０はトランジスタ、抵抗および容量などを含む半導体集積回路を構成する半導体チップである。また、誘導結合しない配置とは、一方のインダクタによって誘起される磁力線が実質的に他方のインダクタに起電力を生じさせることがない配置のことを言う。また、複数のインダクタ素子を具備する場合、複数のインダクタ素子の一方の端子を共用する場合がある。更に、図２に示したインダクタ素子以外の形状として、スパイラル部における巻き線の数が異なるインダクタ素子や、平面的な巻き線だけでなく立体的な巻き線からなるインダクタ素子を使用することもできる。また、本実施の形態ではインダクタ素子２０１、２０２は、互いに誘導結合しないように配置されているとしているが、用途により互いに誘導結合するように配置されていても良い。例えば、インダクタ素子２０２の巻き線の中間に引き出し線を設けて、２つのインダクタ素子の巻き線が互いに重なった構成とすれば、双方のインダクタ素子は誘導結合し、一方のインダクタ素子に発生する磁界により他方のインダクタ素子に起電力を生じさせることが可能である。   The inductor elements 201 and 202 are arranged so as not to be inductively coupled to each other, and are arranged so that lines of magnetic force are generated in a direction perpendicular to the main surface of the semiconductor substrate 11. Here, a semiconductor chip 10 is formed on the semiconductor substrate 11, and the semiconductor chip 10 is a semiconductor chip constituting a semiconductor integrated circuit including transistors, resistors, capacitors, and the like. The arrangement without inductive coupling means an arrangement in which the magnetic lines of force induced by one inductor do not substantially generate an electromotive force in the other inductor. When a plurality of inductor elements is provided, one terminal of the plurality of inductor elements may be shared. Furthermore, as a shape other than the inductor element shown in FIG. 2, an inductor element having a different number of windings in the spiral portion, or an inductor element including not only a planar winding but also a three-dimensional winding can be used. . In the present embodiment, the inductor elements 201 and 202 are arranged so as not to be inductively coupled to each other, but may be arranged to be inductively coupled to each other depending on the application. For example, if a lead wire is provided in the middle of the winding of the inductor element 202 and the windings of the two inductor elements overlap each other, both inductor elements are inductively coupled, and a magnetic field generated in one inductor element. Thus, it is possible to generate an electromotive force in the other inductor element.

ここで、本実施の形態に係る半導体装置の構成を簡潔に記すと、GND電位のリードフレーム４０の上に半導体チップ１０および半導体チップ２０が順に設けられている。半導体チップ２０の表面には導体パッド２０５が配置されており、この導体パッド２０５にはそれぞれビア２０３が接続されており、各ビア２０３には配線２０４が長手方向において互いに間隔を開けて接続されている。また、半導体チップ２０の内部に設けられたインダクタ素子２０１、２０２の端子にはそれぞれ引き出し配線２０６が接続されており、引き出し配線２０６にはそれぞれビア２０３が接続されている。   Here, when the configuration of the semiconductor device according to the present embodiment is described briefly, the semiconductor chip 10 and the semiconductor chip 20 are provided in this order on the lead frame 40 having the GND potential. Conductive pads 205 are arranged on the surface of the semiconductor chip 20, and vias 203 are connected to the conductive pads 205, and wirings 204 are connected to the vias 203 at intervals in the longitudinal direction. Yes. In addition, lead wires 206 are connected to the terminals of the inductor elements 201 and 202 provided inside the semiconductor chip 20, and vias 203 are connected to the lead wires 206.

導体パッド２０５および引き出し配線２０６に接続されたビア２０３はそれぞれ金バンプ５０を介して半導体チップ１０の表面に配置された導体パッド１０１に接続されており、これにより、半導体チップ１０と半導体チップ２０とは互いに電気的に接続されている。また、半導体チップ２０の導体パッド２０５はワイヤー３０を介してリードフレーム４０のリード４１に接続されており、これにより、半導体チップ２０とリードフレーム４０とは互いに電気的に接続されている。   Vias 203 connected to the conductor pads 205 and the lead-out wirings 206 are connected to the conductor pads 101 disposed on the surface of the semiconductor chip 10 via the gold bumps 50, respectively. Are electrically connected to each other. Further, the conductor pads 205 of the semiconductor chip 20 are connected to the leads 41 of the lead frame 40 via the wires 30, whereby the semiconductor chip 20 and the lead frame 40 are electrically connected to each other.

そして、本実施の形態に係る半導体装置では、インダクタ素子２０１、２０２が半導体基板よりも外側に配置されるように金バンプ５０を介して導体パッド１０１とビア２０３とを接続することにより、半導体チップ１０に形成されているトランジスタ、抵抗および容量などの各素子と半導体チップ２０のインダクタ素子２０１、２０２および配線２０４とを導体パッド１０１および金バンプ５０を介して電気的に接続している。   In the semiconductor device according to the present embodiment, the semiconductor pad is connected to the via pad 203 via the gold bump 50 so that the inductor elements 201 and 202 are arranged outside the semiconductor substrate, thereby providing a semiconductor chip. 10 are electrically connected to each of the elements such as transistors, resistors, and capacitors formed on the semiconductor chip 20 through the conductor pads 101 and the gold bumps 50.

なお、半導体チップ２０は、インダクタ素子２０１、２０２、ビア２０３、配線２０４、導体パッド２０５および引き出し配線２０６を形成後、裏面を半導体チップ１０と電気的に接続できるようビア２０３の底面が露出するまで薄膜化加工されている。   In the semiconductor chip 20, after the inductor elements 201 and 202, the via 203, the wiring 204, the conductor pad 205, and the lead wiring 206 are formed, the bottom surface of the via 203 is exposed so that the back surface can be electrically connected to the semiconductor chip 10. Thinned.

本実施の形態において得られる効果を以下にまとめて記載する。   The effects obtained in the present embodiment are summarized below.

本実施の形態によれば、インダクタ素子２０１、２０２は半導体基板１１よりも外側に配置されているので、インダクタ素子２０１、２０２の直下には半導体基板１１が配置されない。よって、インダクタ素子２０１、２０２とＧＮＤとの間の距離は、インダクタ素子とリードフレーム４０との間においてインダクタ素子２０１、２０２の直下に半導体基板１１が配置される場合より長くなる。従って、インダクタ素子２０１、２０２の磁界により半導体基板１１に誘起される渦電流が低減され、インダクタ素子２０１、２０２の損失が抑制される。更にインダクタ素子２０１、２０２の配線とGNDとの間の寄生容量値Cが低減されるため、自己共振周波数が高くなり、最大使用周波数が高くなる。また、並列容量成分が低減されることから、インダクタ素子２０１、２０２のQ値が向上する。   According to the present embodiment, since the inductor elements 201 and 202 are disposed outside the semiconductor substrate 11, the semiconductor substrate 11 is not disposed immediately below the inductor elements 201 and 202. Therefore, the distance between the inductor elements 201 and 202 and GND is longer than when the semiconductor substrate 11 is disposed directly below the inductor elements 201 and 202 between the inductor element and the lead frame 40. Therefore, the eddy current induced in the semiconductor substrate 11 by the magnetic field of the inductor elements 201 and 202 is reduced, and the loss of the inductor elements 201 and 202 is suppressed. Furthermore, since the parasitic capacitance value C between the wiring of the inductor elements 201 and 202 and GND is reduced, the self-resonance frequency is increased and the maximum usable frequency is increased. In addition, since the parallel capacitance component is reduced, the Q values of the inductor elements 201 and 202 are improved.

更に、好ましくは、インダクタ素子２０１、２０２直下におけるリードフレーム４０に切り欠きを設けることにより、リードフレーム４０内でも渦電流の発生を抑制することが可能であると共に、インダクタ素子２０１、２０２とリードフレーム４０との間の寄生容量も低減できるので、更なるQ値の向上により特性向上を達成できる。   Further, preferably, by providing a cutout in the lead frame 40 immediately below the inductor elements 201 and 202, it is possible to suppress the generation of eddy currents in the lead frame 40, and the inductor elements 201 and 202 and the lead frame Since the parasitic capacitance between 40 and 40 can be reduced, the characteristics can be improved by further improving the Q value.

なお、本実施の形態によれば、インダクタ素子２０１、２０２直下に半導体チップ１０が配置されない実装レイアウトにすることで、高周波特性に優れたインダクタ素子２０１、２０２を集積化することができる。ちなみに、インダクタ素子２０１、２０２を半導体チップ１０よりも外側に配置しても、インダクタ素子２０１、２０２はリードフレーム４０よりも外側に配置されないので、パッケージを大きくする必要はない。   According to the present embodiment, by adopting a mounting layout in which the semiconductor chip 10 is not disposed immediately below the inductor elements 201 and 202, the inductor elements 201 and 202 having excellent high frequency characteristics can be integrated. Incidentally, even if the inductor elements 201 and 202 are arranged outside the semiconductor chip 10, the inductor elements 201 and 202 are not arranged outside the lead frame 40, so that it is not necessary to enlarge the package.

（実施の形態２）
図３は、本実施の形態２における半導体装置２の構造図であり、図３（ａ）、図３（ｂ）および図３（ｃ）はそれぞれ斜視図、断面図および上面図である。 (Embodiment 2)
FIG. 3 is a structural diagram of the semiconductor device 2 according to the second embodiment. FIGS. 3A, 3B, and 3C are a perspective view, a cross-sectional view, and a top view, respectively.

本実施の形態２では、半導体チップ２０はインダクタ素子２０１、２０２のみが設けられたインダクタ素子の専用のチップであり、半導体チップ１０の表面の導体パッド２０５からワイヤー３０が引き出されている。それ以外の構成については、本実施の形態１と同様で、半導体チップ２０のインダクタ素子２０１、２０２の直下には半導体基板１１が配置されないように、半導体チップ２０が半導体チップ１０の上に配置されている。インダクタ素子２０１、２０２の各端子は、引き出し配線２０６およびビア２０３を介して金バンプ５０に接続されており、その金バンプ５０は半導体チップ１０の表面の周縁に配置された導体パッド２０５に接続されている。これにより、インダクタ素子２０１、２０２のスパイラル部は半導体基板１１よりも外側に配置され、インダクタ素子２０１、２０２の両端の接続配線により半導体基板１１の各素子と電気的に接続している。   In the second embodiment, the semiconductor chip 20 is a dedicated chip for the inductor element provided with only the inductor elements 201 and 202, and the wire 30 is drawn from the conductor pad 205 on the surface of the semiconductor chip 10. Other configurations are the same as those in the first embodiment, and the semiconductor chip 20 is disposed on the semiconductor chip 10 so that the semiconductor substrate 11 is not disposed immediately below the inductor elements 201 and 202 of the semiconductor chip 20. ing. Each terminal of the inductor elements 201 and 202 is connected to the gold bump 50 through the lead wiring 206 and the via 203, and the gold bump 50 is connected to the conductor pad 205 disposed on the peripheral edge of the surface of the semiconductor chip 10. ing. As a result, the spiral portions of the inductor elements 201 and 202 are disposed outside the semiconductor substrate 11 and are electrically connected to each element of the semiconductor substrate 11 by connection wirings at both ends of the inductor elements 201 and 202.

図４を用いて、インダクタ素子専用の半導体チップ２０の構造について説明する。図４（ａ）はインダクタ素子専用の半導体チップ２０の平面概要図で、図３に示したインダクタ素子２０１だけを抜き出して記載しており、インダクタ素子２０１は例えば樹脂材料からなる基板２００の上に設けられており、基板２００は絶縁性の材料であればセラミックのような樹脂以外の材料でも構わない。図４（ｂ）は、図４（ａ）のIVB−IVB’における断面図である。基板２００の一方の表面上には、金属からなるインダクタ素子２０１が形成されている。インダクタ素子２０１の両端にはそれぞれ金属からなる引き出し配線２０６が接続されており、そのうち一方の引き出し配線２０６は基板２００の他方の表面に設けられ、貫通電極２０７を介してインダクタ素子の一方の端部に電気的に接続されている。また、基板２００の他方の表面には、半導体チップ２０を半導体チップ１０に接続するための導体パッド１０１が形成されており、よって、この導体パッド１０１は、上記一方の引き出し配線２０６と同一面に形成されている。   The structure of the semiconductor chip 20 dedicated to the inductor element will be described with reference to FIG. FIG. 4A is a schematic plan view of the semiconductor chip 20 dedicated to the inductor element, in which only the inductor element 201 shown in FIG. 3 is extracted and described. The inductor element 201 is formed on a substrate 200 made of, for example, a resin material. The substrate 200 may be a material other than a resin such as ceramic as long as the substrate 200 is an insulating material. FIG. 4B is a cross-sectional view taken along IVB-IVB ′ of FIG. An inductor element 201 made of metal is formed on one surface of the substrate 200. Lead wires 206 made of metal are connected to both ends of the inductor element 201, one of the lead wires 206 is provided on the other surface of the substrate 200, and one end portion of the inductor element via the through electrode 207. Is electrically connected. Further, a conductor pad 101 for connecting the semiconductor chip 20 to the semiconductor chip 10 is formed on the other surface of the substrate 200. Therefore, the conductor pad 101 is flush with the one lead wiring 206. Is formed.

上記構成の半導体チップ２０の導体パッド１０１は、半導体チップ１０の表面の周縁に設けられている導体パッド２０５に、例えば金バンプ５０を介して接続される。このとき、インダクタ素子２０１、２０２を半導体チップ１０よりも外側に配置することにより、インダクタ素子２０１、２０２に電流が流れた結果、磁界が誘起されても、半導体基板１１の内部に磁界が及ぶことがない。   The conductor pad 101 of the semiconductor chip 20 having the above configuration is connected to the conductor pad 205 provided on the peripheral edge of the surface of the semiconductor chip 10 through, for example, a gold bump 50. At this time, by disposing the inductor elements 201 and 202 outside the semiconductor chip 10, as a result of a current flowing through the inductor elements 201 and 202, the magnetic field reaches the inside of the semiconductor substrate 11 even if a magnetic field is induced. There is no.

以上説明したように、本実施の形態によれば、上記実施の形態１と同じく、インダクタ素子２０１、２０２は半導体基板１１よりも外側に配置されているので、インダクタ素子２０１、２０２の直下には半導体基板１１が配置されない。よって、本実施の形態においても上記実施の形態１と同一の効果を得ることができる。   As described above, according to the present embodiment, the inductor elements 201 and 202 are arranged outside the semiconductor substrate 11 as in the first embodiment. The semiconductor substrate 11 is not disposed. Therefore, also in this embodiment, the same effect as in the first embodiment can be obtained.

（その他の実施の形態）
上記実施の形態１および２では、インダクタ素子において発生する磁界が半導体チップ１０を形成する半導体基板１１の主表面に対して垂直な向きになるようにインダクタ素子を設置したが、磁界が半導体基板１１の主表面に対して平行になるようにインダクタ素子を設置することもできる。すなわち、インダクタ素子は半導体基板１１の端部から側面に突き出し、インダクタ素子を構成する巻き線が半導体基板１１の主表面および突き出した側面とほぼ垂直に形成されていても良い。さらに、インダクタ素子によって誘起される磁界が半導体基板の主表面に対して平行でも垂直でもない角度に傾いて発生しても、その磁界が半導体チップに直接影響を与えることを阻止することができるので、上記実施の形態１および２と同様の効果を得ることができる。 (Other embodiments)
In the first and second embodiments, the inductor element is installed so that the magnetic field generated in the inductor element is oriented perpendicular to the main surface of the semiconductor substrate 11 forming the semiconductor chip 10. It is also possible to install the inductor element so as to be parallel to the main surface. That is, the inductor element may protrude from the end portion of the semiconductor substrate 11 to the side surface, and the windings constituting the inductor element may be formed substantially perpendicular to the main surface of the semiconductor substrate 11 and the protruding side surface. Furthermore, even if the magnetic field induced by the inductor element is generated at an angle that is neither parallel nor perpendicular to the main surface of the semiconductor substrate, the magnetic field can be prevented from directly affecting the semiconductor chip. The same effects as in the first and second embodiments can be obtained.

また、上記実施の形態１および２では、インダクタ素子の全体を半導体基板１１よりも外側に配置することによって、磁界が半導体基板に及ぶことを抑制している。しかし、使用周波数などの半導体装置の仕様により、インダクタ素子の全体を半導体基板１１よりも外側に配置させるのではなく、少なくとも巻き線部の中心を半導体基板１１よりも外側に配置すれば、所定の効果を得ることができる。この場合にも、インダクタ素子からの磁界が及ぶ範囲は半導体チップの周辺部であって、磁界によって誤作動を引き起こす可能性のあるトランジスタ等のレイアウトに制約を与えることはない。   In the first and second embodiments, the entire inductor element is disposed outside the semiconductor substrate 11 to suppress the magnetic field from reaching the semiconductor substrate. However, depending on the specifications of the semiconductor device such as the operating frequency, if the entire inductor element is not arranged outside the semiconductor substrate 11 but at least the center of the winding portion is arranged outside the semiconductor substrate 11, a predetermined value is obtained. An effect can be obtained. Also in this case, the range covered by the magnetic field from the inductor element is the peripheral portion of the semiconductor chip, and does not restrict the layout of transistors or the like that may cause malfunction due to the magnetic field.

さらに、本発明は、以上の実施の形態に限定されることなく、種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることは言うまでもない。   Furthermore, the present invention is not limited to the above-described embodiments, and various modifications are possible, and it goes without saying that these are also included in the scope of the present invention.

以上のように、本発明にかかる半導体装置は、インダクタ素子の磁界により半導体基板に誘起される渦電流が低減し、インダクタ素子の損失が抑制され、インダクタ素子の配線とGNDとの間の寄生容量が低減し、最大使用周波数が高くなるという効果を有するので、高周波の半導体装置として有用である。   As described above, in the semiconductor device according to the present invention, the eddy current induced in the semiconductor substrate by the magnetic field of the inductor element is reduced, the loss of the inductor element is suppressed, and the parasitic capacitance between the wiring of the inductor element and GND is reduced. Is effective as a high-frequency semiconductor device.

実施の形態１の半導体装置の構造図であり、（ａ）はその斜視図、（ｂ）はその断面図、（ｃ）はその上面図BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a structural diagram of a semiconductor device according to a first embodiment, where (a) is a perspective view thereof, (b) is a sectional view thereof, and (c) is a top view thereof. 実施の形態１におけるインダクタンスの配置図Arrangement diagram of inductance in the first embodiment 実施の形態２の半導体装置の構造図であり、（ａ）はその斜視図、（ｂ）はその断面図、（ｃ）はその上面図FIG. 3 is a structural diagram of a semiconductor device according to a second embodiment, where (a) is a perspective view thereof, (b) is a sectional view thereof, and (c) is a top view thereof. 実施の形態２におけるインダクタンスの配置図であり、（ａ）はその上面図、（ｂ）は（ａ）におけるIVB−IVB'線における断面図FIG. 4 is a layout diagram of inductances in Embodiment 2, where (a) is a top view thereof, and (b) is a cross-sectional view taken along the line IVB-IVB ′ in (a). 従来の半導体装置の構造図Structure of conventional semiconductor device

符号の説明Explanation of symbols

１ 半導体装置
２ 半導体装置
１０ 半導体チップ
１１ 半導体基板
２０ 半導体チップ
３０ ワイヤー
４０ リードフレーム
４１ リード
５０ 金バンプ
１０１ 導体パッド
２００ 基板
２０１ インダクタ素子
２０２ インダクタ素子
２０３ ビア
２０４ 配線
２０５ 導体パッド
２０６ 引き出し配線
２０７ 貫通電極 1 Semiconductor device
2 Semiconductor devices
10 Semiconductor chip
11 Semiconductor substrate
20 Semiconductor chip
30 wires
40 Lead frame
41 lead
50 gold bumps
101 Conductor pad
200 substrates
201 Inductor element
202 Inductor element
203 Via
204 Wiring
205 Conductor pad
206 Lead-out wiring
207 Through electrode

Claims (7)

半導体集積回路と、前記半導体集積回路と電気的に接続されたインダクタ素子とを有し、
前記インダクタ素子は、前記半導体集積回路を構成する半導体基板よりも外側に配置されていることを特徴とする半導体装置。 A semiconductor integrated circuit, and an inductor element electrically connected to the semiconductor integrated circuit,
The semiconductor device according to claim 1, wherein the inductor element is disposed outside a semiconductor substrate constituting the semiconductor integrated circuit. 前記インダクタ素子の長手方向における各端に設けられた端子はどちらも、前記半導体基板に電気的に接続されていることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein both terminals provided at each end in the longitudinal direction of the inductor element are electrically connected to the semiconductor substrate. 前記インダクタ素子は、１ターン以上の巻き線からなることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein the inductor element includes a winding of one turn or more. 前記半導体基板の表面に設けられた導体パッドを有し、
前記インダクタ素子の前記端子は、それぞれ、前記導体パッドを介して前記半導体基板に接続されていることを特徴とする請求項２に記載の半導体装置。 A conductor pad provided on the surface of the semiconductor substrate;
The semiconductor device according to claim 2, wherein each of the terminals of the inductor element is connected to the semiconductor substrate via the conductor pad. 前記インダクタ素子は、１ターン以上の巻き線からなり、
前記インダクタ素子の前記端子は、前記インダクタ素子の巻き中心に対して互いに同じ側に配置されていることを特徴とする請求項２に記載の半導体装置。 The inductor element comprises a winding of one turn or more,
The semiconductor device according to claim 2, wherein the terminals of the inductor element are disposed on the same side with respect to a winding center of the inductor element. 前記インダクタ素子を複数有していることを特徴とする請求項１に記載の半導体装置。   The semiconductor device according to claim 1, comprising a plurality of the inductor elements. 複数のインダクタ素子は互いに誘導結合しないように配置されていることを特徴とする請求項６に記載の半導体装置。   The semiconductor device according to claim 6, wherein the plurality of inductor elements are arranged so as not to be inductively coupled to each other.
JP2008290215A 2008-11-12 2008-11-12 Semiconductor device Pending JP2010118471A (en)

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